mirror of
https://github.com/hathach/tinyusb.git
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refractor dcd_controller_reset & hcd_controller_reset to hal_controller_reset
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024858a605
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@ -60,7 +60,7 @@
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// CONTROLLER CONFIGURATION
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// CONTROLLER CONFIGURATION
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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#define TUSB_CFG_CONTROLLER_0_MODE (TUSB_MODE_DEVICE)
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#define TUSB_CFG_CONTROLLER_0_MODE (TUSB_MODE_DEVICE)
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#define TUSB_CFG_CONTROLLER_1_MODE (TUSB_MODE_NONE)
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#define TUSB_CFG_CONTROLLER_1_MODE (TUSB_MODE_DEVICE)
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// HOST CONFIGURATION
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// HOST CONFIGURATION
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@ -81,7 +81,7 @@
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// DEVICE CONFIGURATION
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// DEVICE CONFIGURATION
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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#define TUSB_CFG_DEVICE_FULLSPEED 1 // TODO refractor
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#define TUSB_CFG_DEVICE_FULLSPEED 0 // TODO refractor
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#define TUSB_CFG_DEVICE_USE_ROM_DRIVER 0
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#define TUSB_CFG_DEVICE_USE_ROM_DRIVER 0
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@ -371,7 +371,7 @@ app_descriptor_configuration_t app_tusb_desc_configuration =
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.bDescriptorType = TUSB_DESC_TYPE_ENDPOINT,
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.bDescriptorType = TUSB_DESC_TYPE_ENDPOINT,
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.bEndpointAddress = 0x83,
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.bEndpointAddress = 0x83,
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.bmAttributes = { .xfer = TUSB_XFER_BULK },
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.bmAttributes = { .xfer = TUSB_XFER_BULK },
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.wMaxPacketSize = { .size = 64 /*512*/ },
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.wMaxPacketSize = { .size = TUSB_CFG_DEVICE_FULLSPEED ? 64 : 512 },
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.bInterval = 1
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.bInterval = 1
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},
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},
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@ -381,7 +381,7 @@ app_descriptor_configuration_t app_tusb_desc_configuration =
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.bDescriptorType = TUSB_DESC_TYPE_ENDPOINT,
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.bDescriptorType = TUSB_DESC_TYPE_ENDPOINT,
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.bEndpointAddress = 0x03,
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.bEndpointAddress = 0x03,
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.bmAttributes = { .xfer = TUSB_XFER_BULK },
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.bmAttributes = { .xfer = TUSB_XFER_BULK },
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.wMaxPacketSize = { .size = 64 /*512*/ },
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.wMaxPacketSize = { .size = TUSB_CFG_DEVICE_FULLSPEED ? 64 : 512 },
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.bInterval = 1
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.bInterval = 1
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},
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},
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#endif
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#endif
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@ -76,8 +76,8 @@
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#define TUSB_CFG_HOST_HID_KEYBOARD 0
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#define TUSB_CFG_HOST_HID_KEYBOARD 0
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#define TUSB_CFG_HOST_HID_MOUSE 0
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#define TUSB_CFG_HOST_HID_MOUSE 0
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#define TUSB_CFG_HOST_HID_GENERIC 0
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#define TUSB_CFG_HOST_HID_GENERIC 0
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#define TUSB_CFG_HOST_MSC 0
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#define TUSB_CFG_HOST_MSC 1
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#define TUSB_CFG_HOST_CDC 1
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#define TUSB_CFG_HOST_CDC 0
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#define TUSB_CFG_HOST_CDC_RNDIS 0
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#define TUSB_CFG_HOST_CDC_RNDIS 0
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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@ -75,7 +75,6 @@ tusb_error_t dcd_init(void) ATTR_WARN_UNUSED_RESULT;
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void dcd_isr(uint8_t coreid);
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void dcd_isr(uint8_t coreid);
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//------------- Controller API -------------//
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//------------- Controller API -------------//
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tusb_error_t dcd_controller_reset(uint8_t coreid) ATTR_WARN_UNUSED_RESULT;
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void dcd_controller_connect(uint8_t coreid);
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void dcd_controller_connect(uint8_t coreid);
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void dcd_controller_disconnect(uint8_t coreid);
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void dcd_controller_disconnect(uint8_t coreid);
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void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr);
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void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr);
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@ -166,21 +166,21 @@ ATTR_ALIGNED(2048) dcd_data_t dcd_data TUSB_CFG_ATTR_USBRAM;
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// CONTROLLER API
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// CONTROLLER API
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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tusb_error_t dcd_controller_reset(uint8_t coreid)
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//tusb_error_t dcd_controller_reset(uint8_t coreid)
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{
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//{
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volatile uint32_t * p_reg_usbcmd;
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// volatile uint32_t * p_reg_usbcmd;
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p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
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// NXP chip powered with non-host mode --> sts bit is not correctly reflected
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(*p_reg_usbcmd) |= BIT_(1); // TODO refractor reset controller
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// timeout_timer_t timeout;
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// timeout_set(&timeout, 2); // should not take longer the time to stop controller
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while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !timeout_expired(&timeout)*/) {}
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//
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//
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// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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// p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
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return TUSB_ERROR_NONE;
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//// NXP chip powered with non-host mode --> sts bit is not correctly reflected
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}
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// (*p_reg_usbcmd) |= BIT_(1); // TODO refractor reset controller
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//
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//// timeout_timer_t timeout;
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//// timeout_set(&timeout, 2); // should not take longer the time to stop controller
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// while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !timeout_expired(&timeout)*/) {}
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////
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//// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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// return TUSB_ERROR_NONE;
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//}
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void dcd_controller_connect(uint8_t coreid)
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void dcd_controller_connect(uint8_t coreid)
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{
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{
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@ -102,8 +102,6 @@ tusb_error_t usbd_init (void)
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ASSERT_STATUS ( dcd_init() );
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ASSERT_STATUS ( dcd_init() );
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dcd_controller_connect(0); // TODO USB1
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return TUSB_ERROR_NONE;
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return TUSB_ERROR_NONE;
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}
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}
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@ -54,9 +54,25 @@ enum {
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LPC43XX_USBMODE_VBUS_HIGH = 1
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LPC43XX_USBMODE_VBUS_HIGH = 1
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};
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};
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static tusb_error_t hal_controller_reset(uint8_t coreid)
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{ // TODO timeout expired to prevent trap
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volatile uint32_t * p_reg_usbcmd;
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p_reg_usbcmd = (coreid ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
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// NXP chip powered with non-host mode --> sts bit is not correctly reflected
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(*p_reg_usbcmd) |= BIT_(1);
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// timeout_timer_t timeout;
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// timeout_set(&timeout, 2); // should not take longer the time to stop controller
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while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !timeout_expired(&timeout)*/) {}
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//
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// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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return TUSB_ERROR_NONE;
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}
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tusb_error_t hal_init(void)
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tusb_error_t hal_init(void)
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{
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{
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//------------- USB0 Clock -------------//
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//------------- USB0 -------------//
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#if TUSB_CFG_CONTROLLER_0_MODE
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#if TUSB_CFG_CONTROLLER_0_MODE
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CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
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CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
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ASSERT_INT( CGU_ERROR_SUCCESS, CGU_SetPLL0(), TUSB_ERROR_FAILED); /* the usb core require output clock = 480MHz */
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ASSERT_INT( CGU_ERROR_SUCCESS, CGU_SetPLL0(), TUSB_ERROR_FAILED); /* the usb core require output clock = 480MHz */
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@ -65,25 +81,24 @@ tusb_error_t hal_init(void)
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LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
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LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
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// reset controller & set role
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// reset controller & set role
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hal_controller_reset(0);
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#if TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_HOST
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#if TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_HOST
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hcd_controller_reset(0); // TODO where to place prototype
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LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
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LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
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#else // TODO OTG
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#else // TODO OTG
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dcd_controller_reset(0);
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LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
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LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
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LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
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LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
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#if TUSB_CFG_DEVICE_FULLSPEED // TODO for easy testing
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#if TUSB_CFG_DEVICE_FULLSPEED // TODO for easy testing
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LPC_USB0->PORTSC1_D |= (1<<24); // force full speed
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LPC_USB0->PORTSC1_D |= (1<<24); // force full speed
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#endif
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#endif
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dcd_controller_connect(0);
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#endif
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#endif
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hal_interrupt_enable(0);
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hal_interrupt_enable(0);
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#endif
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#endif
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//------------- USB1 Clock, only use on-chip FS PHY -------------//
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//------------- USB1 -------------//
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#if TUSB_CFG_CONTROLLER_1_MODE
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#if TUSB_CFG_CONTROLLER_1_MODE
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// TODO confirm whether device mode require P2_5 or not
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// Host require to config P2_5, TODO confirm whether device mode require P2_5 or not
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scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); // USB1_VBUS monitor presence, must be high for bus reset occur
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scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); // USB1_VBUS monitor presence, must be high for bus reset occur
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/* connect CLK_USB1 to 60 MHz clock */
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/* connect CLK_USB1 to 60 MHz clock */
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@ -91,11 +106,11 @@ tusb_error_t hal_init(void)
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//LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
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//LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
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LPC_SCU->SFSUSB = (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY
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LPC_SCU->SFSUSB = (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY
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hal_controller_reset(1);
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#if TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST
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#if TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST
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hcd_controller_reset(1); // TODO where to place prototype
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LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
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LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
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#else // TODO OTG
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#else // TODO OTG
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// dcd_controller_reset(1);
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LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
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LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
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dcd_controller_connect(1);
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dcd_controller_connect(1);
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#endif
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#endif
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@ -277,19 +277,19 @@ static tusb_error_t hcd_controller_stop(uint8_t hostid)
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return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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}
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}
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tusb_error_t hcd_controller_reset(uint8_t hostid)
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//tusb_error_t hcd_controller_reset(uint8_t hostid)
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{
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//{
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ehci_registers_t* const regs = get_operational_register(hostid);
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// ehci_registers_t* const regs = get_operational_register(hostid);
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timeout_timer_t timeout;
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// timeout_timer_t timeout;
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//
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// NXP chip powered with non-host mode --> sts bit is not correctly reflected
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//// NXP chip powered with non-host mode --> sts bit is not correctly reflected
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regs->usb_cmd_bit.reset = 1;
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// regs->usb_cmd_bit.reset = 1;
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//
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timeout_set(&timeout, 2); // should not take longer the time to stop controller
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// timeout_set(&timeout, 2); // should not take longer the time to stop controller
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while( regs->usb_cmd_bit.reset && !timeout_expired(&timeout)) {}
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// while( regs->usb_cmd_bit.reset && !timeout_expired(&timeout)) {}
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//
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return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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// return timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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}
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//}
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// CONTROL PIPE API
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// CONTROL PIPE API
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@ -469,9 +469,6 @@ typedef struct {
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}device[TUSB_CFG_HOST_DEVICE_MAX];
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}device[TUSB_CFG_HOST_DEVICE_MAX];
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}ehci_data_t;
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}ehci_data_t;
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//For NXP's MCU, host/device mode must be set immediately after a reset
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tusb_error_t hcd_controller_reset(uint8_t hostid) ATTR_WARN_UNUSED_RESULT;
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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