Embedded/tinyusb
1
0
Fork 0
mirror of https://github.com/hathach/tinyusb.git synced 2025-01-31 05:52:55 +08:00
Code Issues Packages Projects Releases Wiki Activity

add test & code for open bulk transfer to hcd_pipe_open()

Browse Source
This commit is contained in:
hathach 2013-03-05 23:08:00 +07:00
parent c0bbc2aded
commit b3775b631b
7 changed files with 133 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
tests/test/host/ehci/test_ehci_pipe.c
View File

@ -53,7 +53,7 @@ usbh_device_info_t usbh_device_info_pool[TUSB_CFG_HOST_DEVICE_MAX+1];
LPC_USB0_Type lpc_usb0;
LPC_USB1_Type lpc_usb1;
uint8_t const max_packet_size = 64;
uint8_t const control_max_packet_size = 64;
uint8_t dev_addr;
uint8_t hub_addr;
uint8_t hub_port;
@ -61,6 +61,16 @@ uint8_t hostid;
ehci_qhd_t *async_head;
tusb_descriptor_endpoint_t const desc_ept_bulk_in =
{
.bLength = sizeof(tusb_descriptor_endpoint_t),
.bDescriptorType = TUSB_DESC_ENDPOINT,
.bEndpointAddress = 0x81,
.bmAttributes = { .xfer = TUSB_XFER_BULK },
.wMaxPacketSize = 64,
.bInterval = 0
};
//--------------------------------------------------------------------+
// Setup/Teardown + helper declare
//--------------------------------------------------------------------+
@ -96,21 +106,14 @@ void tearDown(void)
//--------------------------------------------------------------------+
// CONTROL PIPE
//--------------------------------------------------------------------+
void verify_control_open_qhd(ehci_qhd_t *p_qhd)
void verify_open_qhd(ehci_qhd_t *p_qhd)
{
TEST_ASSERT_EQUAL(dev_addr, p_qhd->device_address);
TEST_ASSERT_FALSE(p_qhd->inactive_next_xact);
TEST_ASSERT_EQUAL(0, p_qhd->endpoint_number);
TEST_ASSERT_EQUAL(1, p_qhd->data_toggle_control);
TEST_ASSERT_EQUAL(max_packet_size, p_qhd->max_package_size);
TEST_ASSERT_EQUAL(0, p_qhd->nak_count_reload); // TODO NAK Reload disable
TEST_ASSERT_EQUAL(0, p_qhd->smask);
TEST_ASSERT_EQUAL(0, p_qhd->cmask);
TEST_ASSERT_EQUAL(hub_addr, p_qhd->hub_address);
TEST_ASSERT_EQUAL(hub_port, p_qhd->hub_port);
TEST_ASSERT_EQUAL(1, p_qhd->mult);
TEST_ASSERT(p_qhd->qtd_overlay.next.terminate);
TEST_ASSERT(p_qhd->qtd_overlay.alternate.terminate);
TEST_ASSERT(p_qhd->qtd_overlay.halted);
@ -120,13 +123,44 @@ void verify_control_open_qhd(ehci_qhd_t *p_qhd)
TEST_ASSERT_NULL(p_qhd->p_qtd_list);
}
void verify_bulk_open_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint)
{
verify_open_qhd(p_qhd);
TEST_ASSERT_FALSE(p_qhd->head_list_flag);
TEST_ASSERT_EQUAL(desc_endpoint->wMaxPacketSize, p_qhd->max_package_size);
TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x0F, p_qhd->endpoint_number);
TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control);
TEST_ASSERT_EQUAL(0, p_qhd->smask);
TEST_ASSERT_EQUAL(0, p_qhd->cmask);
// TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TEST highspeed bulk/control OUT
TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x80 ? EHCI_PID_IN : EHCI_PID_OUT, p_qhd->pid_non_control);
//------------- async list check -------------//
TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(async_head->next.address));
TEST_ASSERT_FALSE(async_head->next.terminate);
TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, async_head->next.type);
}
void verify_control_open_qhd(ehci_qhd_t *p_qhd)
{
verify_open_qhd(p_qhd);
TEST_ASSERT_EQUAL(control_max_packet_size, p_qhd->max_package_size);
TEST_ASSERT_EQUAL(0, p_qhd->endpoint_number);
TEST_ASSERT_EQUAL(1, p_qhd->data_toggle_control);
TEST_ASSERT_EQUAL(0, p_qhd->smask);
TEST_ASSERT_EQUAL(0, p_qhd->cmask);
}
void test_control_open_addr0_qhd_data(void)
{
dev_addr = 0;
ehci_qhd_t * const p_qhd = async_head;
hcd_pipe_control_open(dev_addr, max_packet_size);
hcd_pipe_control_open(dev_addr, control_max_packet_size);
verify_control_open_qhd(p_qhd);
TEST_ASSERT(p_qhd->head_list_flag);
@ -136,7 +170,7 @@ void test_control_open_qhd_data(void)
{
ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr].control.qhd;
hcd_pipe_control_open(dev_addr, max_packet_size);
hcd_pipe_control_open(dev_addr, control_max_packet_size);
verify_control_open_qhd(p_qhd);
TEST_ASSERT_FALSE(p_qhd->head_list_flag);
@ -153,7 +187,7 @@ void test_control_open_highspeed(void)
usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_HIGH;
hcd_pipe_control_open(dev_addr, max_packet_size);
hcd_pipe_control_open(dev_addr, control_max_packet_size);
TEST_ASSERT_EQUAL(TUSB_SPEED_HIGH, p_qhd->endpoint_speed);
TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
@ -165,7 +199,7 @@ void test_control_open_non_highspeed(void)
usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_FULL;
hcd_pipe_control_open(dev_addr, max_packet_size);
hcd_pipe_control_open(dev_addr, control_max_packet_size);
TEST_ASSERT_EQUAL(TUSB_SPEED_FULL, p_qhd->endpoint_speed);
TEST_ASSERT_TRUE(p_qhd->non_hs_control_endpoint);
@ -174,28 +208,20 @@ void test_control_open_non_highspeed(void)
//--------------------------------------------------------------------+
// BULK PIPE
//--------------------------------------------------------------------+
void test_open_bulk_qhd_data(void)
void test_open_bulk_in_qhd_data(void)
{
// dev_addr = 1;
// for (uint8_t i=0; i<CONTROLLER_HOST_NUMBER; i++)
// {
// uint8_t hostid = i + TEST_CONTROLLER_HOST_START_INDEX;
// ehci_qhd_t * const async_head = get_async_head( hostid );
// ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr].control.qhd;
//
// usbh_device_info_pool[dev_addr].core_id = hostid;
// usbh_device_info_pool[dev_addr].hub_addr = hub_addr;
// usbh_device_info_pool[dev_addr].hub_port = hub_port;
//
// hcd_pipe_open(dev_addr, &desc_configuration.keyboard_endpoint);
//
// verify_control_open_qhd(p_qhd);
// TEST_ASSERT_FALSE(p_qhd->head_list_flag);
//
// //------------- async list check -------------//
// TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(async_head->next.address));
// TEST_ASSERT_FALSE(async_head->next.terminate);
// TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, async_head->next.type);
// }
ehci_qhd_t *p_qhd;
tusb_descriptor_endpoint_t const * desc_endpoint = &desc_ept_bulk_in;
pipe_handle_t pipe_hdl;
pipe_hdl = hcd_pipe_open(dev_addr, desc_endpoint);
p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
verify_bulk_open_qhd(p_qhd, desc_endpoint);
//------------- async list check -------------//
TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(async_head->next.address));
TEST_ASSERT_FALSE(async_head->next.terminate);
TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, async_head->next.type);
}

4
tests/test/host/test_hid_host_keyboard.c
View File

@ -67,7 +67,7 @@ void setUp(void)
memset(&report, 0, sizeof(tusb_keyboard_report_t));
keyboard_info_pool[0].instance_count = 0;
keyboard_info_pool[0].instance[0].pipe_in = 1;
keyboard_info_pool[0].instance[0].pipe_in = (pipe_handle_t) { .dev_addr = 1, .xfer_type = TUSB_XFER_INTERRUPT, .index = 1};
keyboard_info_pool[0].instance[0].report_size = sizeof(tusb_keyboard_report_t);
kbd_descriptor = ((tusb_descriptor_interface_t)
@ -163,7 +163,7 @@ void test_keyboard_get_invalid_para()
void test_keyboard_get_class_not_supported()
{
tusbh_device_status_get_IgnoreAndReturn(TUSB_DEVICE_STATUS_READY);
keyboard_info_pool[device_hdl].instance[0].pipe_in = 0;
keyboard_info_pool[device_hdl].instance[0].pipe_in = (pipe_handle_t) { 0 };
TEST_ASSERT_EQUAL(TUSB_ERROR_CLASS_DEVICE_DONT_SUPPORT, tusbh_hid_keyboard_get(device_hdl, instance_num, &report));
}

2
tinyusb/class/hid_host.c
View File

@ -71,7 +71,7 @@ tusb_error_t tusbh_hid_keyboard_get(tusb_handle_device_t const device_hdl, uint8
p_kbd = &keyboard_info_pool[device_hdl].instance[instance_num];
ASSERT(0 != p_kbd->pipe_in, TUSB_ERROR_CLASS_DEVICE_DONT_SUPPORT);
ASSERT(0 != p_kbd->pipe_in.dev_addr, TUSB_ERROR_CLASS_DEVICE_DONT_SUPPORT);
ASSERT_INT(PIPE_STATUS_COMPLETE, usbh_pipe_status_get(p_kbd->pipe_in), TUSB_ERROR_CLASS_DATA_NOT_AVAILABLE);

7
tinyusb/core/tusb_types.h
View File

@ -73,13 +73,6 @@ typedef enum {
TUSB_DIR_DEV_TO_HOST = 1
}tusb_direction_t;
/// TBD
typedef enum {
TUSB_PID_SETUP,
TUSB_PID_IN,
TUSB_PID_OUT
}tusb_pid_t;
/// USB Descriptor Types (section 9.4 table 9-5)
typedef enum {
TUSB_DESC_DEVICE =1 , ///< 1

57
tinyusb/host/ehci/ehci.c
View File

@ -262,7 +262,7 @@ tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
}else
{
p_qhd = &ehci_data.device[dev_addr].control.qhd;
p_qhd->head_list_flag = 0; // make sure it is still head of list
p_qhd->head_list_flag = 0;
}
p_qhd->device_address = dev_addr;
@ -308,9 +308,60 @@ tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
//}
//
pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_descriptor_endpoint_t const * endpoint_desc)
pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_descriptor_endpoint_t const * p_endpoint_desc)
{
return TUSB_ERROR_NONE;
pipe_handle_t const null_handle = { .dev_addr = 0, .xfer_type = 0, .index = 0 };
if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_BULK)
{
uint8_t index=0;
while( index<EHCI_MAX_QHD && ehci_data.device[dev_addr].qhd[index].used )
{
index++;
}
ASSERT( index < EHCI_MAX_QHD, null_handle);
ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr].qhd[index];
memclr_(p_qhd, sizeof(ehci_qhd_t));
p_qhd->device_address = dev_addr;
p_qhd->inactive_next_xact = 0;
p_qhd->endpoint_number = p_endpoint_desc->bEndpointAddress & 0x0F;
p_qhd->endpoint_speed = usbh_device_info_pool[dev_addr].speed;
p_qhd->data_toggle_control = 0;
p_qhd->head_list_flag = 0;
p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize;
p_qhd->non_hs_control_endpoint = 0;
p_qhd->nak_count_reload = 0;
p_qhd->smask = 0;
p_qhd->cmask = 0;
p_qhd->hub_address = usbh_device_info_pool[dev_addr].hub_addr;
p_qhd->hub_port = usbh_device_info_pool[dev_addr].hub_port;
p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet
//------------- inactive when just opened -------------//
p_qhd->qtd_overlay.next.terminate = 1;
p_qhd->qtd_overlay.alternate.terminate = 1;
p_qhd->qtd_overlay.halted = 1;
//------------- HCD Management Data -------------//
p_qhd->used = 1;
p_qhd->p_qtd_list = NULL;
p_qhd->pid_non_control = (p_endpoint_desc->bEndpointAddress & 0x80) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint
//------------- insert to async list -------------//
// TODO disable async list first if got error
ehci_qhd_t * const async_head = get_async_head(usbh_device_info_pool[dev_addr].core_id);
p_qhd->next = async_head->next;
async_head->next.address = (uint32_t) p_qhd;
async_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
return (pipe_handle_t) { .dev_addr = dev_addr, .xfer_type = p_endpoint_desc->bmAttributes.xfer, .index = index};
}
return null_handle;
}
#endif

12
tinyusb/host/ehci/ehci.h
View File

@ -101,6 +101,13 @@ enum ehci_queue_element_type_{
EHCI_QUEUE_ELEMENT_FSTN ///< 3
};
/// TBD
enum tusb_pid_{
EHCI_PID_OUT = 0 ,
EHCI_PID_IN ,
EHCI_PID_SETUP
};
/// Link pointer
typedef union {
uint32_t address;
@ -189,8 +196,9 @@ typedef struct {
/// Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes
/// thus there are 16 bytes padding free that we can make use of.
uint8_t used;
uint8_t pid_non_control;
uint8_t list_index;
uint8_t reserved[2];
uint8_t reserved;
ehci_qtd_t *p_qtd_list; /* used as TD head to clean up TD chain when transfer done */ // TODO consider using ehci_link_t (terminate bit)
@ -427,7 +435,6 @@ typedef volatile struct {
// EHCI Data Organization
//--------------------------------------------------------------------+
typedef struct {
// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool
struct {
ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; /// head qhd of async list, also is used as control endpoint for address 0
@ -436,6 +443,7 @@ typedef struct {
}controller; ///< Static Interrupt Queue Head
struct {
// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool
struct {
ehci_qhd_t qhd;
ehci_qtd_t qtd[3];

7
tinyusb/host/hcd.h
View File

@ -60,8 +60,11 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
typedef uint32_t pipe_handle_t;
typedef struct {
uint8_t dev_addr;
uint8_t xfer_type;
uint8_t index;
} pipe_handle_t;
//--------------------------------------------------------------------+
// USBH-HCD API