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add os FromISR support for freeRTOS
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@ -56,8 +56,6 @@ extern "C" {
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#if 0
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// Helper to determine if we are in ISR to use ISR API (only cover ARM Cortex)
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// Note: Actually we don't need this since any event signal (queue send, semaphore post)
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// is done in ISR, other event receive (queue receive, semaphore wait ) in in thread
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static inline bool in_isr(void)
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{
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return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
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@ -98,11 +96,14 @@ static inline void osal_queue_receive (osal_queue_t const queue_hdl, void *p_dat
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(*p_error) = ( xQueueReceive(queue_hdl, p_data, ticks) ? TUSB_ERROR_NONE : TUSB_ERROR_OSAL_TIMEOUT);
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}
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static inline bool osal_queue_send_isr(osal_queue_t const queue_hdl, void const * data)
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{
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return xQueueSendToFrontFromISR(queue_hdl, data, NULL);
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}
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static inline bool osal_queue_send(osal_queue_t const queue_hdl, void const * data)
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{
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// queue send used by msc device for retrying read10/write10
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verify_breakpoint();
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return xQueueSendToFrontFromISR(queue_hdl, data, NULL);
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return xQueueSendToFront(queue_hdl, data, OSAL_TIMEOUT_WAIT_FOREVER) == pdTRUE;
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}
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static inline void osal_queue_flush(osal_queue_t const queue_hdl)
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@ -122,11 +123,17 @@ static inline osal_semaphore_t osal_semaphore_create(uint32_t max, uint32_t init
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}
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// TODO add timeout (with instant return from ISR option) for semaphore post & queue send
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static inline bool osal_semaphore_post_isr(osal_semaphore_t sem_hdl)
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{
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return xSemaphoreGiveFromISR(sem_hdl, NULL) == pdTRUE;
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}
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static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl)
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{
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return xSemaphoreGiveFromISR(sem_hdl, NULL);
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return xSemaphoreGive(sem_hdl) == pdTRUE;
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}
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static inline void osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec, tusb_error_t *p_error)
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{
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uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec);
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