change ra bsp to match fsp generated directory

hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h

@@ -1,7 +1,13 @@
 /* generated configuration header file - do not edit */
 #ifndef R_IOPORT_CFG_H_
 #define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
 
+#ifdef __cplusplus
+}
+#endif
 #endif /* R_IOPORT_CFG_H_ */

hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h

@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */

hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h

@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */

hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h

@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */

hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h

@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */

hw/bsp/ra/boards/ra6m5_ek/board.cmake

@@ -2,6 +2,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
 set(MCU_VARIANT ra6m5)
 
 set(JLINK_DEVICE R7FA6M5BH)
+set(JLINK_OPTION "-USB 000831915224")
 
 # Device port default to PORT1 Highspeed
 if (NOT DEFINED PORT)

hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h

@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */

hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h

@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */

hw/bsp/ra/family.cmake

@@ -44,8 +44,9 @@ function(add_board_target BOARD_TARGET)
     target_include_directories(${BOARD_TARGET} PUBLIC
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg/bsp
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg/bsp
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen
       ${CMSIS_DIR}/CMSIS/Core/Include
       ${FSP_RA}/inc
       ${FSP_RA}/inc/api