mirror of
https://github.com/hathach/tinyusb.git
synced 2025-01-17 05:32:55 +08:00
ra8m1_ek led and button works
This commit is contained in:
hathach
parent
4b39ecc519
commit
c79890c359
@ -2,7 +2,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
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set(MCU_VARIANT ra6m5)
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set(JLINK_DEVICE R7FA6M5BH)
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set(JLINK_OPTION "-USB 000831915224")
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#set(JLINK_OPTION "-USB 000831915224")
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# Device port default to PORT1 Highspeed
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if (NOT DEFINED PORT)
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8
hw/bsp/ra/boards/ra8m1_ek/board.cmake
Normal file
8
hw/bsp/ra/boards/ra8m1_ek/board.cmake
Normal file
@ -0,0 +1,8 @@
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set(CMAKE_SYSTEM_PROCESSOR cortex-m85 CACHE INTERNAL "System Processor")
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set(MCU_VARIANT ra8m1)
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set(JLINK_DEVICE R7FA8M1AH)
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#set(JLINK_OPTION "-USB 001083115236")
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function(update_board TARGET)
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endfunction()
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42
hw/bsp/ra/boards/ra8m1_ek/board.h
Normal file
42
hw/bsp/ra/boards/ra8m1_ek/board.h
Normal file
@ -0,0 +1,42 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LED_STATE_ON 1
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#define BUTTON_STATE_ACTIVE 0
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#ifdef __cplusplus
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}
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#endif
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#endif
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62
hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
Normal file
62
hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
Normal file
@ -0,0 +1,62 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "board_cfg.h"
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
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#define BSP_CFG_HEAP_BYTES (0x1000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_CFG_H_ */
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@ -0,0 +1,5 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_CFG_H_
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#define BSP_MCU_DEVICE_CFG_H_
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#define BSP_CFG_MCU_PART_SERIES (8)
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#endif /* BSP_MCU_DEVICE_CFG_H_ */
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@ -0,0 +1,11 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_R7FA8M1AHECBD
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#define BSP_MCU_FEATURE_SET ('A')
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#define BSP_ROM_SIZE_BYTES (2064384)
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#define BSP_RAM_SIZE_BYTES (917504)
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#define BSP_DATA_FLASH_SIZE_BYTES (12288)
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#define BSP_PACKAGE_BGA
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#define BSP_PACKAGE_PINS (224)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
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@ -0,0 +1,526 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_FAMILY_CFG_H_
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#define BSP_MCU_FAMILY_CFG_H_
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA8M1 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (0)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (16000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 1
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#define BSP_HOCO_HZ (18000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (20000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 4
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#define BSP_HOCO_HZ (32000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 7
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#define BSP_HOCO_HZ (48000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CFG_FLL_ENABLE (0)
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#define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1)
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#define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1)
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#define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1)
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#define BSP_CFG_RTOS_IDLE_SLEEP (0)
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#define BSP_CFG_CLOCK_SETTLING_DELAY_US (150)
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#if defined(BSP_PACKAGE_LQFP) && (BSP_PACKAGE_PINS == 100)
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#define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U)
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#elif defined(BSP_PACKAGE_LQFP)
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#define BSP_MAX_CLOCK_CHANGE_THRESHOLD (200000000U)
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#else
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#define BSP_MAX_CLOCK_CHANGE_THRESHOLD (240000000U)
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#endif
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
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#define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
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#if defined(_RA_TZ_SECURE)
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#define BSP_TZ_SECURE_BUILD (1)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#elif defined(_RA_TZ_NONSECURE)
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (1)
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#else
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#endif
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/* TrustZone Settings */
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#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
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#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
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#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
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/* CMSIS TrustZone Settings */
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#define SCB_CSR_AIRCR_INIT (1)
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#define SCB_AIRCR_BFHFNMINS_VAL (0)
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#define SCB_AIRCR_SYSRESETREQS_VAL (1)
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#define SCB_AIRCR_PRIS_VAL (0)
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#define TZ_FPU_NS_USAGE (1)
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#ifndef SCB_NSACR_CP10_11_VAL
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#define SCB_NSACR_CP10_11_VAL (3U)
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#endif
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#ifndef FPU_FPCCR_TS_VAL
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#define FPU_FPCCR_TS_VAL (1U)
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#endif
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#define FPU_FPCCR_CLRONRETS_VAL (1)
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#ifndef FPU_FPCCR_CLRONRET_VAL
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#define FPU_FPCCR_CLRONRET_VAL (1)
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#endif
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/* Type 1 Peripheral Security Attribution */
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/* Peripheral Security Attribution Register (PSAR) Settings */
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#ifndef BSP_TZ_CFG_PSARB
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#define BSP_TZ_CFG_PSARB (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | \
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(1 << 15) /* ETHERC/EDMAC */ | \
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(1 << 16) /* OSPI */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */)
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#endif
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#ifndef BSP_TZ_CFG_PSARC
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#define BSP_TZ_CFG_PSARC (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP-E51A */)
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#endif
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#ifndef BSP_TZ_CFG_PSARD
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#define BSP_TZ_CFG_PSARD (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */)
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#endif
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#ifndef BSP_TZ_CFG_PSARE
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#define BSP_TZ_CFG_PSARE (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */)
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#endif
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#ifndef BSP_TZ_CFG_MSSAR
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#define BSP_TZ_CFG_MSSAR (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */)
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#endif
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/* Type 2 Peripheral Security Attribution */
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/* Security attribution for RSTSRn registers. */
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#ifndef BSP_TZ_CFG_RSTSAR
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#define BSP_TZ_CFG_RSTSAR (0x00000007U)
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#endif
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/* Security attribution for registers of LVD channels. */
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#ifndef BSP_TZ_CFG_LVDSAR
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/* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */
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#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0)
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#define BSP_TZ_CFG_LVDSAR (0U)
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#else
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#define BSP_TZ_CFG_LVDSAR (3U)
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#endif
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#endif
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/* Security attribution for LPM registers.
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* - OPCCR based on clock security.
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* - Set remaining registers based on LPM security.
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*/
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#ifndef BSP_TZ_CFG_LPMSAR
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#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\
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0x002E0106U | \
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(BSP_CFG_CLOCKS_SECURE == 0)))
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#endif
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/* Deep Standby Interrupt Factor Security Attribution Register. */
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#ifndef BSP_TZ_CFG_DPFSAR
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#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0U : 0xAF1FFFFFU)
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#endif
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/* RAM Standby Control Security Attribution Register. */
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#ifndef BSP_TZ_CFG_RSCSAR
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#define BSP_TZ_CFG_RSCSAR ((RA_NOT_DEFINED > 0) ? 0U : 0x00037FFFU)
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#endif
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/* Security attribution for CGC registers. */
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#ifndef BSP_TZ_CFG_CGFSAR
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#if BSP_CFG_CLOCKS_SECURE
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/* Protect all CGC registers from Non-secure write access. */
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#define BSP_TZ_CFG_CGFSAR (0U)
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#else
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/* Allow Secure and Non-secure write access. */
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#define BSP_TZ_CFG_CGFSAR (0x047F3BFDU)
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#endif
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#endif
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/* Security attribution for Battery Backup registers. */
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#ifndef BSP_TZ_CFG_BBFSAR
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#if 0
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#define BSP_TZ_CFG_BBFSAR (0U)
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#else
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#define BSP_TZ_CFG_BBFSAR (0x1FU)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for Battery Backup registers (VBTBKRn). */
|
||||
#ifndef BSP_TZ_CFG_VBRSABAR
|
||||
#if 0
|
||||
#define BSP_TZ_CFG_VBRSABAR (0xFFE0)
|
||||
#else
|
||||
#define BSP_TZ_CFG_VBRSABAR (0xED00)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for IRQ channels. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARA
|
||||
#define BSP_TZ_CFG_ICUSARA (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */)
|
||||
#endif
|
||||
|
||||
/* Security attribution for NMI registers. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARB
|
||||
#define BSP_TZ_CFG_ICUSARB (0 | 0U) /* Should match AIRCR.BFHFNMINS. */
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for DMAC channels */
|
||||
#ifndef BSP_TZ_CFG_DMACCHSAR
|
||||
#define BSP_TZ_CFG_DMACCHSAR (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARE
|
||||
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0U : 0xFF1D0000U)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN1. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARF
|
||||
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0U : 0x00007F08U)
|
||||
#endif
|
||||
|
||||
/* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */
|
||||
#ifndef BSP_TZ_CFG_TEVTRCR
|
||||
#define BSP_TZ_CFG_TEVTRCR (0)
|
||||
#endif
|
||||
|
||||
/* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */
|
||||
#ifndef BSP_TZ_CFG_ELCSARA
|
||||
#define BSP_TZ_CFG_ELCSARA (0x00000007U)
|
||||
#endif
|
||||
|
||||
/* Set DTCSTSAR if the Secure program uses the DTC. */
|
||||
#if RA_NOT_DEFINED == RA_NOT_DEFINED
|
||||
#define BSP_TZ_CFG_DTC_USED (0U)
|
||||
#else
|
||||
#define BSP_TZ_CFG_DTC_USED (1U)
|
||||
#endif
|
||||
|
||||
/* Security attribution of FLWT and FCKMHZ registers. */
|
||||
#ifndef BSP_TZ_CFG_FSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for nonsecure applications to access FLWT and FCKMHZ. */
|
||||
#define BSP_TZ_CFG_FSAR (\
|
||||
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\
|
||||
((RA_NOT_DEFINED) > 0 ? 0U: (1U << 1)) | /* FCACHESA */\
|
||||
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \
|
||||
((RA_NOT_DEFINED) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */\
|
||||
((RA_NOT_DEFINED) > 0 ? 0U: (1U << 10U)) /* FACICMRSA */)
|
||||
#endif
|
||||
|
||||
/* Security attribution for SRAM registers. */
|
||||
#ifndef BSP_TZ_CFG_SRAMSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
|
||||
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
|
||||
#define BSP_TZ_CFG_SRAMSAR (\
|
||||
((1U) << 0U) | /* SRAMSA0 */\
|
||||
((1U) << 1U) | /* SRAMSA1 */\
|
||||
((1U) << 7U) | /* STBRAMSA */\
|
||||
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */)
|
||||
#endif
|
||||
|
||||
/* Security attribution for the DMAC Bus Master MPU settings. */
|
||||
#ifndef BSP_TZ_CFG_MMPUSARA
|
||||
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
|
||||
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR)
|
||||
#endif
|
||||
|
||||
/* Security Attribution Register A for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARA
|
||||
#define BSP_TZ_CFG_BUSSARA (1U)
|
||||
#endif
|
||||
/* Security Attribution Register B for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARB
|
||||
#define BSP_TZ_CFG_BUSSARB (1U)
|
||||
#endif
|
||||
/* Security Attribution Register C for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARC
|
||||
#define BSP_TZ_CFG_BUSSARC (1U)
|
||||
#endif
|
||||
|
||||
/* Enable Uninitialized Non-Secure Application Fallback. */
|
||||
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
|
||||
#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
|
||||
#endif
|
||||
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
|
||||
#define BSP_CFG_ROM_REG_OFS2 ((1 << 0) | 0xFFFFFFFEU)
|
||||
|
||||
/* Option Function Select Register 1 Security Attribution */
|
||||
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
|
||||
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U)))
|
||||
#else
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U)
|
||||
#endif
|
||||
#endif
|
||||
#define BSP_CFG_ROM_REG_OFS1_INITECCEN (0 << 25)
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFCFFFED0 | (1 << 3) | (7) | (1 << 5) | (1 << 8) | (1 << 24) | (BSP_CFG_ROM_REG_OFS1_INITECCEN))
|
||||
|
||||
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
|
||||
|
||||
/* Dual Mode Select Register */
|
||||
#ifndef BSP_CFG_ROM_REG_DUALSEL
|
||||
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
|
||||
#endif
|
||||
|
||||
/* Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS0
|
||||
#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS1
|
||||
#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS2
|
||||
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS3
|
||||
#define BSP_CFG_ROM_REG_BPS3 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS0
|
||||
#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS1
|
||||
#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS2
|
||||
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS3
|
||||
#define BSP_CFG_ROM_REG_PBPS3 (~( 0U))
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
|
||||
#endif
|
||||
/* Security Attribution for Bank Select Register */
|
||||
#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
|
||||
#define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
#endif
|
||||
|
||||
/* FSBL Control Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_FSBLCTRL0
|
||||
#define BSP_CFG_ROM_REG_FSBLCTRL0 ( \
|
||||
(7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos) | \
|
||||
(7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos) | \
|
||||
(7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos) | \
|
||||
(7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos) | \
|
||||
0xFFFFF000)
|
||||
#endif
|
||||
|
||||
/* FSBL Control Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_FSBLCTRL1
|
||||
#define BSP_CFG_ROM_REG_FSBLCTRL1 ( \
|
||||
(3 << R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos) | \
|
||||
0xFFFFFFFC)
|
||||
#endif
|
||||
|
||||
/* FSBL Control Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_FSBLCTRL2
|
||||
#define BSP_CFG_ROM_REG_FSBLCTRL2 ( \
|
||||
(15 << R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos) | \
|
||||
(0x1F << R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos) | \
|
||||
0xFFFFFE00)
|
||||
#endif
|
||||
|
||||
/* Start Address of Code Certificate Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_SACC0
|
||||
#define BSP_CFG_ROM_REG_SACC0 (0xFFFFFFFF)
|
||||
#endif
|
||||
|
||||
/* Start Address of Code Certificate Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_SACC1
|
||||
#define BSP_CFG_ROM_REG_SACC1 (0xFFFFFFFF)
|
||||
#endif
|
||||
|
||||
/* Start Address of Measurement Report Register */
|
||||
#ifndef BSP_CFG_ROM_REG_SAMR
|
||||
#define BSP_CFG_ROM_REG_SAMR (0xFFFFFFFF)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_DCACHE_ENABLED
|
||||
#define BSP_CFG_DCACHE_ENABLED (0)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_ENABLED
|
||||
#define BSP_CFG_SDRAM_ENABLED (0)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_TRAS
|
||||
#define BSP_CFG_SDRAM_TRAS (6)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_TRCD
|
||||
#define BSP_CFG_SDRAM_TRCD (3)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_TRP
|
||||
#define BSP_CFG_SDRAM_TRP (3)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_TWR
|
||||
#define BSP_CFG_SDRAM_TWR (2)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_TCL
|
||||
#define BSP_CFG_SDRAM_TCL (3)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_TRFC
|
||||
#define BSP_CFG_SDRAM_TRFC (937)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_TREFW
|
||||
#define BSP_CFG_SDRAM_TREFW (8)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_INIT_ARFI
|
||||
#define BSP_CFG_SDRAM_INIT_ARFI (10)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_INIT_ARFC
|
||||
#define BSP_CFG_SDRAM_INIT_ARFC (8)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_INIT_PRC
|
||||
#define BSP_CFG_SDRAM_INIT_PRC (3)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
|
||||
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
|
||||
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_ACCESS_MODE
|
||||
#define BSP_CFG_SDRAM_ACCESS_MODE (1)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_SDRAM_BUS_WIDTH
|
||||
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
|
||||
#endif
|
||||
#endif /* BSP_MCU_FAMILY_CFG_H_ */
|
||||
127
hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
127
hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Normal file
@ -0,0 +1,127 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_PIN_CFG_H_
|
||||
#define BSP_PIN_CFG_H_
|
||||
#include "r_ioport.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
#define ENET_RMII_INT (BSP_IO_PORT_00_PIN_00)
|
||||
#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_01)
|
||||
#define GROVE2_AN102 (BSP_IO_PORT_00_PIN_02)
|
||||
#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_03)
|
||||
#define ARDUINO_A0_MIKROBUS_AN000 (BSP_IO_PORT_00_PIN_04)
|
||||
#define GROVE2_AN001 (BSP_IO_PORT_00_PIN_05)
|
||||
#define PMOD1_IRQ11 (BSP_IO_PORT_00_PIN_06)
|
||||
#define ARDUINO_A004 (BSP_IO_PORT_00_PIN_07)
|
||||
#define USER_S2 (BSP_IO_PORT_00_PIN_08)
|
||||
#define SW1 (BSP_IO_PORT_00_PIN_09)
|
||||
#define MIKROBUS_IRQ14 (BSP_IO_PORT_00_PIN_10)
|
||||
#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
|
||||
#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
|
||||
#define OSPI_DQ0 (BSP_IO_PORT_01_PIN_00)
|
||||
#define OSPI_DQ3 (BSP_IO_PORT_01_PIN_01)
|
||||
#define OSPI_DQ4 (BSP_IO_PORT_01_PIN_02)
|
||||
#define OSPI_DQ2 (BSP_IO_PORT_01_PIN_03)
|
||||
#define OSPI_CS (BSP_IO_PORT_01_PIN_04)
|
||||
#define OSPI_INT (BSP_IO_PORT_01_PIN_05)
|
||||
#define OSPI_RESET (BSP_IO_PORT_01_PIN_06)
|
||||
#define LED3 (BSP_IO_PORT_01_PIN_07)
|
||||
#define ETH_A_RMII_RMII_RXDV (BSP_IO_PORT_01_PIN_12)
|
||||
#define ETH_A_LINKSTA (BSP_IO_PORT_01_PIN_14)
|
||||
#define MPLX_CTRL (BSP_IO_PORT_01_PIN_15)
|
||||
#define NMI (BSP_IO_PORT_02_PIN_00)
|
||||
#define MD (BSP_IO_PORT_02_PIN_01)
|
||||
#define CAN_STB (BSP_IO_PORT_02_PIN_07)
|
||||
#define TDI (BSP_IO_PORT_02_PIN_08)
|
||||
#define TDO (BSP_IO_PORT_02_PIN_09)
|
||||
#define SWDIO (BSP_IO_PORT_02_PIN_10)
|
||||
#define SWCLK (BSP_IO_PORT_02_PIN_11)
|
||||
#define EXTAL (BSP_IO_PORT_02_PIN_12)
|
||||
#define XTAL (BSP_IO_PORT_02_PIN_13)
|
||||
#define ETH_A_RXER (BSP_IO_PORT_03_PIN_00)
|
||||
#define ETH_A_RXD1 (BSP_IO_PORT_03_PIN_01)
|
||||
#define ETH_A_RXD0 (BSP_IO_PORT_03_PIN_02)
|
||||
#define ETH_A_REFCLK (BSP_IO_PORT_03_PIN_03)
|
||||
#define ETH_A_TXD0 (BSP_IO_PORT_03_PIN_04)
|
||||
#define ETH_A_TXD1 (BSP_IO_PORT_03_PIN_05)
|
||||
#define ETH_A_TXEN (BSP_IO_PORT_03_PIN_06)
|
||||
#define ETH_A_MDIO (BSP_IO_PORT_03_PIN_07)
|
||||
#define ETH_A_MDC (BSP_IO_PORT_03_PIN_08)
|
||||
#define ARDUINO_D0_MIKROBUS_RXD3 (BSP_IO_PORT_03_PIN_09)
|
||||
#define ARDUINO_D1_MIKROBUS_TXD3 (BSP_IO_PORT_03_PIN_10)
|
||||
#define CAN_RXD (BSP_IO_PORT_03_PIN_11)
|
||||
#define CAN_TXD (BSP_IO_PORT_03_PIN_12)
|
||||
#define I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic (BSP_IO_PORT_04_PIN_00)
|
||||
#define I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic (BSP_IO_PORT_04_PIN_01)
|
||||
#define ETH_B_MDIO (BSP_IO_PORT_04_PIN_02)
|
||||
#define ETH_B_LINKSTA (BSP_IO_PORT_04_PIN_03)
|
||||
#define ETH_B_RST_N (BSP_IO_PORT_04_PIN_04)
|
||||
#define ETH_B_TXEN (BSP_IO_PORT_04_PIN_05)
|
||||
#define ETH_B_TXD1 (BSP_IO_PORT_04_PIN_06)
|
||||
#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07)
|
||||
#define USBHS_VBUSEN (BSP_IO_PORT_04_PIN_08)
|
||||
#define USBHS_OVRCURA (BSP_IO_PORT_04_PIN_09)
|
||||
#define MISOB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_10)
|
||||
#define MOSIB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_11)
|
||||
#define RSPCKB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_12)
|
||||
#define SSLB0_B_ARDUINO_D10_MIKROBUS (BSP_IO_PORT_04_PIN_13)
|
||||
#define LED2 (BSP_IO_PORT_04_PIN_14)
|
||||
#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00)
|
||||
#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01)
|
||||
#define MIKROBUS_RESET (BSP_IO_PORT_05_PIN_02)
|
||||
#define PMOD2_7_IRQ1 (BSP_IO_PORT_05_PIN_08)
|
||||
#define GROVE2_IIC_SDA1 (BSP_IO_PORT_05_PIN_11)
|
||||
#define GROVE2_IIC_SCL1 (BSP_IO_PORT_05_PIN_12)
|
||||
#define LED1 (BSP_IO_PORT_06_PIN_00)
|
||||
#define ARDUINO_D5 (BSP_IO_PORT_06_PIN_01)
|
||||
#define ARDUINO_D6 (BSP_IO_PORT_06_PIN_02)
|
||||
#define ARDUINO_D9 (BSP_IO_PORT_06_PIN_03)
|
||||
#define PMOD1_3_MISO0_RXD0_SCL0 (BSP_IO_PORT_06_PIN_09)
|
||||
#define PMOD1_2_MOSI0_TXD0 (BSP_IO_PORT_06_PIN_10)
|
||||
#define PMOD1_4_SCK0 (BSP_IO_PORT_06_PIN_11)
|
||||
#define PMOD1_1_SSL0_CTS_RTS (BSP_IO_PORT_06_PIN_12)
|
||||
#define PMOD1_1_CTS0 (BSP_IO_PORT_06_PIN_13)
|
||||
#define PMOD1_9_GPIO (BSP_IO_PORT_06_PIN_14)
|
||||
#define PMOD1_10_GPIO (BSP_IO_PORT_06_PIN_15)
|
||||
#define ETH_B_TXD0 (BSP_IO_PORT_07_PIN_00)
|
||||
#define ETH_B_REFCLK (BSP_IO_PORT_07_PIN_01)
|
||||
#define ETH_B_RXD0 (BSP_IO_PORT_07_PIN_02)
|
||||
#define ETH_B_RXD1 (BSP_IO_PORT_07_PIN_03)
|
||||
#define ETH_B_RXER (BSP_IO_PORT_07_PIN_04)
|
||||
#define ETH_B_RMII_RXDV (BSP_IO_PORT_07_PIN_05)
|
||||
#define I3C_SDA0_PULLUP (BSP_IO_PORT_07_PIN_11)
|
||||
#define OSPI_DQ5 (BSP_IO_PORT_08_PIN_00)
|
||||
#define OSPI_DS (BSP_IO_PORT_08_PIN_01)
|
||||
#define OSPI_DQ6 (BSP_IO_PORT_08_PIN_02)
|
||||
#define OSPI_DQ1 (BSP_IO_PORT_08_PIN_03)
|
||||
#define OSPI_DQ7 (BSP_IO_PORT_08_PIN_04)
|
||||
#define OSPI_CK (BSP_IO_PORT_08_PIN_08)
|
||||
#define PMOD2_8_RESET (BSP_IO_PORT_08_PIN_09)
|
||||
#define PMOD2_9_GPIO (BSP_IO_PORT_08_PIN_10)
|
||||
#define PMOD2_10_GPIO (BSP_IO_PORT_08_PIN_11)
|
||||
#define ARDUINO_RESET (BSP_IO_PORT_08_PIN_12)
|
||||
#define USBFS_P (BSP_IO_PORT_08_PIN_14)
|
||||
#define USBFS_N (BSP_IO_PORT_08_PIN_15)
|
||||
#define ARDUINO_D4 (BSP_IO_PORT_09_PIN_05)
|
||||
#define ARDUINO_D2 (BSP_IO_PORT_09_PIN_06)
|
||||
#define ARDUINO_D3_MIKROBUS_GTIOC13A (BSP_IO_PORT_09_PIN_07)
|
||||
#define ARDUINO_D7 (BSP_IO_PORT_09_PIN_08)
|
||||
#define ARDUINO_D8 (BSP_IO_PORT_09_PIN_09)
|
||||
#define PMOD2_3_MISO2_RXD2 (BSP_IO_PORT_10_PIN_02)
|
||||
#define PMOD2_2_MOSI2_TXD2 (BSP_IO_PORT_10_PIN_03)
|
||||
#define PMOD2_4_SCK2 (BSP_IO_PORT_10_PIN_04)
|
||||
#define PMOD2_1_CTS_RTS_SSL2 (BSP_IO_PORT_10_PIN_05)
|
||||
#define PMOD2_1_CTS2 (BSP_IO_PORT_10_PIN_06)
|
||||
#define PMOD1_8_RESET (BSP_IO_PORT_10_PIN_08)
|
||||
#define JLOB_COMS_TX (BSP_IO_PORT_10_PIN_14)
|
||||
#define JLOB_COMS_RX (BSP_IO_PORT_10_PIN_15)
|
||||
#define I3C_SCL0_PULLUP (BSP_IO_PORT_11_PIN_00)
|
||||
#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01)
|
||||
extern const ioport_cfg_t g_bsp_pin_cfg; /* RA8M1 EK */
|
||||
|
||||
void BSP_PinConfigSecurityInit();
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
#endif /* BSP_PIN_CFG_H_ */
|
||||
13
hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
Normal file
13
hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
Normal file
@ -0,0 +1,13 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef R_IOPORT_CFG_H_
|
||||
#define R_IOPORT_CFG_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* R_IOPORT_CFG_H_ */
|
||||
56
hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h
Normal file
56
hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h
Normal file
@ -0,0 +1,56 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (7) /* HOCO 48MHz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL Mul x80-99|Mul x96|PLL Mul x96.00 */
|
||||
#define BSP_CFG_PLL_FREQUENCY_HZ (960000000) /* PLL 960000000Hz */
|
||||
#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */
|
||||
#define BSP_CFG_PLL1P_FREQUENCY_HZ (480000000) /* PLL1P 480000000Hz */
|
||||
#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL1Q Div /2 */
|
||||
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (480000000) /* PLL1Q 480000000Hz */
|
||||
#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */
|
||||
#define BSP_CFG_PLL1R_FREQUENCY_HZ (480000000) /* PLL1R 480000000Hz */
|
||||
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */
|
||||
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
|
||||
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL2 Mul x80-99|Mul x96|PLL2 Mul x96.00 */
|
||||
#define BSP_CFG_PLL2_FREQUENCY_HZ (0) /* PLL2 0Hz */
|
||||
#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL2P Div /2 */
|
||||
#define BSP_CFG_PLL2P_FREQUENCY_HZ (0) /* PLL2P 0Hz */
|
||||
#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL2Q Div /2 */
|
||||
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (0) /* PLL2Q 0Hz */
|
||||
#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL2R Div /2 */
|
||||
#define BSP_CFG_PLL2R_FREQUENCY_HZ (0) /* PLL2R 0Hz */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SCICLK Disabled */
|
||||
#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SPICLK Disabled */
|
||||
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
|
||||
#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* I3CCLK Disabled */
|
||||
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCK Disabled */
|
||||
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
|
||||
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
|
||||
#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKC Div /8 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */
|
||||
#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */
|
||||
#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */
|
||||
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* BCLK Div /4 */
|
||||
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* FCLK Div /8 */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_4) /* SCICLK Div /4 */
|
||||
#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_4) /* SPICLK Div /4 */
|
||||
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_8) /* CANFDCLK Div /8 */
|
||||
#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_3) /* I3CCLK Div /3 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCK Div /5 */
|
||||
#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* U60CK Div /5 */
|
||||
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTASPICLK Div /4 */
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
11
hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c
Normal file
11
hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* generated common source file - do not edit */
|
||||
#include "common_data.h"
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport =
|
||||
{
|
||||
.p_api = &g_ioport_on_ioport,
|
||||
.p_ctrl = &g_ioport_ctrl,
|
||||
.p_cfg = &g_bsp_pin_cfg,
|
||||
};
|
||||
void g_common_init(void) {
|
||||
}
|
||||
20
hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h
Normal file
20
hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* generated common header file - do not edit */
|
||||
#ifndef COMMON_DATA_H_
|
||||
#define COMMON_DATA_H_
|
||||
#include <stdint.h>
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "bsp_pin_cfg.h"
|
||||
FSP_HEADER
|
||||
#define IOPORT_CFG_NAME g_bsp_pin_cfg
|
||||
#define IOPORT_CFG_OPEN R_IOPORT_Open
|
||||
#define IOPORT_CFG_CTRL g_ioport_ctrl
|
||||
|
||||
/* IOPORT Instance */
|
||||
extern const ioport_instance_t g_ioport;
|
||||
|
||||
/* IOPORT control structure. */
|
||||
extern ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
void g_common_init(void);
|
||||
FSP_FOOTER
|
||||
#endif /* COMMON_DATA_H_ */
|
||||
275
hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c
Normal file
275
hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c
Normal file
@ -0,0 +1,275 @@
|
||||
/* generated pin source file - do not edit */
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_10,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_10,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_12,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_13,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_04_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_11,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_12,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_06_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_09,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_08_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_10_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_10_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_10_PIN_04,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_10_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_10_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_10_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_10_PIN_15,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_11_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
|
||||
},
|
||||
};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
|
||||
#if BSP_TZ_SECURE_BUILD
|
||||
|
||||
void R_BSP_PinCfgSecurityInit(void);
|
||||
|
||||
/* Initialize SAR registers for secure pins. */
|
||||
void R_BSP_PinCfgSecurityInit(void)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#else
|
||||
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#endif
|
||||
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
|
||||
|
||||
|
||||
for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
|
||||
{
|
||||
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
|
||||
uint32_t port = port_pin >> 8U;
|
||||
uint32_t pin = port_pin & 0xFFU;
|
||||
pmsar[port] &= (uint16_t) ~(1U << pin);
|
||||
}
|
||||
|
||||
for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
|
||||
#else
|
||||
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
820
hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld
Normal file
820
hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld
Normal file
@ -0,0 +1,820 @@
|
||||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
INCLUDE memory_regions.ld
|
||||
|
||||
/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
|
||||
/*
|
||||
XIP_SECONDARY_SLOT_IMAGE = 1;
|
||||
*/
|
||||
|
||||
QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
|
||||
OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
|
||||
OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
|
||||
|
||||
/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
|
||||
__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
|
||||
|
||||
ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
|
||||
ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
|
||||
DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
|
||||
DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
|
||||
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
|
||||
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
|
||||
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
|
||||
RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
|
||||
|
||||
OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
|
||||
OPTION_SETTING_DATA_FLASH_S_START = DEFINED(OPTION_SETTING_DATA_FLASH_S_START) ? OPTION_SETTING_DATA_FLASH_S_START : 0;
|
||||
OPTION_SETTING_DATA_FLASH_S_LENGTH = DEFINED(OPTION_SETTING_DATA_FLASH_S_LENGTH) ? OPTION_SETTING_DATA_FLASH_S_LENGTH : 0;
|
||||
|
||||
/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
|
||||
* Bootloader images do not configure option settings because they are owned by the bootloader.
|
||||
* FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
|
||||
__bl_FSP_BOOTABLE_IMAGE = 1;
|
||||
__bln_FSP_BOOTABLE_IMAGE = 1;
|
||||
PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
|
||||
USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
|
||||
USE_OPTION_SETTING_DATA_FLASH = PROJECT_SECURE_OR_FLAT && (OPTION_SETTING_DATA_FLASH_S_LENGTH != 0);
|
||||
|
||||
__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
|
||||
(DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
|
||||
FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
|
||||
__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
|
||||
__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
|
||||
__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
|
||||
__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
|
||||
RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
|
||||
__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
|
||||
__bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
|
||||
__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
|
||||
__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
|
||||
__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
|
||||
|
||||
XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
|
||||
FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
|
||||
XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
|
||||
FLASH_IMAGE_START;
|
||||
LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
|
||||
DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
|
||||
FLASH_LENGTH;
|
||||
OPTION_SETTING_SAS_SIZE = 0x34;
|
||||
OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
|
||||
OPTION_SETTING_LENGTH == 0 ? 0 :
|
||||
OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
|
||||
DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
|
||||
FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
|
||||
RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
|
||||
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
|
||||
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
|
||||
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
|
||||
OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
|
||||
OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
|
||||
OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
|
||||
OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
|
||||
OPTION_SETTING_DATA_FLASH_S (r) : ORIGIN = OPTION_SETTING_DATA_FLASH_S_START, LENGTH = OPTION_SETTING_DATA_FLASH_S_LENGTH
|
||||
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be DEFINED in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
* __qspi_flash_start__
|
||||
* __qspi_flash_end__
|
||||
* __qspi_flash_code_size__
|
||||
* __qspi_region_max_size__
|
||||
* __qspi_region_start_address__
|
||||
* __qspi_region_end_address__
|
||||
* __ospi_device_0_start__
|
||||
* __ospi_device_0_end__
|
||||
* __ospi_device_0_code_size__
|
||||
* __ospi_device_0_region_max_size__
|
||||
* __ospi_device_0_region_start_address__
|
||||
* __ospi_device_0_region_end_address__
|
||||
* __ospi_device_1_start__
|
||||
* __ospi_device_1_end__
|
||||
* __ospi_device_1_code_size__
|
||||
* __ospi_device_1_region_max_size__
|
||||
* __ospi_device_1_region_start_address__
|
||||
* __ospi_device_1_region_end_address__
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__tz_FLASH_S = ABSOLUTE(FLASH_START);
|
||||
__ROM_Start = .;
|
||||
|
||||
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
|
||||
* space because ROM registers are at address 0x400 and there is very little space
|
||||
* in between. */
|
||||
KEEP(*(.fixed_vectors*))
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
|
||||
/* Some devices have a gap of code flash between the vector table and ROM Registers.
|
||||
* The flash gap section allows applications to place code and data in this section. */
|
||||
*(.flash_gap*)
|
||||
|
||||
/* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
|
||||
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
|
||||
KEEP(*(.rom_registers*))
|
||||
|
||||
/* Allocate flash write-boundary-aligned
|
||||
* space for sce9 wrapped public keys for mcuboot if the module is used.
|
||||
*/
|
||||
KEEP(*(.mcuboot_sce9_key*))
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.version))
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
__usb_dev_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_device_desc_fs*))
|
||||
__usb_cfg_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_config_desc_fs*))
|
||||
__usb_interface_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_interface_desc_fs*))
|
||||
__usb_descriptor_end_fs = .;
|
||||
__usb_dev_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_device_desc_hs*))
|
||||
__usb_cfg_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_config_desc_hs*))
|
||||
__usb_interface_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_interface_desc_hs*))
|
||||
__usb_descriptor_end_hs = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
__ROM_End = .;
|
||||
} > FLASH = 0xFF
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
. = .;
|
||||
__itcm_data_pre_location = .;
|
||||
|
||||
/* Initialized ITCM data. */
|
||||
/* Aligned to FCACHE2 for RA8. */
|
||||
.itcm_data : ALIGN(16)
|
||||
{
|
||||
/* Start of ITCM Secure Trustzone region. */
|
||||
__tz_ITCM_S = ABSOLUTE(ITCM_START);
|
||||
|
||||
/* All ITCM data start */
|
||||
__itcm_data_start = .;
|
||||
|
||||
KEEP(*(.itcm_data*))
|
||||
|
||||
/* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* All ITCM data end */
|
||||
__itcm_data_end = .;
|
||||
|
||||
/*
|
||||
* Start of the ITCM Non-Secure Trustzone region.
|
||||
* ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
|
||||
} > ITCM AT > FLASH = 0x00
|
||||
|
||||
/* Addresses exported for ITCM initialization. */
|
||||
__itcm_data_init_start = LOADADDR(.itcm_data);
|
||||
__itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
|
||||
|
||||
ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
|
||||
ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
|
||||
ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
|
||||
|
||||
/* Restore location counter. */
|
||||
/* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
|
||||
/* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
|
||||
. = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
|
||||
|
||||
__exidx_start = .;
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
}
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
__tz_RAM_S = ORIGIN(RAM);
|
||||
|
||||
/* If DTC is used, put the DTC vector table at the start of SRAM.
|
||||
This avoids memory holes due to 1K alignment required by it. */
|
||||
.fsp_dtc_vector_table (NOLOAD) :
|
||||
{
|
||||
. = ORIGIN(RAM);
|
||||
*(.fsp_dtc_vector_table)
|
||||
} > RAM
|
||||
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__Code_In_RAM_Start = .;
|
||||
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
|
||||
*(vtable)
|
||||
/* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
|
||||
*(.data.*)
|
||||
*(.data)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM AT > FLASH
|
||||
|
||||
. = .;
|
||||
__dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
/* Initialized DTCM data. */
|
||||
/* Aligned to FCACHE2 for RA8. */
|
||||
.dtcm_data : ALIGN(16)
|
||||
{
|
||||
/* Start of DTCM Secure Trustzone region. */
|
||||
__tz_DTCM_S = ABSOLUTE(DTCM_START);
|
||||
|
||||
/* Initialized DTCM data start */
|
||||
__dtcm_data_start = .;
|
||||
|
||||
KEEP(*(.dtcm_data*))
|
||||
|
||||
/* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* Initialized DTCM data end */
|
||||
__dtcm_data_end = .;
|
||||
} > DTCM AT > FLASH = 0x00
|
||||
|
||||
. = __dtcm_data_end;
|
||||
/* Uninitialized DTCM data. */
|
||||
/* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
|
||||
.dtcm_bss ALIGN(8) (NOLOAD) :
|
||||
{
|
||||
/* Uninitialized DTCM data start */
|
||||
__dtcm_bss_start = .;
|
||||
|
||||
KEEP(*(.dtcm_bss*))
|
||||
|
||||
/* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* Uninitialized DTCM data end */
|
||||
__dtcm_bss_end = .;
|
||||
|
||||
/*
|
||||
* Start of the DTCM Non-Secure Trustzone region.
|
||||
* DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
|
||||
} > DTCM
|
||||
|
||||
/* Addresses exported for DTCM initialization. */
|
||||
__dtcm_data_init_start = LOADADDR(.dtcm_data);
|
||||
__dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
|
||||
|
||||
ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
|
||||
ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
|
||||
ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
|
||||
ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
|
||||
ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
|
||||
ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
|
||||
|
||||
/* Restore location counter. */
|
||||
/* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
|
||||
/* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
|
||||
. = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
|
||||
|
||||
/* TrustZone Secure Gateway Stubs Section */
|
||||
|
||||
/* Store location counter for SPI non-retentive sections. */
|
||||
sgstubs_pre_location = .;
|
||||
|
||||
/* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
|
||||
SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
|
||||
.gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
|
||||
{
|
||||
__FLASH_NSC_START = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
|
||||
_start_sg = .;
|
||||
*(.gnu.sgstubs*)
|
||||
. = ALIGN(32);
|
||||
_end_sg = .;
|
||||
} > FLASH
|
||||
|
||||
__tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
|
||||
FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
|
||||
|
||||
/* QSPI_FLASH section to be downloaded via debugger */
|
||||
.qspi_flash :
|
||||
{
|
||||
__qspi_flash_start__ = .;
|
||||
KEEP(*(.qspi_flash*))
|
||||
KEEP(*(.code_in_qspi*))
|
||||
__qspi_flash_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
|
||||
|
||||
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
|
||||
__qspi_flash_code_addr__ = sgstubs_pre_location;
|
||||
.qspi_non_retentive : AT(__qspi_flash_code_addr__)
|
||||
{
|
||||
__qspi_non_retentive_start__ = .;
|
||||
KEEP(*(.qspi_non_retentive*))
|
||||
__qspi_non_retentive_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
|
||||
|
||||
__qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
|
||||
__qspi_region_start_address__ = __qspi_flash_start__;
|
||||
__qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
|
||||
|
||||
/* Support for OctaRAM */
|
||||
.OSPI_DEVICE_0_NO_LOAD (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ospi_device_0_start__ = .;
|
||||
*(.ospi_device_0_no_load*)
|
||||
. = ALIGN(4);
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0_RAM
|
||||
|
||||
.OSPI_DEVICE_1_NO_LOAD (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ospi_device_1_start__ = .;
|
||||
*(.ospi_device_1_no_load*)
|
||||
. = ALIGN(4);
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1_RAM
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
|
||||
|
||||
/* OSPI_DEVICE_0 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_0 :
|
||||
{
|
||||
__ospi_device_0_start__ = .;
|
||||
KEEP(*(.ospi_device_0*))
|
||||
KEEP(*(.code_in_ospi_device_0*))
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
|
||||
|
||||
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
|
||||
.ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
|
||||
{
|
||||
__ospi_device_0_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_0_non_retentive*))
|
||||
__ospi_device_0_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
|
||||
|
||||
__ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_0_region_start_address__ = __ospi_device_0_start__;
|
||||
__ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
|
||||
|
||||
/* OSPI_DEVICE_1 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_1 :
|
||||
{
|
||||
__ospi_device_1_start__ = .;
|
||||
KEEP(*(.ospi_device_1*))
|
||||
KEEP(*(.code_in_ospi_device_1*))
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
|
||||
|
||||
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
|
||||
.ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
|
||||
{
|
||||
__ospi_device_1_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_1_non_retentive*))
|
||||
__ospi_device_1_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
|
||||
|
||||
__ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_1_region_start_address__ = __ospi_device_1_start__;
|
||||
__ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
|
||||
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_start = .;
|
||||
KEEP(*(.noinit*))
|
||||
. = ALIGN(8);
|
||||
/* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
|
||||
KEEP(*(.heap.*))
|
||||
__noinit_end = .;
|
||||
} > RAM
|
||||
|
||||
. = .;
|
||||
__nocache_pre_location = .;
|
||||
.nocache ALIGN(32) (NOLOAD):
|
||||
{
|
||||
__nocache_start = .;
|
||||
|
||||
KEEP(*(.nocache))
|
||||
|
||||
. = ALIGN(32);
|
||||
__nocache_end = .;
|
||||
} > RAM
|
||||
. = (SIZEOF(.nocache) > 0) ? __nocache_end : __nocache_pre_location;
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* Stacks are stored in this section. */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
/* Main stack */
|
||||
KEEP(*(.stack))
|
||||
__StackTop = .;
|
||||
/* Thread stacks */
|
||||
KEEP(*(.stack*))
|
||||
__StackTopAll = .;
|
||||
} > RAM
|
||||
|
||||
PROVIDE(__stack = __StackTopAll);
|
||||
|
||||
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
|
||||
at run time for things such as ThreadX memory pool allocations. */
|
||||
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
|
||||
|
||||
/* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
|
||||
* If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__RAM_NSC_START = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
|
||||
|
||||
/* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
|
||||
* RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
|
||||
* specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_N = DEFINED(FLASH_BOOTLOADER_LENGTH) ? (RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH) : DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_NSC_START, 8192);
|
||||
|
||||
/* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
|
||||
* The EDMAC is a non-secure bus master and can only access non-secure RAM. */
|
||||
.ns_buffer (NOLOAD):
|
||||
{
|
||||
/* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
|
||||
. = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
|
||||
|
||||
KEEP(*(.ns_buffer*))
|
||||
} > RAM
|
||||
|
||||
/* Data flash. */
|
||||
.data_flash :
|
||||
{
|
||||
. = ORIGIN(DATA_FLASH);
|
||||
__tz_DATA_FLASH_S = .;
|
||||
__Data_Flash_Start = .;
|
||||
KEEP(*(.data_flash*))
|
||||
__Data_Flash_End = .;
|
||||
|
||||
__tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
|
||||
} > DATA_FLASH
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_S = ORIGIN(SDRAM);
|
||||
|
||||
/* SDRAM */
|
||||
.sdram (NOLOAD):
|
||||
{
|
||||
__SDRAM_Start = .;
|
||||
KEEP(*(.sdram*))
|
||||
KEEP(*(.frame*))
|
||||
__SDRAM_End = .;
|
||||
} > SDRAM
|
||||
|
||||
. = .;
|
||||
__nocache_sdram_pre_location = .;
|
||||
.nocache_sdram ALIGN(32) (NOLOAD):
|
||||
{
|
||||
__nocache_sdram_start = .;
|
||||
|
||||
KEEP(*(.nocache_sdram))
|
||||
|
||||
. = ALIGN(32);
|
||||
__nocache_sdram_end = .;
|
||||
} > SDRAM
|
||||
. = (SIZEOF(.nocache_sdram) > 0) ? __nocache_sdram_end : __nocache_sdram_pre_location;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_N = __SDRAM_End;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_S = ORIGIN(ID_CODE);
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
|
||||
* Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
|
||||
* memory region between TrustZone projects. */
|
||||
__tz_ID_CODE_N = __tz_ID_CODE_S;
|
||||
|
||||
.id_code :
|
||||
{
|
||||
__ID_Code_Start = .;
|
||||
KEEP(*(.id_code*))
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
|
||||
|
||||
.option_setting_ofs :
|
||||
{
|
||||
__OPTION_SETTING_OFS_Start = .;
|
||||
KEEP(*(.option_setting_ofs0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
|
||||
KEEP(*(.option_setting_ofs2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
|
||||
KEEP(*(.option_setting_dualsel))
|
||||
__OPTION_SETTING_OFS_End = .;
|
||||
} > OPTION_SETTING_OFS = 0xFF
|
||||
|
||||
.option_setting_sas :
|
||||
{
|
||||
__OPTION_SETTING_SAS_Start = .;
|
||||
KEEP(*(.option_setting_sas))
|
||||
__OPTION_SETTING_SAS_End = .;
|
||||
} > OPTION_SETTING_SAS = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
|
||||
|
||||
.option_setting_ns :
|
||||
{
|
||||
__OPTION_SETTING_NS_Start = .;
|
||||
KEEP(*(.option_setting_ofs1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_ofs3))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_banksel))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps0))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps2))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps3))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps0))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps1))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps2))
|
||||
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps3))
|
||||
__OPTION_SETTING_NS_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
|
||||
|
||||
.option_setting_s :
|
||||
{
|
||||
__OPTION_SETTING_S_Start = .;
|
||||
KEEP(*(.option_setting_ofs1_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs3_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sec))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec3))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec3))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs3_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel3))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} > OPTION_SETTING_S = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_DATA_FLASH_S_S = ORIGIN(OPTION_SETTING_DATA_FLASH_S);
|
||||
|
||||
.option_setting_data_flash_s :
|
||||
{
|
||||
__OPTION_SETTING_DATA_FLASH_S_Start = .;
|
||||
KEEP(*(.option_setting_data_flash_fsblctrl0))
|
||||
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x04 : __OPTION_SETTING_DATA_FLASH_S_Start;
|
||||
KEEP(*(.option_setting_data_flash_fsblctrl1))
|
||||
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x08 : __OPTION_SETTING_DATA_FLASH_S_Start;
|
||||
KEEP(*(.option_setting_data_flash_fsblctrl2))
|
||||
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x0C : __OPTION_SETTING_DATA_FLASH_S_Start;
|
||||
KEEP(*(.option_setting_data_flash_sacc0))
|
||||
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x10 : __OPTION_SETTING_DATA_FLASH_S_Start;
|
||||
KEEP(*(.option_setting_data_flash_sacc1))
|
||||
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x14 : __OPTION_SETTING_DATA_FLASH_S_Start;
|
||||
KEEP(*(.option_setting_data_flash_samr))
|
||||
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x2E0 : __OPTION_SETTING_DATA_FLASH_S_Start;
|
||||
KEEP(*(.option_setting_data_flash_hoemrtpk))
|
||||
__OPTION_SETTING_DATA_FLASH_S_End = .;
|
||||
} > OPTION_SETTING_DATA_FLASH_S = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_DATA_FLASH_S_N = __OPTION_SETTING_DATA_FLASH_S_End;
|
||||
}
|
||||
30
hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld
Normal file
30
hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld
Normal file
@ -0,0 +1,30 @@
|
||||
|
||||
/* generated memory regions file - do not edit */
|
||||
RAM_START = 0x22000000;
|
||||
RAM_LENGTH = 0xE0000;
|
||||
FLASH_START = 0x02000000;
|
||||
FLASH_LENGTH = 0x1F8000;
|
||||
DATA_FLASH_START = 0x27000000;
|
||||
DATA_FLASH_LENGTH = 0x3000;
|
||||
OPTION_SETTING_START = 0x0300A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0300A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
OPTION_SETTING_DATA_FLASH_S_START = 0x27030080;
|
||||
OPTION_SETTING_DATA_FLASH_S_LENGTH = 0x800;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x68000000;
|
||||
SDRAM_LENGTH = 0x8000000;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x0;
|
||||
OSPI_DEVICE_0_START = 0x80000000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x10000000;
|
||||
OSPI_DEVICE_1_START = 0x90000000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x10000000;
|
||||
ITCM_START = 0x00000000;
|
||||
ITCM_LENGTH = 0x10000;
|
||||
DTCM_START = 0x20000000;
|
||||
DTCM_LENGTH = 0x10000;
|
||||
NS_OFFSET_START = 0x10000000;
|
||||
NS_OFFSET_LENGTH = 0x0;
|
||||
@ -133,8 +133,8 @@
|
||||
<property id="config.bsp.fsp.dcache" value="config.bsp.fsp.dcache.disabled"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra">
|
||||
<property id="config.bsp.common.main" value="0x400"/>
|
||||
<property id="config.bsp.common.heap" value="0"/>
|
||||
<property id="config.bsp.common.main" value="0x1000"/>
|
||||
<property id="config.bsp.common.heap" value="0x1000"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
@ -290,7 +290,7 @@
|
||||
<symbolicName propertyId="p006.symbolic_name" value="PMOD1_IRQ11"/>
|
||||
<symbolicName propertyId="p007.symbolic_name" value="ARDUINO_A004"/>
|
||||
<symbolicName propertyId="p008.symbolic_name" value="USER_S2"/>
|
||||
<symbolicName propertyId="p009.symbolic_name" value="USER_S1"/>
|
||||
<symbolicName propertyId="p009.symbolic_name" value="SW1"/>
|
||||
<symbolicName propertyId="p010.symbolic_name" value="MIKROBUS_IRQ14"/>
|
||||
<symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/>
|
||||
<symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/>
|
||||
|
||||
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Reference in New Issue
Block a user