diff --git a/examples/build_system/cmake/cpu/cortex-m23.cmake b/examples/build_system/cmake/cpu/cortex-m23.cmake
index 3093dc99a..c7ce1d242 100644
--- a/examples/build_system/cmake/cpu/cortex-m23.cmake
+++ b/examples/build_system/cmake/cpu/cortex-m23.cmake
@@ -5,13 +5,13 @@ if (TOOLCHAIN STREQUAL "gcc")
     -mfloat-abi=soft
     )
 
-  set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+  set(FREERTOS_PORT GCC_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
 
 elseif (TOOLCHAIN STREQUAL "iar")
   set(TOOLCHAIN_COMMON_FLAGS
     --cpu cortex-m23
     )
 
-  set(FREERTOS_PORT IAR_ARM_CM0 CACHE INTERNAL "")
+  set(FREERTOS_PORT IAR_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
 
 endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake b/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake
index 7946affbe..01e6b979a 100644
--- a/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake
+++ b/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake
@@ -12,6 +12,6 @@ elseif (TOOLCHAIN STREQUAL "iar")
     --cpu cortex-m33+nodsp
     )
 
-  set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+  set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
 
 endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m33.cmake b/examples/build_system/cmake/cpu/cortex-m33.cmake
index 7ebaf1748..94c29099d 100644
--- a/examples/build_system/cmake/cpu/cortex-m33.cmake
+++ b/examples/build_system/cmake/cpu/cortex-m33.cmake
@@ -14,6 +14,6 @@ elseif (TOOLCHAIN STREQUAL "iar")
     --fpu VFPv5-SP
     )
 
-  set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+  set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
 
 endif ()
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
index acde3f46f..6a9a20e21 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
@@ -1,9 +1,6 @@
 set(MCU_VARIANT MCXA153)
 set(MCU_CORE MCXA153)
 
-set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
-
 set(JLINK_DEVICE MCXA153_M33)
 set(PYOCD_TARGET MCXA153)
 set(NXPLINK_DEVICE MCXA153:MCXA153)
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.h b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
index 02a452da5..e207d89d9 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.h
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
@@ -28,7 +28,7 @@
 #define BOARD_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 // LED
@@ -38,29 +38,27 @@
 #define LED_STATE_ON          0
 
 // ISP button (Dummy, use unused pin
- #define BUTTON_GPIO           GPIO3
- #define BUTTON_CLK            kCLOCK_GateGPIO3
- #define BUTTON_PIN            29 //sw2
- #define BUTTON_STATE_ACTIVE   0
+#define BUTTON_GPIO           GPIO3
+#define BUTTON_CLK            kCLOCK_GateGPIO3
+#define BUTTON_PIN            29 //sw2
+#define BUTTON_STATE_ACTIVE   0
 
 // UART
 #define UART_DEV              LPUART0
 
 static inline void board_uart_init_clock(void) {
-
   /* attach 12 MHz clock to LPUART0 (debug console) */
-    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
-    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+  CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+  CLOCK_AttachClk(kFRO12M_to_LPUART0);
 
-    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
 }
 
-
 // XTAL
 #define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
 
 #ifdef __cplusplus
- }
+}
 #endif
 
 #endif
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
index cf6d9c0eb..af8416d8e 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
@@ -2,7 +2,7 @@ MCU_VARIANT = MCXA153
 MCU_CORE = MCXA153
 PORT = 0
 
-CPU_CORE ?= cortex-m33-nodsp-nofp
+CPU_CORE = cortex-m33-nodsp-nofp
 CFLAGS += \
 	-DCPU_MCXA153VLH \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
index a08d248f5..8c3280743 100644
--- a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
@@ -1,9 +1,6 @@
 set(MCU_VARIANT MCXN947)
 set(MCU_CORE MCXN947_cm33_core0)
 
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
-
 set(JLINK_DEVICE MCXN947_M33_0)
 set(PYOCD_TARGET MCXN947)
 set(NXPLINK_DEVICE MCXN947:MCXN947)
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
index d90780996..22fefd79b 100644
--- a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
@@ -2,7 +2,7 @@ MCU_VARIANT = MCXN947
 MCU_CORE = MCXN947_cm33_core0
 PORT ?= 1
 
-CPU_CORE ?= cortex-m33
+CPU_CORE = cortex-m33
 CFLAGS += \
 	-DCPU_MCXN947VDF_cm33_core0 \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
index a08d248f5..8c3280743 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -1,9 +1,6 @@
 set(MCU_VARIANT MCXN947)
 set(MCU_CORE MCXN947_cm33_core0)
 
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
-
 set(JLINK_DEVICE MCXN947_M33_0)
 set(PYOCD_TARGET MCXN947)
 set(NXPLINK_DEVICE MCXN947:MCXN947)
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
index d90780996..22fefd79b 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.mk
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -2,7 +2,7 @@ MCU_VARIANT = MCXN947
 MCU_CORE = MCXN947_cm33_core0
 PORT ?= 1
 
-CPU_CORE ?= cortex-m33
+CPU_CORE = cortex-m33
 CFLAGS += \
 	-DCPU_MCXN947VDF_cm33_core0 \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index 96ae2fde3..cc675a49d 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -33,6 +33,10 @@
 #include "pin_mux.h"
 #include "clock_config.h"
 
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
 #ifdef BOARD_TUD_RHPORT
   #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
 #else
@@ -45,54 +49,50 @@
   #define PORT_SUPPORT_HOST(_n)    0
 #endif
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
 
 #if CFG_TUSB_MCU == OPT_MCU_MCXN9
-void USB0_FS_IRQHandler(void)
-{
+void USB0_FS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB1_HS_IRQHandler(void)
-{
+void USB1_HS_IRQHandler(void) {
   tud_int_handler(1);
 }
 
 #elif CFG_TUSB_MCU == OPT_MCU_MCXA15
-void USB0_IRQHandler(void)
-{
+
+void USB0_IRQHandler(void) {
   tud_int_handler(0);
 }
+
 #endif
 
 
-void board_init(void)
-{
+void board_init(void) {
   BOARD_InitPins();
   BOARD_InitBootClocks();
   CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
 
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  #if CFG_TUSB_MCU == OPT_MCU_MCXN9
+  NVIC_SetPriority(USB0_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #else
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
 #endif
 
   // LED
   CLOCK_EnableClock(LED_CLK);
-  gpio_pin_config_t led_config = {
-      kGPIO_DigitalOutput,
-      0,
-  };
-  GPIO_PinInit(LED_GPIO,LED_PIN, &led_config);
+  gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0};
+  GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
   board_led_write(0);
 
 #ifdef NEOPIXEL_PIN
@@ -110,7 +110,7 @@ void board_init(void)
   // Button
 #ifdef BUTTON_GPIO
   CLOCK_EnableClock(BUTTON_CLK);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+  gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
   GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
 #endif
 
@@ -125,33 +125,26 @@ void board_init(void)
   lpuart_config_t uart_config;
   LPUART_GetDefaultConfig(&uart_config);
   uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = true;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
   LPUART_Init(UART_DEV, &uart_config, 12000000u);
 #endif
 
   // USB VBUS
   /* PORT0 PIN22 configured as USB0_VBUS */
 
-
-  /* MCXA15 USB configurations */
-#if PORT_SUPPORT_DEVICE(0) && (CFG_TUSB_MCU == OPT_MCU_MCXA15)
-
-  RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
-  CLOCK_EnableUsbfsClock();
-
-#endif
-
-
-  /* MCXN9 USB configurations */
-#if PORT_SUPPORT_DEVICE(0) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
+#if PORT_SUPPORT_DEVICE(0)
   // Port0 is Full Speed
 
+  #if CFG_TUSB_MCU == OPT_MCU_MCXA15
+  RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
+  #elif CFG_TUSB_MCU == OPT_MCU_MCXN9
   CLOCK_AttachClk(kCLK_48M_to_USB0);
   CLOCK_EnableClock(kCLOCK_Usb0Ram);
   CLOCK_EnableClock(kCLOCK_Usb0Fs);
-  CLOCK_EnableUsbfsClock();
+  #endif
 
+  CLOCK_EnableUsbfsClock();
 #endif
 
 #if PORT_SUPPORT_DEVICE(1) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
@@ -213,9 +206,8 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 
 #ifdef NEOPIXEL_PIN
   if (state) {
@@ -229,23 +221,21 @@ void board_led_write(bool state)
 #endif
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
 #ifdef BUTTON_GPIO
   return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
 #endif
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
 #ifdef UART_DEV
-  LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+  LPUART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
   return len;
 #else
   (void) buf; (void) len;
@@ -255,13 +245,13 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 78490ec57..c8591b569 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -11,6 +11,16 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 # toolchain set up
+if (MCU_VARIANT STREQUAL "MCXA153")
+  set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
+  set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
+elseif (MCU_VARIANT STREQUAL "MCXN947")
+  set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+  set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
+else()
+  message(FATAL_ERROR "MCU_VARIANT not supported")
+endif()
+
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 #------------------------------------
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index 3ee0efaf6..58149fb8d 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -39,23 +39,16 @@ SRC_C += \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
 
-
-# fsl_lpflexcomm just needed for MCXN9
+# fsl_lpflexcomm for MCXN9
 ifeq ($(MCU_VARIANT), MCXN947)
-	SRC_C += \
-		$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
-
+	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c
 endif
 
-# fsl_spc just needed for MCXNA15
+# fsl_spc for MCXNA15
 ifeq ($(MCU_VARIANT), MCXA153)
-	SRC_C += \
-		$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c  \
-
+	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c
 endif
 
-
-
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcx.h b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
index 3f2b13323..4b93a03a7 100644
--- a/src/portable/chipidea/ci_fs/ci_fs_mcx.h
+++ b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
@@ -30,29 +30,27 @@
 #include "fsl_device_registers.h"
 
 #if CFG_TUSB_MCU == OPT_MCU_MCXN9
-	#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USBFS0_BASE)
-	#define USB0_IRQN 				USB0_FS_IRQn
+  #define CI_FS_REG(_port)  ((ci_fs_regs_t*) USBFS0_BASE)
+  #define CIFS_IRQN 				USB0_FS_IRQn
 
 #elif CFG_TUSB_MCU == OPT_MCU_MCXA15
-	#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
-	#define USB0_IRQN 				USB0_IRQn
+  #define CI_FS_REG(_port)  ((ci_fs_regs_t*) USB0_BASE)
+  #define CIFS_IRQN         USB0_IRQn
 
 #else
   #error "MCU is not supported"
 #endif
 
-#define CI_REG                  CI_FS_REG(0)
+#define CI_REG              CI_FS_REG(0)
 
-void dcd_int_enable(uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   (void) rhport;
-  NVIC_EnableIRQ(USB0_IRQN);
+  NVIC_EnableIRQ(CIFS_IRQN);
 }
 
-void dcd_int_disable(uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   (void) rhport;
-  NVIC_DisableIRQ(USB0_IRQN);
+  NVIC_DisableIRQ(CIFS_IRQN);
 }
 
 #endif
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
index a68ecf8c9..02f813ab5 100644
--- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -295,7 +295,7 @@ void dcd_init(uint8_t rhport)
   CI_REG->INT_EN = USB_INTEN_USBRSTEN_MASK;
 
   dcd_connect(rhport);
-  // NVIC_ClearPendingIRQ(USB0_IRQn);
+  // NVIC_ClearPendingIRQ(CIFS_IRQN);
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)