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Merge pull request #2480 from hathach/fix-k32l2-clock
add clock_config.c/h from mcux to frdmk32l2a4 and frdm_k32l2b
This commit is contained in:
Ha Thach
GitHub
commit
d241f32342
@ -8,9 +8,6 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast
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# All source paths should be relative to the top level.
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LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
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SRC_C += \
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$(MCU_DIR)/project_template/clock_config.c \
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# For flash-jlink target
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JLINK_DEVICE = K32L2A41xxxxA
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491
hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
Normal file
491
hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
Normal file
@ -0,0 +1,491 @@
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/*
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* Copyright 2019 ,2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
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* Note: The clock could not be set when it is being used as system clock.
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* In default out of reset, the CPU is clocked from FIRC(IRC48M),
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* so before setting FIRC, change to use another available clock source.
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*
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* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
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*
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* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
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* Wait until the system clock source is changed to target source.
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*
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* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
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* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
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* Supported run mode and clock restrictions could be found in Reference Manual.
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v7.0
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processor: K32L2A41xxxxA
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package_id: K32L2A41VLL1A
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mcu_data: ksdk2_0
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processor_version: 9.0.0
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_smc.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define SCG_CLKOUTCNFG_SIRC 2U /*!< SCG CLKOUT clock select: Slow IRC */
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#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
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#define SCG_SPLL_DISABLE 0U /*!< System PLL disabled */
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#define SCG_SYS_OSC_CAP_0P 0U /*!< Oscillator 0pF capacitor load */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetScgOutSel
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* Description : Set the SCG clock out select (CLKOUTSEL).
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* Param setting : The selected clock source.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
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{
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SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_FircSafeConfig
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* Description : This function is used to safely configure FIRC clock.
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* In default out of reset, the CPU is clocked from FIRC(IRC48M).
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* Before setting FIRC, change to use SIRC as system clock,
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* then configure FIRC. After FIRC is set, change back to use FIRC
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* in case SIRC need to be configured.
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* Param fircConfig : FIRC configuration.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
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{
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scg_sys_clk_config_t curConfig;
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const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
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.div1 = kSCG_AsyncClkDisable,
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.div3 = kSCG_AsyncClkDivBy2,
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.range = kSCG_SircRangeHigh};
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scg_sys_clk_config_t sysClkSafeConfigSource = {
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.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved1 = 0,
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.reserved2 = 0,
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.reserved3 = 0,
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#endif
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.divCore = kSCG_SysClkDivBy1, /* Core clock divider */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved4 = 0,
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#endif
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.src = kSCG_SysClkSrcSirc, /* System clock source */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved5 = 0,
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#endif
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};
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/* Init Sirc. */
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CLOCK_InitSirc(&scgSircConfig);
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/* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
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CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
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/* Wait for clock source switch finished. */
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do
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{
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CLOCK_GetCurSysClkConfig(&curConfig);
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} while (curConfig.src != sysClkSafeConfigSource.src);
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/* Init Firc. */
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CLOCK_InitFirc(fircConfig);
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/* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
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sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
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CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
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/* Wait for clock source switch finished. */
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do
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{
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CLOCK_GetCurSysClkConfig(&curConfig);
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} while (curConfig.src != sysClkSafeConfigSource.src);
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}
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: Core_clock.outFreq, value: 48 MHz}
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- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
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- {id: LPO_clock.outFreq, value: 1 kHz}
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- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
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- {id: SIRCDIV3_CLK.outFreq, value: 4 MHz}
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- {id: SIRC_CLK.outFreq, value: 8 MHz}
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- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
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- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
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- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
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- {id: Slow_clock.outFreq, value: 24 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
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- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
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- {id: SCG.SIRCDIV3.scale, value: '2', locked: true}
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- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
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- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
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- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
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- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
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sources:
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- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
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{
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.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved1 = 0,
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.reserved2 = 0,
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.reserved3 = 0,
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#endif
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.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved4 = 0,
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#endif
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.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved5 = 0,
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#endif
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};
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const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
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{
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.freq = 32768U, /* System Oscillator frequency: 32768Hz */
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.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
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.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
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.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
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.div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
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.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
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.workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
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};
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const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
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{
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.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
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.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
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.div3 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 3: divided by 2 */
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.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
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};
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const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
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{
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.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
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.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
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.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
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.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
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.trimConfig = NULL, /* Fast IRC Trim disabled */
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};
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const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
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{
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.enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
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.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
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.div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
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.div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
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.src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
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.prediv = 0, /* Divided by 1 */
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.mult = 0, /* Multiply Factor is 16 */
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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{
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scg_sys_clk_config_t curConfig;
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/* Init SOSC according to board configuration. */
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CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
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/* Set the XTAL0 frequency based on board settings. */
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CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
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/* Init FIRC. */
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CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
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/* Init SIRC. */
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CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
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/* Set SCG to FIRC mode. */
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CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
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/* Wait for clock source switch finished. */
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do
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{
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CLOCK_GetCurSysClkConfig(&curConfig);
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} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
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}
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/*******************************************************************************
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********************* Configuration BOARD_BootClockHSRUN **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockHSRUN
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outputs:
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- {id: CLKOUT.outFreq, value: 8 MHz}
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- {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
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- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
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- {id: LPO_clock.outFreq, value: 1 kHz}
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- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
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- {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
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- {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
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- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
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- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
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- {id: SIRC_CLK.outFreq, value: 8 MHz}
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- {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
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- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
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- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
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- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
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- {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
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- {id: System_clock.outFreq, value: 96 MHz}
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settings:
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- {id: SCGMode, value: SPLL}
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- {id: powerMode, value: HSRUN}
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- {id: CLKOUTConfig, value: 'yes'}
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- {id: SCG.DIVSLOW.scale, value: '4'}
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- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
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- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
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- {id: SCG.PREDIV.scale, value: '4'}
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- {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
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- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
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- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
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- {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
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- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
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- {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
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- {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
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- {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
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- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
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- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
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- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
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- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
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sources:
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- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockHSRUN configuration
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******************************************************************************/
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const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
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{
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.divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved1 = 0,
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.reserved2 = 0,
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.reserved3 = 0,
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#endif
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.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved4 = 0,
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#endif
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.src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved5 = 0,
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#endif
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};
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const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
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{
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.freq = 32768U, /* System Oscillator frequency: 32768Hz */
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.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
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.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
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.div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
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.div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
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.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
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.workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
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};
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const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
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{
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.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
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.div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
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.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
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.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
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};
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const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
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{
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.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
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.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
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.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
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.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
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.trimConfig = NULL, /* Fast IRC Trim disabled */
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};
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const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN =
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{
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||||
.enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
|
||||
.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 3: divided by 1 */
|
||||
.src = kSCG_SysPllSrcFirc, /* System PLL clock source is Fast IRC */
|
||||
.prediv = 3, /* Divided by 4 */
|
||||
.mult = 0, /* Multiply Factor is 16 */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockHSRUN(void)
|
||||
{
|
||||
scg_sys_clk_config_t curConfig;
|
||||
|
||||
/* Init SOSC according to board configuration. */
|
||||
CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
|
||||
/* Set the XTAL0 frequency based on board settings. */
|
||||
CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
|
||||
/* Init FIRC. */
|
||||
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
|
||||
/* Init SIRC. */
|
||||
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
|
||||
/* Init SysPll. */
|
||||
CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
|
||||
/* Set HSRUN power mode. */
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeHsrun(SMC);
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
|
||||
{
|
||||
}
|
||||
|
||||
/* Set SCG to SPLL mode. */
|
||||
CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
|
||||
/* Wait for clock source switch finished. */
|
||||
do
|
||||
{
|
||||
CLOCK_GetCurSysClkConfig(&curConfig);
|
||||
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
|
||||
/* Set SCG CLKOUT selection. */
|
||||
CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockVLPR
|
||||
outputs:
|
||||
- {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: SIRC_CLK.outFreq, value: 8 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: System_clock.outFreq, value: 8 MHz}
|
||||
settings:
|
||||
- {id: SCGMode, value: SIRC}
|
||||
- {id: powerMode, value: VLPR}
|
||||
- {id: SCG.DIVSLOW.scale, value: '8'}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
|
||||
- {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
|
||||
sources:
|
||||
- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved1 = 0,
|
||||
.reserved2 = 0,
|
||||
.reserved3 = 0,
|
||||
#endif
|
||||
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved4 = 0,
|
||||
#endif
|
||||
.src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved5 = 0,
|
||||
#endif
|
||||
};
|
||||
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.freq = 0U, /* System Oscillator frequency: 0Hz */
|
||||
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
|
||||
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
|
||||
.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
|
||||
.workMode = kSCG_SysOscModeExt, /* Use external clock */
|
||||
};
|
||||
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
|
||||
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
|
||||
};
|
||||
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower,/* Enable FIRC clock, Enable FIRC in low power mode */
|
||||
.div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
|
||||
.trimConfig = NULL, /* Fast IRC Trim disabled */
|
||||
};
|
||||
const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
|
||||
.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
|
||||
.src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
|
||||
.prediv = 0, /* Divided by 1 */
|
||||
.mult = 0, /* Multiply Factor is 16 */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
/* Init FIRC. */
|
||||
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
|
||||
/* Init SIRC. */
|
||||
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
|
||||
/* Allow SMC all power modes. */
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
/* Set VLPR power mode. */
|
||||
SMC_SetPowerModeVlpr(SMC);
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||||
}
|
||||
164
hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
Normal file
164
hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
Normal file
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright 2019 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 32768U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
|
||||
/*! @brief System OSC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
|
||||
/*! @brief SIRC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
|
||||
/*! @brief FIRC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
|
||||
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockRUN;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockHSRUN **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
|
||||
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockHSRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 8000000U /*!< Core clock frequency: 8000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
|
||||
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockVLPR;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockVLPR(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
@ -8,9 +8,6 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
|
||||
|
||||
SRC_C += \
|
||||
$(MCU_DIR)/project_template/clock_config.c \
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = K32L2B31xxxxA
|
||||
|
||||
|
||||
220
hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
Normal file
220
hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
Normal file
@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Copyright 2019 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
|
||||
* and flash clock are in allowed range during clock mode switch.
|
||||
*
|
||||
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
|
||||
*
|
||||
* 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
|
||||
*
|
||||
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v7.0
|
||||
processor: K32L2B31xxxxA
|
||||
package_id: K32L2B31VLH0A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 9.0.0
|
||||
board: FRDM-K32L2B
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_smc.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
|
||||
#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
|
||||
#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 24 MHz}
|
||||
- {id: Core_clock.outFreq, value: 48 MHz}
|
||||
- {id: Flash_clock.outFreq, value: 24 MHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: MCGIRCLK.outFreq, value: 8 MHz}
|
||||
- {id: MCGPCLK.outFreq, value: 48 MHz}
|
||||
- {id: System_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: MCGMode, value: HIRC}
|
||||
- {id: MCG.CLKS.sel, value: MCG.HIRC}
|
||||
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
|
||||
- {id: MCG_C2_RANGE0_CFG, value: Very_high}
|
||||
- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
|
||||
- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
|
||||
- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
|
||||
- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
|
||||
- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
|
||||
- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
|
||||
sources:
|
||||
- {id: MCG.HIRC.outFreq, value: 48 MHz}
|
||||
- {id: OSC.OSC.outFreq, value: 32 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
|
||||
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
|
||||
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.hircEnableInNotHircMode = true, /* HIRC source is enabled */
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
|
||||
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
|
||||
};
|
||||
const osc_config_t oscConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.freq = 0U, /* Oscillator frequency: 0Hz */
|
||||
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Set MCG to HIRC mode. */
|
||||
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockVLPR
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 1 MHz}
|
||||
- {id: Core_clock.outFreq, value: 2 MHz}
|
||||
- {id: Flash_clock.outFreq, value: 1 MHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: MCGIRCLK.outFreq, value: 2 MHz}
|
||||
- {id: System_clock.outFreq, value: 2 MHz}
|
||||
settings:
|
||||
- {id: MCGMode, value: LIRC2M}
|
||||
- {id: powerMode, value: VLPR}
|
||||
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
|
||||
- {id: RTCCLKOUTConfig, value: 'yes'}
|
||||
- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
|
||||
- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
|
||||
sources:
|
||||
- {id: MCG.LIRC.outFreq, value: 2 MHz}
|
||||
- {id: OSC.OSC.outFreq, value: 32.768 kHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.outSrc = kMCGLITE_ClkSrcLirc, /* MCGOUTCLK source is LIRC */
|
||||
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCGLITE_Lirc2M, /* Slow internal reference (LIRC) 2 MHz clock selected */
|
||||
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.hircEnableInNotHircMode = false, /* HIRC source is not enabled */
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
|
||||
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
|
||||
};
|
||||
const osc_config_t oscConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.freq = 0U, /* Oscillator frequency: 0Hz */
|
||||
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Set MCG to LIRC2M mode. */
|
||||
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
|
||||
/* Set VLPR power mode. */
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
|
||||
SMC_SetPowerModeVlpr(SMC, false);
|
||||
#else
|
||||
SMC_SetPowerModeVlpr(SMC);
|
||||
#endif
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||||
}
|
||||
110
hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h
Normal file
110
hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright 2019 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
/*! @brief MCG lite set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN;
|
||||
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
|
||||
/*! @brief OSC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 2000000U /*!< Core clock frequency: 2000000Hz */
|
||||
|
||||
/*! @brief MCG lite set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief OSC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockVLPR(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
Loading…
x
Reference in New Issue
Block a user