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lpc13xx build ok (not work) with lpcopen

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hathach 2018-11-30 23:39:18 +07:00
parent 804c60304e
commit d246cc2e6c
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GPG Key ID: 2FA891220FBFD581
86 changed files with 15932 additions and 6276 deletions
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63
examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject
View File

@ -10,15 +10,15 @@
arm_endian="Little"
arm_fpu_type="None"
arm_interwork="No"
arm_linker_heap_size="256"
arm_linker_heap_size="0"
arm_linker_process_stack_size="0"
arm_linker_stack_size="256"
arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00010000;RAM;0x10000000;0x00002000;RAM;0x20000000;0x00000800"
arm_target_debug_interface_type="ADIv5"
arm_target_device_name="LPC1347"
arm_target_interface_type="SWD"
c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;BOARD_LPCXPRESSO1347;CFG_TUSB_MCU=OPT_MCU_LPC13XX"
c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)"
c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_LPCXPRESSO1347;CFG_TUSB_MCU=OPT_MCU_LPC13XX"
c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/lpc_chip_13xx/inc"
debug_register_definition_file="$(ProjectDir)/LPC13Uxx_Registers.xml"
debug_target_connection="J-Link"
gcc_entry_point="Reset_Handler"
@ -50,28 +50,55 @@
<folder Name="bsp">
<file file_name="../../../../../hw/bsp/ansi_escape.h" />
<file file_name="../../../../../hw/bsp/board.h" />
<folder Name="lpcxpresso1769">
<file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c" />
<file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.h" />
<folder Name="lpcxpresso1347">
<file file_name="../../../../../hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c" />
<file file_name="../../../../../hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h" />
</folder>
</folder>
<folder Name="mcu">
<folder Name="nxp">
<folder Name="lpc175x_6x">
<folder Name="CMSIS_CORE_LPC17xx">
<folder Name="lpc13xx">
<folder Name="lpc_chip_13xx">
<folder Name="inc">
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/adc_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/chip.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/clock_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis_1347.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cm3.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmFunc.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmInstr.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/error.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/flash_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/fmc_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_1.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_2.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpiogroup_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2c_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2cm_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/iocon_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/lpc_types.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pinint_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pmu_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ring_buffer.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ritimer_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/romapi_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ssp_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/stopwatch.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sys_config.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sysctl_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/timer_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/uart_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/usbd_13xx.h" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/wwdt_13xx.h" />
</folder>
<folder Name="src">
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c" />
</folder>
</folder>
<folder Name="LPC17xx_DriverLib">
<folder Name="include" />
<folder Name="source">
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_gpio.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_pinsel.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/chip_13xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/clock_13xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_1.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysctl_13xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysinit_13xx.c" />
<file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/uart_13xx.c" />
</folder>
</folder>
</folder>

509
hw/bsp/ea4357/startup/xpresso/cr_startup_lpc43xx.c
View File

@ -1,509 +0,0 @@
//*****************************************************************************
// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 150706
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2013-2015
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
// Declaration of external SystemInit function
extern void SystemInit(void);
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
//
// External declaration for LPC MCU vector table checksum from Linker Script
//
//*****************************************************************************
WEAK extern void __valid_user_code_checksum();
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((used,section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM4
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
__valid_user_code_checksum, // LPC MCU Checksum
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC43 (M4)
DAC_IRQHandler, // 16
#if defined (__USE_LPCOPEN)
M0APP_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY)
#else
M0CORE_IRQHandler, // 17
#endif
DMA_IRQHandler, // 18
0, // 19
FLASH_EEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
ETH_IRQHandler, // 21
SDIO_IRQHandler, // 22
LCD_IRQHandler, // 23
USB0_IRQHandler, // 24
USB1_IRQHandler, // 25
SCT_IRQHandler, // 26
RIT_IRQHandler, // 27
TIMER0_IRQHandler, // 28
TIMER1_IRQHandler, // 29
TIMER2_IRQHandler, // 30
TIMER3_IRQHandler, // 31
MCPWM_IRQHandler, // 32
ADC0_IRQHandler, // 33
I2C0_IRQHandler, // 34
I2C1_IRQHandler, // 35
SPI_IRQHandler, // 36
ADC1_IRQHandler, // 37
SSP0_IRQHandler, // 38
SSP1_IRQHandler, // 39
UART0_IRQHandler, // 40
UART1_IRQHandler, // 41
UART2_IRQHandler, // 42
UART3_IRQHandler, // 43
I2S0_IRQHandler, // 44
I2S1_IRQHandler, // 45
SPIFI_IRQHandler, // 46
SGPIO_IRQHandler, // 47
GPIO0_IRQHandler, // 48
GPIO1_IRQHandler, // 49
GPIO2_IRQHandler, // 50
GPIO3_IRQHandler, // 51
GPIO4_IRQHandler, // 52
GPIO5_IRQHandler, // 53
GPIO6_IRQHandler, // 54
GPIO7_IRQHandler, // 55
GINT0_IRQHandler, // 56
GINT1_IRQHandler, // 57
EVRT_IRQHandler, // 58
CAN1_IRQHandler, // 59
0, // 60
#if defined (__USE_LPCOPEN)
ADCHS_IRQHandler, // 61 ADCHS combined interrupt
#else
VADC_IRQHandler, // 61
#endif
ATIMER_IRQHandler, // 62
RTC_IRQHandler, // 63
0, // 64
WDT_IRQHandler, // 65
M0SUB_IRQHandler, // 66
CAN0_IRQHandler, // 67
QEI_IRQHandler, // 68
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__((section(".after_vectors"
)))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//
//*****************************************************************************
void ResetISR(void) {
// *************************************************************
// The following conditional block of code manually resets as
// much of the peripheral set of the LPC43 as possible. This is
// done because the LPC43 does not provide a means of triggering
// a full system reset under debugger control, which can cause
// problems in certain circumstances when debugging.
//
// You can prevent this code block being included if you require
// (for example when creating a final executable which you will
// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
//
#ifndef DONT_RESET_ON_RESTART
// Disable interrupts
__asm volatile ("cpsid i");
// equivalent to CMSIS '__disable_irq()' function
unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
// LPC_RGU->RESET_CTRL0 @ 0x40053100
// LPC_RGU->RESET_CTRL1 @ 0x40053104
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
// Write to LPC_RGU->RESET_CTRL0
*(RESET_CONTROL + 0) = 0x10DF1000;
// GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
// USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
// Write to LPC_RGU->RESET_CTRL1
*(RESET_CONTROL + 1) = 0x01DFF7FF;
// M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
// I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
// DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
// RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
// Clear all pending interrupts in the NVIC
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
unsigned int irqpendloop;
for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
*(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
}
// Reenable interrupts
__asm volatile ("cpsie i");
// equivalent to CMSIS '__enable_irq()' function
#endif // ifndef DONT_RESET_ON_RESTART
// *************************************************************
#if defined (__USE_LPCOPEN)
SystemInit();
#endif
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if !defined (__USE_LPCOPEN)
// LPCOpen init code deals with FP and VTOR initialisation
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
/*
* Code to enable the Cortex-M4 FPU only included
* if appropriate build options have been selected.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
*/
// CPACR is located at address 0xE000ED88
asm("LDR.W R0, =0xE000ED88");
// Read CPACR
asm("LDR R1, [R0]");
// Set bits 20-23 to enable CP10 and CP11 coprocessors
asm(" ORR R1, R1, #(0xF << 20)");
// Write back the modified value to the CPACR
asm("STR R1, [R0]");
#endif // (__VFP_FP__) && !(__SOFTFP__)
// ******************************
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
// CMSIS : SCB->VTOR = <address of vector table>
*pSCB_VTOR = (unsigned int) g_pfnVectors;
}
#endif
#if defined (__USE_CMSIS)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void) {
while (1) {
}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void) {
while (1) {
}
}

58
hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c
View File

@ -36,10 +36,10 @@
*/
/**************************************************************************/
#include "../board.h"
#ifdef BOARD_LPCXPRESSO1347
#include "../board.h"
#define LED_PORT (0)
#define LED_PIN (7)
#define LED_ON (1)
@ -63,39 +63,67 @@ enum {
BOARD_BUTTON_COUNT = sizeof(buttons) / sizeof(buttons[0])
};
// required by lpcopen chip layer
uint32_t const OscRateIn = 0;
uint32_t const ExtRateIn = 0;
// required by startup
void SystemInit(void)
{
Chip_SystemInit();
}
void board_init(void)
{
SystemInit();
Chip_SystemInit();
#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ); // 1 msec tick timer
#endif
GPIOInit();
Chip_GPIO_Init(LPC_GPIO_PORT);
//------------- LED -------------//
GPIOSetDir(LED_PORT, LED_PIN, 1);
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, BOARD_LED0);
//------------- BUTTON -------------//
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
//------------- UART -------------//
UARTInit(CFG_UART_BAUDRATE);
//UARTInit(CFG_UART_BAUDRATE);
}
/*------------------------------------------------------------------*/
/* TUSB HAL MILLISECOND
*------------------------------------------------------------------*/
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
system_ticks++;
}
uint32_t tusb_hal_millis(void)
{
return board_tick2ms(system_ticks);
}
#endif
//--------------------------------------------------------------------+
// LEDS
//--------------------------------------------------------------------+
void board_leds(uint32_t on_mask, uint32_t off_mask)
void board_led_control(uint32_t id, bool state)
{
if (on_mask & BIT_(0))
if (state)
{
GPIOSetBitValue(LED_PORT, LED_PIN, LED_ON);
}else if (off_mask & BIT_(0))
Chip_GPIO_SetValue(LPC_GPIO_PORT, 0, 1 << id);
}else
{
GPIOSetBitValue(LED_PORT, LED_PIN, LED_OFF);
Chip_GPIO_ClearValue(LPC_GPIO_PORT, 0, 1 << id);
}
}
@ -104,14 +132,14 @@ void board_leds(uint32_t on_mask, uint32_t off_mask)
//--------------------------------------------------------------------+
static bool button_read(uint8_t id)
{
return !GPIOGetPinValue(buttons[id].port, buttons[id].pin); // button is active low
// return !GPIOGetPinValue(buttons[id].port, buttons[id].pin); // button is active low
}
uint32_t board_buttons(void)
{
uint32_t result = 0;
for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
// for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
return result;
}
@ -121,7 +149,7 @@ uint32_t board_buttons(void)
//--------------------------------------------------------------------+
void board_uart_putchar(uint8_t c)
{
UARTSend(&c, 1);
// UARTSend(&c, 1);
}
uint8_t board_uart_getchar(void)

8
hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h
View File

@ -43,11 +43,11 @@
extern "C" {
#endif
#include "LPC13Uxx.h"
#include "gpio.h"
#include "uart.h"
//#include "LPC13Uxx.h"
#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
#include "chip.h"
#define BOARD_LED0 7
#ifdef __cplusplus
}

354
hw/bsp/lpcxpresso1347/startup/xpresso/cr_startup_lpc13u.c
View File

@ -1,354 +0,0 @@
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2012 Code Red Technologies Ltd.
//
// NXP LPC13U Microcontroller Startup code for use with Red Suite
//
// Version : 120202
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
// Code Red - if CMSIS is being used, then SystemInit() routine
// will be called by startup code rather than in application's main()
#if defined (__USE_CMSIS)
#include "LPC13Uxx.h"
#endif
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void OSTIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C_IRQHandler(void) ALIAS(IntDefaultHandler);
void CT16B0_IRQHandler(void) ALIAS(IntDefaultHandler);
void CT16B1_IRQHandler(void) ALIAS(IntDefaultHandler);
void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler);
void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void USART_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_FIQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler(void) ALIAS(IntDefaultHandler);
void OSCFAIL_IRQHandler(void) ALIAS(IntDefaultHandler);
void PVTCIRCUIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// LPC13U External Interrupts
PIN_INT0_IRQHandler, // All GPIO pin can be routed to PIN_INTx
PIN_INT1_IRQHandler,
PIN_INT2_IRQHandler,
PIN_INT3_IRQHandler,
PIN_INT4_IRQHandler,
PIN_INT5_IRQHandler,
PIN_INT6_IRQHandler,
PIN_INT7_IRQHandler,
GINT0_IRQHandler,
GINT1_IRQHandler, // PIO0 (0:7)
0,
0,
OSTIMER_IRQHandler,
0,
SSP1_IRQHandler, // SSP1
I2C_IRQHandler, // I2C
CT16B0_IRQHandler, // 16-bit Timer0
CT16B1_IRQHandler, // 16-bit Timer1
CT32B0_IRQHandler, // 32-bit Timer0
CT32B1_IRQHandler, // 32-bit Timer1
SSP0_IRQHandler, // SSP0
USART_IRQHandler, // USART
USB_IRQHandler, // USB IRQ
USB_FIQHandler, // USB FIQ
ADC_IRQHandler, // A/D Converter
WDT_IRQHandler, // Watchdog timer
BOD_IRQHandler, // Brown Out Detect
FMC_IRQHandler, // IP2111 Flash Memory Controller
OSCFAIL_IRQHandler, // OSC FAIL
PVTCIRCUIT_IRQHandler, // PVT CIRCUIT
USBWakeup_IRQHandler, // USB wake up
0,
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#ifdef __USE_CMSIS
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void) {
while (1) {
}
}
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void) {
while (1) {
}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a handler
// is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void) {
//
// Go into an infinite loop.
//
while (1) {
}
}

1
hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
View File

@ -157,7 +157,6 @@ void board_led_control(uint32_t id, bool state)
{
GPIO_ClearValue(BOARD_LED0_PORT, BIT_(BOARD_LED0));
}
}
//--------------------------------------------------------------------+

423
hw/bsp/lpcxpresso1769/startup/xpresso/cr_startup_lpc176x.c
View File

@ -1,423 +0,0 @@
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2009-10 Code Red Technologies Ltd.
//
// Microcontroller Startup code for use with Red Suite
//
// Version : 101130
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define SVCall_Handler SVC_Handler
// Code Red - if CMSIS is being used, then SystemInit() routine
// will be called by startup code rather than in application's main()
#if defined (__USE_CMSIS)
#include "system_LPC17xx.h"
#endif
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVCall_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVCall_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
SPI_IRQHandler, // 29, 0x74 - SPI
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
EINT3_IRQHandler, // 37, 0x94 - EINT3
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
ENET_IRQHandler, // 44, 0xb0 - Ethernet
RIT_IRQHandler, // 45, 0xb4 - RITINT
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
#ifndef USE_OLD_STYLE_DATA_BSS_INIT
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
#else
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the load address, execution address and length of the RW data section and
// the execution and length of the BSS (zero initialized) section.
// Note that these symbols are not normally used by the managed linker script
// mechanism in Red Suite/LPCXpresso 3.6 (Windows) and LPCXpresso 3.8 (Linux).
// They are provide here simply so this startup code can be used with earlier
// versions of Red Suite which do not support the more advanced managed linker
// script mechanism introduced in the above version. To enable their use,
// define "USE_OLD_STYLE_DATA_BSS_INIT".
//*****************************************************************************
extern unsigned int _etext;
extern unsigned int _data;
extern unsigned int _edata;
extern unsigned int _bss;
extern unsigned int _ebss;
#endif
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
#ifndef USE_OLD_STYLE_DATA_BSS_INIT
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#else
// Use Old Style Data and BSS section initialization.
// This will only initialize a single RAM bank.
unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen;
// Copy the data segment from flash to SRAM.
LoadAddr = &_etext;
ExeAddr = &_data;
EndAddr = &_edata;
SectionLen = (void*)EndAddr - (void*)ExeAddr;
data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen);
// Zero fill the bss segment
ExeAddr = &_bss;
EndAddr = &_ebss;
SectionLen = (void*)EndAddr - (void*)ExeAddr;
bss_init ((unsigned int)ExeAddr, SectionLen);
#endif
#ifdef __USE_CMSIS
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void SVCall_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void)
{
while(1)
{
}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{
while(1)
{
}
}

83
hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c
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@ -1,83 +0,0 @@
/**************************************************************************/
/*!
@file hal_lpc13uxx.c
@author hathach (tinyusb.org)
@section LICENSE
Software License Agreement (BSD License)
Copyright (c) 2013, hathach (tinyusb.org)
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holders nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This file is part of the tinyusb stack.
*/
/**************************************************************************/
#include "common/tusb_common.h"
#include "hal.h"
#if CFG_TUSB_MCU == OPT_MCU_LPC13XX
void tusb_hal_int_enable(uint8_t rhport)
{
(void) rhport; // discard compiler's warning
NVIC_EnableIRQ(USB_IRQ_IRQn);
}
void tusb_hal_int_disable(uint8_t rhport)
{
(void) rhport; // discard compiler's warning
NVIC_DisableIRQ(USB_IRQ_IRQn);
}
bool tusb_hal_init(void)
{
// TODO remove magic number
LPC_SYSCON->SYSAHBCLKCTRL |= ((0x1<<14) | (0x1<<27)); /* Enable AHB clock to the USB block and USB RAM. */
LPC_SYSCON->PDRUNCFG &= ~( BIT_(8) | BIT_(10) ); // enable USB PLL & USB transceiver
/* Pull-down is needed, or internally, VBUS will be floating. This is to
address the wrong status in VBUSDebouncing bit in CmdStatus register. */
// set PIO0_3 as USB_VBUS
LPC_IOCON->PIO0_3 &= ~0x1F;
LPC_IOCON->PIO0_3 |= (0x01<<0) | (1 << 3); /* Secondary function VBUS */
// set PIO0_6 as usb connect
LPC_IOCON->PIO0_6 &= ~0x07;
LPC_IOCON->PIO0_6 |= (0x01<<0); /* Secondary function SoftConn */
return true;
}
void USB_IRQHandler(void)
{
hal_dcd_isr(0);
}
#endif

54
hw/mcu/nxp/lpc13uxx/hal_mcu/hal_mcu.h
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@ -1,54 +0,0 @@
/**************************************************************************/
/*!
@file hal_lpc13uxx.h
@author hathach (tinyusb.org)
@section LICENSE
Software License Agreement (BSD License)
Copyright (c) 2013, hathach (tinyusb.org)
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holders nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This file is part of the tinyusb stack.
*/
/**************************************************************************/
#ifndef _TUSB_HAL_MCU_H_
#define _TUSB_HAL_MCU_H_
#include "LPC13Uxx.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _TUSB_HAL_MCU_H_ */

25
hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/history.txt
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@ -1,25 +0,0 @@
History of updates to CMSIS_CORE_LPC13Uxx
===========================================
18 July 2013
------------
CMSIS library project using ARM Cortex-M0 CMSIS files as
supplied in ARM's CMSIS 3.20 March 2013 release, together
with NXP's device specific files taken from old
CMSISv2p10_LPC13Uxx project.
Note files are built -Os for both Debug and Release
History of updates to CMSISv2p10_LPC13Uxx
=========================================
17 February 2012
----------------
CMSIS 2.1 library project using ARM Cortex-M3 CMSIS
files as supplied in ARM's CMSIS 2.1 July 2011 release,
together with device/board specific files from NXP for
LPC1300 (12bit ADC) parts (ie LPC1315/16/17/45/46/47).

760
hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/LPC13Uxx.h
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@ -1,760 +0,0 @@
/****************************************************************************************************//**
* @file LPC13Uxx.h
*
*
*
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
* default LPC13Uxx Device Series
*
* @version V0.1
* @date 18. Jan 2012
*
* @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
*
* from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
* created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
*
*******************************************************************************************************/
/** @addtogroup NXP
* @{
*/
/** @addtogroup LPC13Uxx
* @{
*/
#ifndef __LPC13UXX_H__
#define __LPC13UXX_H__
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/* Interrupt Number Definition */
typedef enum {
// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
// ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
GINT0_IRQn = 8, /*!< 8 GINT0 */
GINT1_IRQn = 9, /*!< 9 GINT1 */
Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
SSP1_IRQn = 14, /*!< 14 SSP1 */
I2C_IRQn = 15, /*!< 15 I2C */
CT16B0_IRQn = 16, /*!< 16 CT16B0 */
CT16B1_IRQn = 17, /*!< 17 CT16B1 */
CT32B0_IRQn = 18, /*!< 18 CT32B0 */
CT32B1_IRQn = 19, /*!< 19 CT32B1 */
SSP0_IRQn = 20, /*!< 20 SSP0 */
USART_IRQn = 21, /*!< 21 USART */
USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
ADC_IRQn = 24, /*!< 24 ADC */
WDT_IRQn = 25, /*!< 25 WDT */
BOD_IRQn = 26, /*!< 26 BOD */
FMC_IRQn = 27, /*!< 27 FMC */
Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
} IRQn_Type;
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
#include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
/** @addtogroup Device_Peripheral_Registers
* @{
*/
// ------------------------------------------------------------------------------------------------
// ----- I2C -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40000000) I2C Structure */
__IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
__IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
__IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
__IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
__O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
union{
__IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
struct{
__IO uint32_t ADR1;
__IO uint32_t ADR2;
__IO uint32_t ADR3;
};
};
__I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
union{
__IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
struct{
__IO uint32_t MASK0;
__IO uint32_t MASK1;
__IO uint32_t MASK2;
__IO uint32_t MASK3;
};
};
} LPC_I2C_Type;
// ------------------------------------------------------------------------------------------------
// ----- WWDT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40004000) WWDT Structure */
__IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
__IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
__O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
__I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
__IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
__IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
__IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
} LPC_WWDT_Type;
// ------------------------------------------------------------------------------------------------
// ----- USART -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40008000) USART Structure */
union {
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
__O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
};
union {
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
};
union {
__O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
__I uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
__I uint32_t RESERVED1;
__IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
__IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
} LPC_USART_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT16B0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
__IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
} LPC_CT16B0_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT16B1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
__IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
} LPC_CT16B1_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT32B0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
__IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
} LPC_CT32B0_Type;
// ------------------------------------------------------------------------------------------------
// ----- CT32B1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
__IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
struct{
__IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
struct{
__I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
} LPC_CT32B1_Type;
// ------------------------------------------------------------------------------------------------
// ----- ADC -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4001C000) ADC Structure */
__IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
__IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
__I uint32_t RESERVED0[1];
__IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
union{
__I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
struct{
__I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
__I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
__I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
__I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
__I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
__I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
__I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
__I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
};
};
__I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
} LPC_ADC_Type;
// ------------------------------------------------------------------------------------------------
// ----- PMU -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40038000) PMU Structure */
__IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
union{
__IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
struct{
__IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
__IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
__IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
__IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
};
};
__IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
} LPC_PMU_Type;
// ------------------------------------------------------------------------------------------------
// ----- FLASHCTRL -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
__I uint32_t RESERVED0[4];
__IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
__I uint32_t RESERVED1[3];
__IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
__IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
__I uint32_t RESERVED2[1];
__I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
__I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
__I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
__I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
__I uint32_t RESERVED3[1001];
__I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
__I uint32_t RESERVED4[1];
__O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
} LPC_FLASHCTRL_Type;
// ------------------------------------------------------------------------------------------------
// ----- SSP0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
__IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
__IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
__IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
__I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
} LPC_SSP0_Type;
// ------------------------------------------------------------------------------------------------
// ----- IOCON -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40044000) IOCON Structure */
__IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
__IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
__IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
__IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
__IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
__IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
__IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
__IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
__IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
__IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
__IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
__IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
__IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
__IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
__IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
__IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
__IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
__IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
__IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
__IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
__IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
__IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
__IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
__IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
__IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
__IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
__IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
__IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
__IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
__IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
__IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
__IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
__IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
__IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
__IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
__IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
__IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
__IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
__IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
__IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
__IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
__IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
__IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
__IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
__IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
__IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
__IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
__IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
__IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
__IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
__IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
__IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
__IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
__IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
__IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
__IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
} LPC_IOCON_Type;
// ------------------------------------------------------------------------------------------------
// ----- SYSCON -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
__IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
__IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
__IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
__I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
__IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
__I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
__I uint32_t RESERVED0[2];
__IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
__IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
__I uint32_t RESERVED1[2];
__IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
__I uint32_t RESERVED2[3];
__IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
__I uint32_t RESERVED3;
__IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
__I uint32_t RESERVED4[9];
__IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
__I uint32_t RESERVED5;
__IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
__I uint32_t RESERVED6;
__IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
__I uint32_t RESERVED7[4];
__IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
__IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
__IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
__I uint32_t RESERVED8[3];
__IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
__IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
__I uint32_t RESERVED9[3];
__IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
__I uint32_t RESERVED10;
__IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
__I uint32_t RESERVED11[5];
__IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
__I uint32_t RESERVED12;
__IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
__I uint32_t RESERVED13[5];
__I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
__I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
__I uint32_t RESERVED14[18];
__IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
__IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
__I uint32_t RESERVED15[6];
__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
__IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
__IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
__IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
__I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
__I uint32_t RESERVED16[25];
__IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
__I uint32_t RESERVED17[3];
__IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
__I uint32_t RESERVED18[6];
__IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
__IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
__IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
__I uint32_t RESERVED19[111];
__I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
} LPC_SYSCON_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_PIN_INT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
__O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
__O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
__O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
} LPC_GPIO_PIN_INT_Type;
// ------------------------------------------------------------------------------------------------
// ----- SSP1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40058000) SSP1 Structure */
__IO uint32_t CR0; /*!< (@ 0x40058000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< (@ 0x40058004) Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< (@ 0x40058008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< (@ 0x4005800C) Status Register */
__IO uint32_t CPSR; /*!< (@ 0x40058010) Clock Prescale Register */
__IO uint32_t IMSC; /*!< (@ 0x40058014) Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< (@ 0x40058018) Raw Interrupt Status Register */
__I uint32_t MIS; /*!< (@ 0x4005801C) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< (@ 0x40058020) SSPICR Interrupt Clear Register */
} LPC_SSP1_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_GROUP_INT0 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
__IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
__I uint32_t RESERVED1[6];
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
} LPC_GPIO_GROUP_INT0_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_GROUP_INT1 -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
__IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
__I uint32_t RESERVED1[6];
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
} LPC_GPIO_GROUP_INT1_Type;
// ------------------------------------------------------------------------------------------------
// ----- Repetitive Interrupt Timer (RIT) -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
__IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
__IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
__IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
__IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
__IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
__IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
__I uint32_t RESERVED0[1];
__IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
} LPC_RITIMER_Type;
// ------------------------------------------------------------------------------------------------
// ----- USB -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x40020000) USB Structure */
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
__IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
__IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
__IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
__IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
__IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
__IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
__IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
__IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
__IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
__IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
__IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
__I uint32_t RESERVED0[1];
__I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
} LPC_USB_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_PORT -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
union {
struct {
__IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
__IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
};
__IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
};
__I uint32_t RESERVED0[1008];
union {
struct {
__IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
__IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
};
__IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
};
__I uint32_t RESERVED1[960];
__IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
__I uint32_t RESERVED2[30];
__IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
__I uint32_t RESERVED3[30];
__IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
__I uint32_t RESERVED4[30];
__IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
__I uint32_t RESERVED5[30];
__IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
__I uint32_t RESERVED6[30];
__O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
__I uint32_t RESERVED7[30];
__O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
} LPC_GPIO_Type;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
// ------------------------------------------------------------------------------------------------
// ----- Peripheral memory map -----
// ------------------------------------------------------------------------------------------------
#define LPC_I2C_BASE (0x40000000)
#define LPC_WWDT_BASE (0x40004000)
#define LPC_USART_BASE (0x40008000)
#define LPC_CT16B0_BASE (0x4000C000)
#define LPC_CT16B1_BASE (0x40010000)
#define LPC_CT32B0_BASE (0x40014000)
#define LPC_CT32B1_BASE (0x40018000)
#define LPC_ADC_BASE (0x4001C000)
#define LPC_PMU_BASE (0x40038000)
#define LPC_FLASHCTRL_BASE (0x4003C000)
#define LPC_SSP0_BASE (0x40040000)
#define LPC_IOCON_BASE (0x40044000)
#define LPC_SYSCON_BASE (0x40048000)
#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
#define LPC_SSP1_BASE (0x40058000)
#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
#define LPC_RITIMER_BASE (0x40064000)
#define LPC_USB_BASE (0x40080000)
#define LPC_GPIO_BASE (0x50000000)
// ------------------------------------------------------------------------------------------------
// ----- Peripheral declaration -----
// ------------------------------------------------------------------------------------------------
#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
#define LPC_CT16B1 ((LPC_CT16B1_Type *) LPC_CT16B1_BASE)
#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
#define LPC_CT32B1 ((LPC_CT32B1_Type *) LPC_CT32B1_BASE)
#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSP1_Type *) LPC_SSP1_BASE)
#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group (null) */
/** @} */ /* End of group h1usf */
#ifdef __cplusplus
}
#endif
#endif // __LPC13UXX_H__

88
hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/power_api.h
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@ -1,88 +0,0 @@
/****************************************************************************
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
* Project: NXP LPC13Uxx software example
*
* Description:
* Power API Header File for NXP LPC13Uxx Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __LPC13UXX_POWER_API_H__
#define __LPC13UXX_POWER_API_H__
#ifdef __cplusplus
extern "C" {
#endif
#define PWRROMD_PRESENT
#define USBROMD_PRESENT
#ifdef USBROMD_PRESENT
#include "mw_usbd_rom_api.h"
#endif
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
typedef struct _ROM {
#ifdef USBROMD_PRESENT
const USBD_API_T * pUSBD;
#else
const unsigned p_usbd;
#endif /* USBROMD_PRESENT */
const unsigned p_clib;
const unsigned p_cand;
#ifdef PWRROMD_PRESENT
const PWRD * pPWRD;
#else
const unsigned p_pwrd;
#endif /* PWRROMD_PRESENT */
const unsigned p_dev1;
const unsigned p_dev2;
const unsigned p_dev3;
const unsigned p_dev4;
} ROM;
//PLL setup related definitions
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
//power setup elated definitions
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
#define MAX_CLOCK_KHZ_PARAM 50000
#ifdef __cplusplus
}
#endif
#endif /* __LPC13UXX_POWER_API_H__ */

64
hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/system_LPC13Uxx.h
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/**************************************************************************//**
* @file system_LPC13Uxx.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
* for the NXP LPC13Uxx Device Series
* @version V1.10
* @date 24. November 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC13Uxx_H
#define __SYSTEM_LPC13Uxx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC13Uxx_H */

32
hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/liblinks.xml
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<!-- liblinks.xml
LPCXpresso "Smart update wizard" script file
When executed on a particular application project, will
add appropriate links to the specified library project.
Note that this script assumes that the application project
contains the standard 'Debug' and 'Release' build
configurations.
-->
<project name="" update="true">
<setting id="all.compiler.inc">
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/inc}</value>
</setting>
<setting id="all.compiler.def">
<value>__USE_CMSIS=CMSIS_CORE_LPC13Uxx</value>
</setting>
<setting id="linker.libs">
<value>CMSIS_CORE_LPC13Uxx</value>
</setting>
<setting id="linker.paths" buildType="Debug">
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Debug}</value>
</setting>
<setting id="linker.paths" buildType="Release">
<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Release}</value>
</setting>
<requires msg="Library project `CMSIS_CORE_LPC13Uxx` not found">
<value>CMSIS_CORE_LPC13Uxx</value>
</requires>
</project>

437
hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/src/system_LPC13Uxx.c
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/******************************************************************************
* @file system_LPC13Uxx.c
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC13xx Device Series
* @version V1.10
* @date 24. November 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC13Uxx.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> System Oscillator Control Register (SYSOSCCTRL)
// <o1.0> BYPASS: System Oscillator Bypass Enable
// <i> If enabled then PLL input (sys_osc_clk) is fed
// <i> directly from XTALIN and XTALOUT pins.
// <o1.9> FREQRANGE: System Oscillator Frequency Range
// <i> Determines frequency range for Low-power oscillator.
// <0=> 1 - 20 MHz
// <1=> 15 - 25 MHz
// </h>
//
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
// <o2.0..4> DIVSEL: Select Divider for Fclkana
// <i> wdt_osc_clk = Fclkana/ (2 <20> (1 + DIVSEL))
// <0-31>
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
// <0=> Undefined
// <1=> 0.5 MHz
// <2=> 0.8 MHz
// <3=> 1.1 MHz
// <4=> 1.4 MHz
// <5=> 1.6 MHz
// <6=> 1.8 MHz
// <7=> 2.0 MHz
// <8=> 2.2 MHz
// <9=> 2.4 MHz
// <10=> 2.6 MHz
// <11=> 2.7 MHz
// <12=> 2.9 MHz
// <13=> 3.1 MHz
// <14=> 3.2 MHz
// <15=> 3.4 MHz
// </h>
//
// <h> System PLL Control Register (SYSPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o3.0..4> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o3.5..6> PSEL: Post Divider Selection
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
//
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
// <o4.0..1> SEL: System PLL Clock Source
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> Main Clock Source Select Register (MAINCLKSEL)
// <o5.0..1> SEL: Clock Source for Main Clock
// <0=> IRC Oscillator
// <1=> Input Clock to System PLL
// <2=> WDT Oscillator
// <3=> System PLL Clock Out
// </h>
//
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
// <o6.0..7> DIV: System AHB Clock Divider
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
// <i> 0 = is disabled
// <0-255>
// </h>
//
// <h> USB PLL Control Register (USBPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o7.0..4> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o7.5..6> PSEL: Post Divider Selection
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
//
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
// <o8.0..1> SEL: USB PLL Clock Source
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> USB Clock Source Select Register (USBCLKSEL)
// <o9.0..1> SEL: System PLL Clock Source
// <0=> USB PLL out
// <1=> Main clock
// <2=> Reserved
// <3=> Reserved
// </h>
//
// <h> USB Clock Divider Register (USBCLKDIV)
// <o10.0..7> DIV: USB Clock Divider
// <i> Divides USB clock to 48 MHz.
// <i> 0 = is disabled
// <0-255>
// </h>
// </e>
*/
#define CLOCK_SETUP 1
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
#error "SYSOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
#error "WDTOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
#error "SYSPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
#error "SYSPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
#error "MAINCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
#error "SYSAHBCLKDIV: Value out of range!"
#endif
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
#error "USBPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
#error "USBPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
#error "USBCLKSEL: Value out of range!"
#endif
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
#error "USBCLKDIV: Value out of range!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (12000000UL) /* Oscillator frequency */
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
#if (CLOCK_SETUP) /* Clock Setup */
#if (__FREQSEL == 0)
#define __WDT_OSC_CLK ( 0) /* undefined */
#elif (__FREQSEL == 1)
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
#elif (__FREQSEL == 2)
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
#elif (__FREQSEL == 3)
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
#elif (__FREQSEL == 4)
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
#elif (__FREQSEL == 5)
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
#elif (__FREQSEL == 6)
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
#elif (__FREQSEL == 7)
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
#elif (__FREQSEL == 8)
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
#elif (__FREQSEL == 9)
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
#elif (__FREQSEL == 10)
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
#elif (__FREQSEL == 11)
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
#elif (__FREQSEL == 12)
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
#elif (__FREQSEL == 13)
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
#elif (__FREQSEL == 14)
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
#else
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
#endif
/* sys_pllclkin calculation */
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
#else
#define __SYS_PLLCLKIN (0)
#endif
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
/* main clock calculation */
#if ((MAINCLKSEL_Val & 0x03) == 0)
#define __MAIN_CLOCK (__IRC_OSC_CLK)
#elif ((MAINCLKSEL_Val & 0x03) == 1)
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
#elif ((MAINCLKSEL_Val & 0x03) == 2)
#if (__FREQSEL == 0)
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
#else
#define __MAIN_CLOCK (__WDT_OSC_CLK)
#endif
#elif ((MAINCLKSEL_Val & 0x03) == 3)
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
#else
#define __MAIN_CLOCK (0)
#endif
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
#else
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
#endif // CLOCK_SETUP
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t wdt_osc = 0;
/* Determine clock frequency according to clock register values */
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
case 0: wdt_osc = 0; break;
case 1: wdt_osc = 500000; break;
case 2: wdt_osc = 800000; break;
case 3: wdt_osc = 1100000; break;
case 4: wdt_osc = 1400000; break;
case 5: wdt_osc = 1600000; break;
case 6: wdt_osc = 1800000; break;
case 7: wdt_osc = 2000000; break;
case 8: wdt_osc = 2200000; break;
case 9: wdt_osc = 2400000; break;
case 10: wdt_osc = 2600000; break;
case 11: wdt_osc = 2700000; break;
case 12: wdt_osc = 2900000; break;
case 13: wdt_osc = 3100000; break;
case 14: wdt_osc = 3200000; break;
case 15: wdt_osc = 3400000; break;
}
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 2: /* WDT Oscillator */
SystemCoreClock = wdt_osc;
break;
case 3: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
SystemCoreClock = __IRC_OSC_CLK;
} else {
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
}
break;
case 1: /* System oscillator */
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
SystemCoreClock = __SYS_OSC_CLK;
} else {
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
}
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
}
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void) {
volatile uint32_t i;
#if (CLOCK_SETUP) /* Clock Setup */
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
for (i = 0; i < 200; i++) __NOP();
#endif
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#endif
#if (((MAINCLKSEL_Val & 0x03) == 2) )
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
for (i = 0; i < 200; i++) __NOP();
#endif
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
/* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
#else /* USB clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
#endif
#endif
/* System clock to the IOCON needs to be enabled or
most of the I/O related peripherals won't work. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
}

44
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/clkconfig.h
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/****************************************************************************
* $Id:: clkconfig.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for clock configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __CLKCONFIG_H
#define __CLKCONFIG_H
#define SYSPLL_SRC_IRC_OSC 0
#define SYSPLL_SRC_SYS_OSC 1
#define MAINCLK_SRC_IRC_OSC 0
#define MAINCLK_SRC_SYSPLL_IN 1
#define MAINCLK_SRC_WDT_OSC 2
#define MAINCLK_SRC_SYS_PLL 3
#define WDTCLK_SRC_IRC_OSC 0
#define WDTCLK_SRC_WDT_OSC 1
#define CLKOUTCLK_SRC_IRC_OSC 0
#define CLKOUTCLK_SRC_SYS_OSC 1
#define CLKOUTCLK_SRC_WDT_OSC 2
#define CLKOUTCLK_SRC_MAIN_CLK 3
void WDT_CLK_Setup(uint32_t timer_num);
void CLKOUT_Setup(uint32_t timer_num);
#endif /* end __CLKCONFIG_H */
/*****************************************************************************
** End Of File
******************************************************************************/

64
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/gpio.h
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/****************************************************************************
* $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for GPIO.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __GPIO_H
#define __GPIO_H
#define CHANNEL0 0
#define CHANNEL1 1
#define CHANNEL2 2
#define CHANNEL3 3
#define CHANNEL4 4
#define CHANNEL5 5
#define CHANNEL6 6
#define CHANNEL7 7
#define PORT0 0
#define PORT1 1
#define GROUP0 0
#define GROUP1 1
void PIN_INT0_IRQHandler(void);
void PIN_INT1_IRQHandler(void);
void PIN_INT2_IRQHandler(void);
void PIN_INT3_IRQHandler(void);
void PIN_INT4_IRQHandler(void);
void PIN_INT5_IRQHandler(void);
void PIN_INT6_IRQHandler(void);
void PIN_INT7_IRQHandler(void);
void GINT0_IRQHandler(void);
void GINT1_IRQHandler(void);
void GPIOInit( void );
void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
uint32_t sense, uint32_t event );
void GPIOPinIntEnable( uint32_t channelNum, uint32_t event );
void GPIOPinIntDisable( uint32_t channelNum, uint32_t event );
uint32_t GPIOPinIntStatus( uint32_t channelNum );
void GPIOPinIntClear( uint32_t channelNum );
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
uint32_t sense, uint32_t *eventPattern );
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
#endif /* end __GPIO_H */
/*****************************************************************************
** End Of File
******************************************************************************/

32
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/nmi.h
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/****************************************************************************
* $Id:: nmi.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx NMI software example
*
* Description:
* This file contains definition and prototype for NMI interrupt.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __NMI_H
#define __NMI_H
#define NMI_ENABLED 1
#define MAX_NMI_NUM 32
void NMI_Init( uint32_t NMI_num );
void NMI_Handler(void);
#endif /* end __NMI_H */
/*****************************************************************************
** End Of File
******************************************************************************/

88
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/power_api.h
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/****************************************************************************
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
* Project: NXP LPC13Uxx software example
*
* Description:
* Power API Header File for NXP LPC13Uxx Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __LPC13UXX_POWER_API_H__
#define __LPC13UXX_POWER_API_H__
#ifdef __cplusplus
extern "C" {
#endif
#define PWRROMD_PRESENT
#define USBROMD_PRESENT
#ifdef USBROMD_PRESENT
#include "mw_usbd_rom_api.h"
#endif
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
typedef struct _ROM {
#ifdef USBROMD_PRESENT
const USBD_API_T * pUSBD;
#else
const unsigned p_usbd;
#endif /* USBROMD_PRESENT */
const unsigned p_clib;
const unsigned p_cand;
#ifdef PWRROMD_PRESENT
const PWRD * pPWRD;
#else
const unsigned p_pwrd;
#endif /* PWRROMD_PRESENT */
const unsigned p_dev1;
const unsigned p_dev2;
const unsigned p_dev3;
const unsigned p_dev4;
} ROM;
//PLL setup related definitions
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
//power setup elated definitions
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
#define MAX_CLOCK_KHZ_PARAM 50000
#ifdef __cplusplus
}
#endif
#endif /* __LPC13UXX_POWER_API_H__ */

59
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer16.h
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/****************************************************************************
* $Id:: timer16.h 6956 2011-03-23 23:03:25Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for 16-bit timer
* configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __TIMER16_H
#define __TIMER16_H
/* The test is either MAT_OUT or CAP_IN. Default is MAT_OUT. */
#define TIMER_MATCH 0
#define EMC0 4
#define EMC1 6
#define EMC2 8
#define EMC3 10
#define MATCH0 (1<<0)
#define MATCH1 (1<<1)
#define MATCH2 (1<<2)
#define MATCH3 (1<<3)
///* For 16-bit timer, make sure that TIME_INTERVAL should be no
//greater than 0xFFFF. */
#ifndef TIME_INTERVAL
#define TIME_INTERVAL (SystemCoreClock/1000 - 1)
#endif
void delayMs(uint8_t timer_num, uint32_t delayInMs);
void CT16B0_IRQHandler(void);
void CT16B1_IRQHandler(void);
void enable_timer16(uint8_t timer_num);
void disable_timer16(uint8_t timer_num);
void reset_timer16(uint8_t timer_num);
void set_timer16_capture(uint8_t timer_num, uint8_t location );
void set_timer16_match(uint8_t timer_num, uint8_t match_enable, uint8_t location);
void init_timer16(uint8_t timer_num, uint32_t timerInterval);
void init_timer16PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable, uint8_t cap_enabled);
void setMatch_timer16PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value);
#endif /* end __TIMER16_H */
/*****************************************************************************
** End Of File
******************************************************************************/

58
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer32.h
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/****************************************************************************
* $Id:: timer32.h 7146 2011-04-19 19:48:01Z nxp28548 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for 32-bit timer
* configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __TIMER32_H
#define __TIMER32_H
/* The test is either MAT_OUT or CAP_IN. Default is CAP_IN. */
#ifndef TIMER_MATCH
#define TIMER_MATCH 0
#endif//TIMER_MATCH
#define EMC0 4
#define EMC1 6
#define EMC2 8
#define EMC3 10
#define MATCH0 (1<<0)
#define MATCH1 (1<<1)
#define MATCH2 (1<<2)
#define MATCH3 (1<<3)
#ifndef TIME_INTERVAL
#define TIME_INTERVAL (SystemCoreClock/100 - 1)
#endif
void delay32Ms(uint8_t timer_num, uint32_t delayInMs);
void CT32B0_IRQHandler(void);
void CT32B1_IRQHandler(void);
void enable_timer32(uint8_t timer_num);
void disable_timer32(uint8_t timer_num);
void reset_timer32(uint8_t timer_num);
void set_timer32_capture(uint8_t timer_num, uint8_t location );
void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location);
void init_timer32(uint8_t timer_num, uint32_t timerInterval);
void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable);
void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value);
#endif /* end __TIMER32_H */
/*****************************************************************************
** End Of File
******************************************************************************/

52
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/type.h
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/****************************************************************************
* $Id:: type.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains different type definition.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __TYPE_H__
#define __TYPE_H__
#if defined (__GNUC__)
#include <stdint.h>
#else
/* exact-width signed integer types */
typedef signed char int8_t;
typedef signed short int int16_t;
typedef signed int int32_t;
//typedef signed __int64 int64_t;
/* exact-width unsigned integer types */
typedef unsigned char uint8_t;
typedef unsigned short int uint16_t;
typedef unsigned int uint32_t;
//typedef unsigned __int64 uint64_t;
#endif
#ifndef NULL
#define NULL ((void *)0)
#endif
#ifndef FALSE
#define FALSE (0)
#endif
#ifndef TRUE
#define TRUE (1)
#endif
#endif /* __TYPE_H__ */

72
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/uart.h
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@ -1,72 +0,0 @@
/****************************************************************************
* $Id:: uart.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for UART configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __UART_H
#define __UART_H
#define AUTOBAUD_ENABLE 0
#define FDR_CALIBRATION 0
#define RS485_ENABLED 0
#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */
#define MODEM_TEST 0
#define IER_RBR (0x01<<0)
#define IER_THRE (0x01<<1)
#define IER_RLS (0x01<<2)
#define IER_ABEO (0x01<<8)
#define IER_ABTO (0x01<<9)
#define IIR_PEND 0x01
#define IIR_RLS 0x03
#define IIR_RDA 0x02
#define IIR_CTI 0x06
#define IIR_THRE 0x01
#define IIR_ABEO (0x01<<8)
#define IIR_ABTO (0x01<<9)
#define LSR_RDR (0x01<<0)
#define LSR_OE (0x01<<1)
#define LSR_PE (0x01<<2)
#define LSR_FE (0x01<<3)
#define LSR_BI (0x01<<4)
#define LSR_THRE (0x01<<5)
#define LSR_TEMT (0x01<<6)
#define LSR_RXFE (0x01<<7)
#define BUFSIZE 0x40
/* RS485 mode definition. */
#define RS485_NMMEN (0x1<<0)
#define RS485_RXDIS (0x1<<1)
#define RS485_AADEN (0x1<<2)
#define RS485_SEL (0x1<<3)
#define RS485_DCTRL (0x1<<4)
#define RS485_OINV (0x1<<5)
void ModemInit( void );
void UARTInit(uint32_t Baudrate);
void USART_IRQHandler(void);
void UARTSend(uint8_t *BufferPtr, uint32_t Length);
void print_string( uint8_t *str_ptr );
uint8_t get_key( void );
#endif /* end __UART_H */
/*****************************************************************************
** End Of File
******************************************************************************/

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hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/usart.h
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/****************************************************************************
* $Id:: usart.h 6172 2011-01-13 18:22:51Z usb00423 $
* Project: NXP LPC13Uxx software example
*
* Description:
* This file contains definition and prototype for UART configuration.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __USART_H
#define __USART_H
/* Synchronous mode control register definition. */
#define SYNC_ON (0x1<<0)
#define SYNC_OFF (0x0<<0)
#define SYNC_MASTER (0x1<<1)
#define SYNC_SLAVE (0x0<<1)
#define SYNC_RE (0x0<<2)
#define SYNC_FE (0x1<<2)
#define SYNC_CONT_CLK_EN (0x1<<4)
#define SYNC_CONT_CLK_DIS (0x0<<4)
#define SYNC_STARTSTOPOFF (0x1<<5)
#define SYNC_STARTSTOPON (0x0<<5)
#define SYNC_CON_CLK_CLR (0x1<<6)
#endif /* end __USART_H */
/*****************************************************************************
** End Of File
******************************************************************************/

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hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/Serial.c
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/******************************************************************************/
/* SERIAL.C: Low Level Serial Routines */
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
#include "LPC13Uxx.h" /* LPC13Uxx definitions */
#include "uart.h"
#define CR 0x0D
/* implementation of putchar (also used by printf function to output data) */
int sendchar (int ch) { /* Write character to Serial Port */
if (ch == '\n') {
while (!(LPC_USART->LSR & 0x20));
LPC_USART->THR = CR; /* output CR */
}
while (!(LPC_USART->LSR & 0x20));
return (LPC_USART->THR = ch);
}
int getkey (void) { /* Read character from Serial Port */
while (!(LPC_USART->LSR & 0x01));
return (LPC_USART->RBR);
}

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hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/clkconfig.c
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/****************************************************************************
* $Id:: clkconfig.c 6874 2011-03-22 01:58:31Z usb00423 $
* Project: NXP LPC13Uxx Clock Configuration example
*
* Description:
* This file contains clock configuration code example which include
* watchdog setup and debug clock out setup.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "clkconfig.h"
/*****************************************************************************
** Function name: WDT_CLK_Setup
**
** Descriptions: Configure WDT clock.
** parameters: clock source: irc_osc(0), main_clk(1), wdt_osc(2).
**
** Returned value: None
**
*****************************************************************************/
void WDT_CLK_Setup ( uint32_t clksrc )
{
/* Freq = 0.5Mhz, div_sel is 0x1F, divided by 64. WDT_OSC should be 7.8125khz */
LPC_SYSCON->WDTOSCCTRL = (0x1<<5)|0x1F;
LPC_SYSCON->PDRUNCFG &= ~(0x1<<6); /* Let WDT clock run */
/* Enables clock for WDT */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<15);
LPC_WWDT->CLKSEL = clksrc; /* Select clock source */
return;
}
/*****************************************************************************
** Function name: CLKOUT_Setup
**
** Descriptions: Configure CLKOUT for reference clock check.
** parameters: clock source: irc_osc(0), sys_osc(1), wdt_osc(2),
** main_clk(3).
**
** Returned value: None
**
*****************************************************************************/
void CLKOUT_Setup ( uint32_t clksrc )
{
/* debug PLL after configuration. */
LPC_SYSCON->CLKOUTSEL = clksrc; /* Select Main clock */
LPC_SYSCON->CLKOUTDIV = 1; /* Divided by 1 */
return;
}

838
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/gpio.c
View File

@ -1,838 +0,0 @@
/****************************************************************************
* $Id:: gpio.c 6874 2011-03-22 01:58:31Z usb00423 $
* Project: NXP LPC13Uxx GPIO example
*
* Description:
* This file contains GPIO code example which include GPIO
* initialization, GPIO interrupt handler, and related APIs for
* GPIO access.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h" /* LPC13Uxx Peripheral Registers */
#include "gpio.h"
volatile uint32_t pin_int0_counter = 0;
volatile uint32_t pin_int1_counter = 0;
volatile uint32_t pin_int2_counter = 0;
volatile uint32_t pin_int3_counter = 0;
volatile uint32_t pin_int4_counter = 0;
volatile uint32_t pin_int5_counter = 0;
volatile uint32_t pin_int6_counter = 0;
volatile uint32_t pin_int7_counter = 0;
volatile uint32_t gint0_counter = 0;
volatile uint32_t gint1_counter = 0;
volatile uint32_t pin_int0_level_counter = 0;
volatile uint32_t pin_int0_rising_edge_counter = 0;
volatile uint32_t pin_int0_falling_edge_counter = 0;
volatile uint32_t pin_int1_level_counter = 0;
volatile uint32_t pin_int1_rising_edge_counter = 0;
volatile uint32_t pin_int1_falling_edge_counter = 0;
volatile uint32_t pin_int2_level_counter = 0;
volatile uint32_t pin_int2_rising_edge_counter = 0;
volatile uint32_t pin_int2_falling_edge_counter = 0;
volatile uint32_t pin_int3_level_counter = 0;
volatile uint32_t pin_int3_rising_edge_counter = 0;
volatile uint32_t pin_int3_falling_edge_counter = 0;
volatile uint32_t pin_int4_level_counter = 0;
volatile uint32_t pin_int4_rising_edge_counter = 0;
volatile uint32_t pin_int4_falling_edge_counter = 0;
volatile uint32_t pin_int5_level_counter = 0;
volatile uint32_t pin_int5_rising_edge_counter = 0;
volatile uint32_t pin_int5_falling_edge_counter = 0;
volatile uint32_t pin_int6_level_counter = 0;
volatile uint32_t pin_int6_rising_edge_counter = 0;
volatile uint32_t pin_int6_falling_edge_counter = 0;
volatile uint32_t pin_int7_level_counter = 0;
volatile uint32_t pin_int7_rising_edge_counter = 0;
volatile uint32_t pin_int7_falling_edge_counter = 0;
volatile uint32_t gint0_level_counter = 0;
volatile uint32_t gint0_edge_counter = 0;
volatile uint32_t gint1_level_counter = 0;
volatile uint32_t gint1_edge_counter = 0;
/*****************************************************************************
** Function name: PIN_INT0_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT0_IRQHandler(void)
{
pin_int0_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<0) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<0) )
{
pin_int0_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<0) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<0) ) )
{
pin_int0_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<0;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<0) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<0) ) )
{
pin_int0_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<0;
}
LPC_GPIO_PIN_INT->IST = 0x1<<0;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT1_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT1_IRQHandler(void)
{
pin_int1_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<1) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<1) )
{
pin_int1_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<1) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<1) ) )
{
pin_int1_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<1;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<1) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<1) ) )
{
pin_int1_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<1;
}
LPC_GPIO_PIN_INT->IST = 0x1<<1;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT2_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT2_IRQHandler(void)
{
pin_int2_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<2) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<2) )
{
pin_int2_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<2) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<2) ) )
{
pin_int2_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<2;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<2) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<2) ) )
{
pin_int2_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<2;
}
LPC_GPIO_PIN_INT->IST = 0x1<<2;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT3_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT3_IRQHandler(void)
{
pin_int3_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<3) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<3) )
{
pin_int3_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<3) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<3) ) )
{
pin_int3_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<3;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<3) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<3) ) )
{
pin_int3_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<3;
}
LPC_GPIO_PIN_INT->IST = 0x1<<3;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT4_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT4_IRQHandler(void)
{
pin_int4_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<4) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<4) )
{
pin_int4_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<4) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<4) ) )
{
pin_int4_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<4;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<4) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<4) ) )
{
pin_int4_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<4;
}
LPC_GPIO_PIN_INT->IST = 0x1<<4;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT5_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT5_IRQHandler(void)
{
pin_int5_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<5) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<5) )
{
pin_int5_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<5) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<5) ) )
{
pin_int5_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<5;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<5) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<5) ) )
{
pin_int5_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<5;
}
LPC_GPIO_PIN_INT->IST = 0x1<<5;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT6_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT6_IRQHandler(void)
{
pin_int6_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<6) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<6) )
{
pin_int6_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<6) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<6) ) )
{
pin_int6_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<6;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<6) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<6) ) )
{
pin_int6_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<6;
}
LPC_GPIO_PIN_INT->IST = 0x1<<6;
}
}
return;
}
/*****************************************************************************
** Function name: PIN_INT7_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void PIN_INT7_IRQHandler(void)
{
pin_int7_counter++;
if ( LPC_GPIO_PIN_INT->IST & (0x1<<7) )
{
if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<7) )
{
pin_int7_level_counter++;
}
else
{
if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<7) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<7) ) )
{
pin_int7_rising_edge_counter++;
LPC_GPIO_PIN_INT->RISE = 0x1<<7;
}
if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<7) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<7) ) )
{
pin_int7_falling_edge_counter++;
LPC_GPIO_PIN_INT->FALL = 0x1<<7;
}
LPC_GPIO_PIN_INT->IST = 0x1<<7;
}
}
return;
}
/*****************************************************************************
** Function name: GINT0_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void GINT0_IRQHandler(void)
{
gint0_counter++;
if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<0) )
{
if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<2) )
{
gint0_level_counter++;
}
else
{
gint0_edge_counter++;
}
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<0);
}
return;
}
/*****************************************************************************
** Function name: GINT1_IRQHandler
**
** Descriptions: Use one GPIO pin as interrupt source
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void GINT1_IRQHandler(void)
{
gint1_counter++;
if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<0) )
{
if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<2) )
{
gint1_level_counter++;
}
else
{
gint1_edge_counter++;
}
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<0);
}
return;
}
/*****************************************************************************
** Function name: GPIOInit
**
** Descriptions: Initialize GPIO, install the
** GPIO interrupt handler
**
** parameters: None
**
** Returned value: true or false, return false if the VIC table
** is full and GPIO interrupt handler can be
** installed.
**
*****************************************************************************/
void GPIOInit( void )
{
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
/* Enable AHB clock to the PinInt, GroupedInt domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
return;
}
/*****************************************************************************
** Function name: GPIOSetPinInterrupt
**
** Descriptions: Set interrupt sense, event, etc.
** sense: edge or level, 0 is edge, 1 is level
** event/polarity: 0 is active low/falling, 1 is high/rising.
**
** parameters: channel #, port #, bit position, sense, event(polarity)
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
uint32_t sense, uint32_t event )
{
switch ( channelNum )
{
case CHANNEL0:
if ( portNum )
{
LPC_SYSCON->PINSEL[0] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[0] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT0_IRQn);
break;
case CHANNEL1:
if ( portNum )
{
LPC_SYSCON->PINSEL[1] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[1] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT1_IRQn);
break;
case CHANNEL2:
if ( portNum )
{
LPC_SYSCON->PINSEL[2] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[2] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT2_IRQn);
break;
case CHANNEL3:
if ( portNum )
{
LPC_SYSCON->PINSEL[3] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[3] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT3_IRQn);
break;
case CHANNEL4:
if ( portNum )
{
LPC_SYSCON->PINSEL[4] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[4] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT4_IRQn);
break;
case CHANNEL5:
if ( portNum )
{
LPC_SYSCON->PINSEL[5] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[5] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT5_IRQn);
break;
case CHANNEL6:
if ( portNum )
{
LPC_SYSCON->PINSEL[6] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[6] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT6_IRQn);
break;
case CHANNEL7:
if ( portNum )
{
LPC_SYSCON->PINSEL[7] = bitPosi + 24;
}
else
{
LPC_SYSCON->PINSEL[7] = bitPosi;
}
NVIC_EnableIRQ(PIN_INT7_IRQn);
break;
default:
break;
}
if ( sense == 0 )
{
LPC_GPIO_PIN_INT->ISEL &= ~(0x1<<channelNum); /* Edge trigger */
if ( event == 0 )
{
LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum); /* faling edge */
}
else
{
LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum); /* Rising edge */
}
}
else
{
LPC_GPIO_PIN_INT->ISEL |= (0x1<<channelNum); /* Level trigger. */
LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum); /* Level enable */
if ( event == 0 )
{
LPC_GPIO_PIN_INT->IENF &= ~(0x1<<channelNum); /* active-low */
}
else
{
LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum); /* active-high */
}
}
return;
}
/*****************************************************************************
** Function name: GPIOPinIntEnable
**
** Descriptions: Enable Interrupt
**
** parameters: channel num, event(0 is falling edge, 1 is rising edge)
** Returned value: None
**
*****************************************************************************/
void GPIOPinIntEnable( uint32_t channelNum, uint32_t event )
{
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
{
if ( event == 0 )
{
LPC_GPIO_PIN_INT->SIENF |= (0x1<<channelNum); /* faling edge */
}
else
{
LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum); /* Rising edge */
}
}
else
{
LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum); /* Level */
}
return;
}
/*****************************************************************************
** Function name: GPIOPinIntDisable
**
** Descriptions: Disable Interrupt
**
** parameters: channel num, event(0 is falling edge, 1 is rising edge)
**
** Returned value: None
**
*****************************************************************************/
void GPIOPinIntDisable( uint32_t channelNum, uint32_t event )
{
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
{
if ( event == 0 )
{
LPC_GPIO_PIN_INT->CIENF |= (0x1<<channelNum); /* faling edge */
}
else
{
LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum); /* Rising edge */
}
}
else
{
LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum); /* Level */
}
return;
}
/*****************************************************************************
** Function name: GPIOPinIntStatus
**
** Descriptions: Get Interrupt status
**
** parameters: channel num
**
** Returned value: None
**
*****************************************************************************/
uint32_t GPIOPinIntStatus( uint32_t channelNum )
{
if ( LPC_GPIO_PIN_INT->IST & (0x1<<channelNum) )
{
return( 1 );
}
else
{
return( 0 );
}
}
/*****************************************************************************
** Function name: GPIOPinIntClear
**
** Descriptions: Clear Interrupt
**
** parameters: channel num
**
** Returned value: None
**
*****************************************************************************/
void GPIOPinIntClear( uint32_t channelNum )
{
if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
{
LPC_GPIO_PIN_INT->IST = (1<<channelNum);
}
return;
}
/*****************************************************************************
** Function name: GPIOSetGroupedInterrupt
**
** Descriptions: Set interrupt logic, sense, eventPattern, etc.
** logic: AND or OR, 0 is OR, 1 is AND
** sensePattern: edge or level, 0 is edge, 1 is level
** event/polarity: 0 is active low/falling, 1 is high/rising.
**
** parameters: group #, bit pattern, logic, sense, event(polarity) pattern
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
uint32_t sense, uint32_t *eventPattern )
{
switch ( groupNum )
{
case GROUP0:
if ( sense == 0 )
{
LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<2); /* Edge trigger */
}
else
{
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<2); /* Level trigger. */
}
if ( logic == 0 )
{
LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<1); /* OR */
}
else
{
LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<1); /* AND */
}
LPC_GPIO_GROUP_INT0->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
LPC_GPIO_GROUP_INT0->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
LPC_GPIO_GROUP_INT0->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
LPC_GPIO_GROUP_INT0->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
/* as soon as enabled, an edge may be generated */
/* clear interrupt flag and NVIC pending interrupt to */
/* workaround the potential edge generated as enabled */
LPC_GPIO_GROUP_INT0->CTRL |= (1<<0);
NVIC_ClearPendingIRQ(GINT0_IRQn);
NVIC_EnableIRQ(GINT0_IRQn);
break;
case GROUP1:
if ( sense == 0 )
{
LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<2); /* Edge trigger */
}
else
{
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<2); /* Level trigger. */
}
if ( logic == 0 )
{
LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<1); /* OR */
}
else
{
LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<1); /* AND */
}
LPC_GPIO_GROUP_INT1->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
LPC_GPIO_GROUP_INT1->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
LPC_GPIO_GROUP_INT1->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
LPC_GPIO_GROUP_INT1->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
/* as soon as enabled, an edge may be generated */
/* clear interrupt flag and NVIC pending interrupt to */
/* workaround the potential edge generated as enabled */
LPC_GPIO_GROUP_INT1->CTRL |= (1<<0);
NVIC_ClearPendingIRQ(GINT1_IRQn);
NVIC_EnableIRQ(GINT1_IRQn);
break;
default:
break;
}
return;
}
/*****************************************************************************
** Function name: GPIOGetPinValue
**
** Descriptions: Read Current state of port pin, PIN register value
**
** parameters: port num, bit position
** Returned value: None
**
*****************************************************************************/
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi )
{
uint32_t regVal = 0;
if( bitPosi < 0x20 )
{
if ( LPC_GPIO->PIN[portNum] & (0x1<<bitPosi) )
{
regVal = 1;
}
}
else if( bitPosi == 0xFF )
{
regVal = LPC_GPIO->PIN[portNum];
}
return ( regVal );
}
/*****************************************************************************
** Function name: GPIOSetBitValue
**
** Descriptions: Set/clear a bit in a specific position
**
** parameters: port num, bit position, bit value
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal )
{
if ( bitVal )
{
LPC_GPIO->SET[portNum] = 1<<bitPosi;
}
else
{
LPC_GPIO->CLR[portNum] = 1<<bitPosi;
}
return;
}
/*****************************************************************************
** Function name: GPIOSetDir
**
** Descriptions: Set the direction in GPIO port
**
** parameters: portNum, bit position, direction (1 out, 0 input)
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir )
{
if( dir )
{
LPC_GPIO->DIR[portNum] |= (1<<bitPosi);
}
else
{
LPC_GPIO->DIR[portNum] &= ~(1<<bitPosi);
}
return;
}
/******************************************************************************
** End Of File
******************************************************************************/

95
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/nmi.c
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@ -1,95 +0,0 @@
/****************************************************************************
* $Id:: nmi.c 7227 2011-04-27 20:20:38Z usb01267 $
* Project: NXP LPC13Uxx NMI interrupt example
*
* Description:
* This file contains NMI interrupt handler code example.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "nmi.h"
#if NMI_ENABLED
volatile uint32_t NMI_Counter[MAX_NMI_NUM];
/*****************************************************************************
** Function name: NMI_Handler
**
** Descriptions: NMI interrupt handler
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void NMI_Handler( void )
{
uint32_t regVal;
regVal = LPC_SYSCON->NMISRC;
regVal &= ~0x80000000;
if ( regVal < MAX_NMI_NUM )
{
if ( regVal == CT16B0_IRQn )
{
/* Use TIMER16_0_IRQHandler as example for real application. */
LPC_CT16B0->IR = 0xFF; /* Clear timer16_0 interrupt */
}
else if ( regVal == CT16B1_IRQn )
{
/* Use TIMER16_1_IRQHandler as example for real application. */
LPC_CT16B1->IR = 0xFF; /* Clear timer16_1 interrupt */
}
else if ( regVal == CT32B0_IRQn )
{
/* Use TIMER32_0_IRQHandler as example for real application. */
LPC_CT32B0->IR = 0xFF; /* Clear timer32_0 interrupt */
}
else if ( regVal == CT32B1_IRQn )
{
/* Use TIMER32_0_IRQHandler as example for real application. */
LPC_CT32B1->IR = 0xFF; /* Clear timer32_1 interrupt */
}
NMI_Counter[regVal]++;
}
return;
}
/*****************************************************************************
** Function name: NMI_Init
**
** Descriptions: NMI initialization
** parameters: NMI number
**
** Returned value: None
**
*****************************************************************************/
void NMI_Init( uint32_t NMI_num )
{
uint32_t i;
for ( i = 0; i < MAX_NMI_NUM; i++ )
{
NMI_Counter[i] = 0x0;
}
LPC_SYSCON->NMISRC = 0x80000000|NMI_num;
return;
}
#endif

628
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer16.c
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@ -1,628 +0,0 @@
/****************************************************************************
* $Id:: timer16.c 6950 2011-03-23 22:09:44Z usb00423 $
* Project: NXP LPC13Uxx 16-bit timer example
*
* Description:
* This file contains 16-bit timer code example which include timer
* initialization, timer interrupt handler, and related APIs for
* timer setup.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "timer16.h"
#include "nmi.h"
volatile uint32_t timer16_0_counter[4] = {0,0,0,0};
volatile uint32_t timer16_1_counter[4] = {0,0,0,0};
volatile uint32_t timer16_0_capture[4] = {0,0,0,0};
volatile uint32_t timer16_1_capture[4] = {0,0,0,0};
volatile uint32_t timer16_0_period = 0;
volatile uint32_t timer16_1_period = 0;
/*****************************************************************************
** Function name: delayMs
**
** Descriptions: Start the timer delay in milo seconds
** until elapsed
**
** parameters: timer number, Delay value in milo second
**
** Returned value: None
**
*****************************************************************************/
void delayMs(uint8_t timer_num, uint32_t delayInMs)
{
if (timer_num == 0)
{
/*
* setup timer #0 for delay
*/
LPC_CT16B0->TCR = 0x02; /* reset timer */
LPC_CT16B0->PR = 0x00; /* set prescaler to zero */
LPC_CT16B0->MR0 = delayInMs * (SystemCoreClock / 1000);
LPC_CT16B0->IR = 0xff; /* reset all interrrupts */
LPC_CT16B0->MCR = 0x04; /* stop timer on match */
LPC_CT16B0->TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (LPC_CT16B0->TCR & 0x01);
}
else if (timer_num == 1)
{
/*
* setup timer #1 for delay
*/
LPC_CT16B1->TCR = 0x02; /* reset timer */
LPC_CT16B1->PR = 0x00; /* set prescaler to zero */
LPC_CT16B1->MR0 = delayInMs * (SystemCoreClock / 1000);
LPC_CT16B1->IR = 0xff; /* reset all interrrupts */
LPC_CT16B1->MCR = 0x04; /* stop timer on match */
LPC_CT16B1->TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (LPC_CT16B1->TCR & 0x01);
}
return;
}
/******************************************************************************
** Function name: CT16B0_IRQHandler
**
** Descriptions: Timer/CounterX and CaptureX interrupt handler
**
** parameters: None
** Returned value: None
**
******************************************************************************/
void CT16B0_IRQHandler(void)
{
if ( LPC_CT16B0->IR & (0x1<<0) )
{
LPC_CT16B0->IR = 0x1<<0; /* clear interrupt flag */
timer16_0_counter[0]++;
}
if ( LPC_CT16B0->IR & (0x1<<1) )
{
LPC_CT16B0->IR = 0x1<<1; /* clear interrupt flag */
timer16_0_counter[1]++;
}
if ( LPC_CT16B0->IR & (0x1<<2) )
{
LPC_CT16B0->IR = 0x1<<2; /* clear interrupt flag */
timer16_0_counter[2]++;
}
if ( LPC_CT16B0->IR & (0x1<<3) )
{
LPC_CT16B0->IR = 0x1<<3; /* clear interrupt flag */
timer16_0_counter[3]++;
}
if ( LPC_CT16B0->IR & (0x1<<4) )
{
LPC_CT16B0->IR = 0x1<<4; /* clear interrupt flag */
timer16_0_capture[0]++;
}
if ( LPC_CT16B0->IR & (0x1<<5) )
{
LPC_CT16B0->IR = 0x1<<5; /* clear interrupt flag */
timer16_0_capture[1]++;
}
if ( LPC_CT16B0->IR & (0x1<<6) )
{
LPC_CT16B0->IR = 0x1<<6; /* clear interrupt flag */
timer16_0_capture[2]++;
}
if ( LPC_CT16B0->IR & (0x1<<7) )
{
LPC_CT16B0->IR = 0x1<<7; /* clear interrupt flag */
timer16_0_capture[3]++;
}
return;
}
/******************************************************************************
** Function name: CT16B1_IRQHandler
**
** Descriptions: Timer/CounterX and CaptureX interrupt handler
**
** parameters: None
** Returned value: None
**
******************************************************************************/
void CT16B1_IRQHandler(void)
{
if ( LPC_CT16B1->IR & (0x1<<0) )
{
LPC_CT16B1->IR = 0x1<<0; /* clear interrupt flag */
timer16_1_counter[0]++;
}
if ( LPC_CT16B1->IR & (0x1<<1) )
{
LPC_CT16B1->IR = 0x1<<1; /* clear interrupt flag */
timer16_1_counter[1]++;
}
if ( LPC_CT16B1->IR & (0x1<<2) )
{
LPC_CT16B1->IR = 0x1<<2; /* clear interrupt flag */
timer16_1_counter[2]++;
}
if ( LPC_CT16B1->IR & (0x1<<3) )
{
LPC_CT16B1->IR = 0x1<<3; /* clear interrupt flag */
timer16_1_counter[3]++;
}
if ( LPC_CT16B1->IR & (0x1<<4) )
{
LPC_CT16B1->IR = 0x1<<4; /* clear interrupt flag */
timer16_1_capture[0]++;
}
if ( LPC_CT16B1->IR & (0x1<<5) )
{
LPC_CT16B1->IR = 0x1<<5; /* clear interrupt flag */
timer16_1_capture[1]++;
}
if ( LPC_CT16B1->IR & (0x1<<6) )
{
LPC_CT16B1->IR = 0x1<<6; /* clear interrupt flag */
timer16_1_capture[2]++;
}
if ( LPC_CT16B1->IR & (0x1<<7) )
{
LPC_CT16B1->IR = 0x1<<7; /* clear interrupt flag */
timer16_1_capture[3]++;
}
return;
}
/******************************************************************************
** Function name: enable_timer
**
** Descriptions: Enable timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void enable_timer16(uint8_t timer_num)
{
if ( timer_num == 0 )
{
LPC_CT16B0->TCR = 1;
}
else
{
LPC_CT16B1->TCR = 1;
}
return;
}
/******************************************************************************
** Function name: disable_timer
**
** Descriptions: Disable timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void disable_timer16(uint8_t timer_num)
{
if ( timer_num == 0 )
{
LPC_CT16B0->TCR = 0;
}
else
{
LPC_CT16B1->TCR = 0;
}
return;
}
/******************************************************************************
** Function name: reset_timer
**
** Descriptions: Reset timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void reset_timer16(uint8_t timer_num)
{
uint32_t regVal;
if ( timer_num == 0 )
{
regVal = LPC_CT16B0->TCR;
regVal |= 0x02;
LPC_CT16B0->TCR = regVal;
}
else
{
regVal = LPC_CT16B1->TCR;
regVal |= 0x02;
LPC_CT16B1->TCR = regVal;
}
return;
}
/******************************************************************************
** Function name: Set_timer_capture
**
** Descriptions: set timer capture based on LOC number.
**
** parameters: timer number and location number
** Returned value: None
**
******************************************************************************/
void set_timer16_capture(uint8_t timer_num, uint8_t location )
{
if ( timer_num == 0 )
{
/* Timer0_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO1_16 &= ~0x07;
LPC_IOCON->PIO1_16 |= 0x02; /* Timer0_16 CAP0 */
LPC_IOCON->PIO1_17 &= ~0x07;
LPC_IOCON->PIO1_17 |= 0x01; /* Timer0_16 CAP2 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO0_2 &= ~0x07;
LPC_IOCON->PIO0_2 |= 0x02; /* Timer0_16 CAP0 */
}
else
{
while ( 1 ); /* Fatal location number error */
}
}
else
{
/* Timer1_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_20 &= ~0x07; /* Timer1_16 I/O config */
LPC_IOCON->PIO0_20 |= 0x01; /* Timer1_16 CAP0 */
LPC_IOCON->PIO1_18 &= ~0x07;
LPC_IOCON->PIO1_18 |= 0x01; /* Timer1_16 CAP1 */
}
else
{
while ( 1 ); /* Fatal location number error */
}
}
return;
}
/******************************************************************************
** Function name: Set_timer_match
**
** Descriptions: set timer match based on LOC number.
**
** parameters: timer number, match enable, and location number
** Returned value: None
**
******************************************************************************/
void set_timer16_match(uint8_t timer_num, uint8_t match_enable, uint8_t location)
{
if ( timer_num == 0 )
{
if ( match_enable & 0x01 )
{
/* Timer0_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_8 &= ~0x07;
LPC_IOCON->PIO0_8 |= 0x02; /* Timer0_16 MAT0 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_13 &= ~0x07;
LPC_IOCON->PIO1_13 |= 0x02; /* Timer0_16 MAT0 */
}
}
if ( match_enable & 0x02 )
{
/* Timer0_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_9 &= ~0x07;
LPC_IOCON->PIO0_9 |= 0x02; /* Timer0_16 MAT1 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_14 &= ~0x07;
LPC_IOCON->PIO1_14 |= 0x02; /* Timer0_16 MAT1 */
}
}
if ( match_enable & 0x04 )
{
/* Timer0_16 I/O config */
if ( location == 0 )
{
#ifdef __SWD_DISABLED
LPC_IOCON->SWCLK_PIO0_10 &= ~0x07;
LPC_IOCON->SWCLK_PIO0_10 |= 0x03; /* Timer0_16 MAT2 */
#endif
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_15 &= ~0x07;
LPC_IOCON->PIO1_15 |= 0x02; /* Timer0_16 MAT2 */
}
}
}
else if ( timer_num == 1 )
{
if ( match_enable & 0x01 )
{
/* Timer1_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_21 &= ~0x07;
LPC_IOCON->PIO0_21 |= 0x01; /* Timer1_16 MAT0 */
}
}
if ( match_enable & 0x02 )
{
/* Timer1_16 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO0_22 &= ~0x07;
LPC_IOCON->PIO0_22 |= 0x02; /* Timer1_16 MAT1 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_23 &= ~0x07;
LPC_IOCON->PIO1_23 |= 0x01; /* Timer1_16 MAT1 */
}
}
}
return;
}
/******************************************************************************
** Function name: init_timer
**
** Descriptions: Initialize timer, set timer interval, reset timer,
** install timer interrupt handler
**
** parameters: timer number and timer interval
** Returned value: None
**
******************************************************************************/
void init_timer16(uint8_t timer_num, uint32_t TimerInterval)
{
uint32_t i;
if ( timer_num == 0 )
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<7);
LPC_CT16B0->MR0 = TimerInterval;
LPC_CT16B0->MR1 = TimerInterval;
#if TIMER_MATCH
for ( i = 0; i < 4; i++ )
{
timer16_0_counter[i] = 0;
}
set_timer16_match(timer_num, 0x07, 0);
LPC_CT16B0->EMR &= ~(0xFF<<4);
LPC_CT16B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8));
#else
for ( i = 0; i < 4; i++ )
{
timer16_0_capture[i] = 0;
}
set_timer16_capture(timer_num, 0);
/* Capture 0 and 2 on rising edge, interrupt enable. */
LPC_CT16B0->CCR = (0x5<<0)|(0x5<<6);
#endif
LPC_CT16B0->MCR = (0x3<<0)|(0x3<<3); /* Interrupt and Reset on MR0 and MR1 */
/* Enable the TIMER0 Interrupt */
#if NMI_ENABLED
NVIC_DisableIRQ(CT16B0_IRQn);
NMI_Init( CT16B0_IRQn );
#else
NVIC_EnableIRQ(CT16B0_IRQn);
#endif
}
else if ( timer_num == 1 )
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);
LPC_CT16B1->MR0 = TimerInterval;
LPC_CT16B1->MR1 = TimerInterval;
#if TIMER_MATCH
for ( i = 0; i < 4; i++ )
{
timer16_1_counter[i] = 0;
}
set_timer16_match(timer_num, 0x07, 0);
LPC_CT16B1->EMR &= ~(0xFF<<4);
LPC_CT16B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8));
#else
for ( i = 0; i < 4; i++ )
{
timer16_1_capture[i] = 0;
}
set_timer16_capture(timer_num, 0);
/* Capture 0 and 1 on rising edge, interrupt enable. */
LPC_CT16B1->CCR = (0x5<<0)|(0x5<<3);
#endif
LPC_CT16B1->MCR = (0x3<<0)|(0x3<<3); /* Interrupt and Reset on MR0 and MR1 */
/* Enable the TIMER1 Interrupt */
#if NMI_ENABLED
NVIC_DisableIRQ(CT16B1_IRQn);
NMI_Init( CT16B1_IRQn );
#else
NVIC_EnableIRQ(CT16B1_IRQn);
#endif
}
return;
}
/******************************************************************************
** Function name: init_timer16PWM
**
** Descriptions: Initialize timer as PWM
**
** parameters: timer number, period and match enable:
** match_enable[0] = PWM for MAT0
** match_enable[1] = PWM for MAT1
** match_enable[2] = PWM for MAT2
**
** Returned value: None
**
******************************************************************************/
void init_timer16PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable, uint8_t cap_enabled)
{
disable_timer16(timer_num);
if (timer_num == 1)
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);
/* Setup the external match register */
LPC_CT16B1->EMR = (1<<EMC3)|(1<<EMC2)|(1<<EMC1)|(2<<EMC0)|(1<<3)|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output */
set_timer16_match(timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT16B1->PWMC = (1<<3)|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer16_1_period = period;
LPC_CT16B1->MR3 = timer16_1_period;
LPC_CT16B1->MR0 = timer16_1_period/2;
LPC_CT16B1->MR1 = timer16_1_period/2;
LPC_CT16B1->MR2 = timer16_1_period/2;
/* Set match control register */
LPC_CT16B1->MCR = 1<<10;// | 1<<9; /* Reset on MR3 */
if (cap_enabled)
{
/* Use location 0 for test. */
set_timer16_capture( timer_num, 0 );
LPC_CT16B1->IR = 0xF; /* clear interrupt flag */
/* Set the capture control register */
LPC_CT16B1->CCR = 7;
}
/* Enable the TIMER1 Interrupt */
NVIC_EnableIRQ(CT16B1_IRQn);
}
else
{
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<7);
/* Setup the external match register */
LPC_CT16B0->EMR = (1<<EMC3)|(1<<EMC2)|(1<<EMC1)|(1<<EMC0)|(1<<3)|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output */
set_timer16_match(timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT16B0->PWMC = (1<<3)|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer16_0_period = period;
LPC_CT16B0->MR3 = timer16_0_period;
LPC_CT16B0->MR0 = timer16_0_period/2;
LPC_CT16B0->MR1 = timer16_0_period/2;
LPC_CT16B0->MR2 = timer16_0_period/2;
/* Set the match control register */
LPC_CT16B0->MCR = 1<<10; /* Reset on MR3 */
/* Enable the TIMER1 Interrupt */
NVIC_EnableIRQ(CT16B0_IRQn);
}
}
/******************************************************************************
** Function name: pwm16_setMatch
**
** Descriptions: Set the pwm16 match values
**
** parameters: timer number, match numner and the value
**
** Returned value: None
**
******************************************************************************/
void setMatch_timer16PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value)
{
if (timer_num)
{
switch (match_nr)
{
case 0:
LPC_CT16B1->MR0 = value;
break;
case 1:
LPC_CT16B1->MR1 = value;
break;
case 2:
LPC_CT16B1->MR2 = value;
break;
case 3:
LPC_CT16B1->MR3 = value;
break;
default:
break;
}
}
else
{
switch (match_nr)
{
case 0:
LPC_CT16B0->MR0 = value;
break;
case 1:
LPC_CT16B0->MR1 = value;
break;
case 2:
LPC_CT16B0->MR2 = value;
break;
case 3:
LPC_CT16B0->MR3 = value;
break;
default:
break;
}
}
}
/******************************************************************************
** End Of File
******************************************************************************/

646
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer32.c
View File

@ -1,646 +0,0 @@
/****************************************************************************
* $Id:: timer32.c 6951 2011-03-23 22:11:07Z usb00423 $
* Project: NXP LPC13Uxx 32-bit timer example
*
* Description:
* This file contains 32-bit timer code example which include timer
* initialization, timer interrupt handler, and related APIs for
* timer setup.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "timer32.h"
#include "nmi.h"
volatile uint32_t timer32_0_counter[4] = {0,0,0,0};
volatile uint32_t timer32_1_counter[4] = {0,0,0,0};
volatile uint32_t timer32_0_capture[4] = {0,0,0,0};
volatile uint32_t timer32_1_capture[4] = {0,0,0,0};
volatile uint32_t timer32_0_period = 0;
volatile uint32_t timer32_1_period = 0;
/*****************************************************************************
** Function name: delay32Ms
**
** Descriptions: Start the timer delay in milo seconds
** until elapsed
**
** parameters: timer number, Delay value in milo second
**
** Returned value: None
**
*****************************************************************************/
void delay32Ms(uint8_t timer_num, uint32_t delayInMs)
{
if (timer_num == 0)
{
/* setup timer #0 for delay */
LPC_CT32B0->TCR = 0x02; /* reset timer */
LPC_CT32B0->PR = 0x00; /* set prescaler to zero */
LPC_CT32B0->MR0 = delayInMs * (SystemCoreClock / 1000);
LPC_CT32B0->IR = 0xff; /* reset all interrrupts */
LPC_CT32B0->MCR = 0x04; /* stop timer on match */
LPC_CT32B0->TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (LPC_CT32B0->TCR & 0x01);
}
else if (timer_num == 1)
{
/* setup timer #1 for delay */
LPC_CT32B1->TCR = 0x02; /* reset timer */
LPC_CT32B1->PR = 0x00; /* set prescaler to zero */
LPC_CT32B1->MR0 = delayInMs * (SystemCoreClock / 1000);
LPC_CT32B1->IR = 0xff; /* reset all interrrupts */
LPC_CT32B1->MCR = 0x04; /* stop timer on match */
LPC_CT32B1->TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (LPC_CT32B1->TCR & 0x01);
}
return;
}
/******************************************************************************
** Function name: CT32B0_IRQHandler
**
** Descriptions: Timer/CounterX and captureX interrupt handler
**
** parameters: None
** Returned value: None
**
******************************************************************************/
void CT32B0_IRQHandler(void)
{
if ( LPC_CT32B0->IR & (0x01<<0) )
{
LPC_CT32B0->IR = 0x1<<0; /* clear interrupt flag */
timer32_0_counter[0]++;
}
if ( LPC_CT32B0->IR & (0x01<<1) )
{
LPC_CT32B0->IR = 0x1<<1; /* clear interrupt flag */
timer32_0_counter[1]++;
}
if ( LPC_CT32B0->IR & (0x01<<2) )
{
LPC_CT32B0->IR = 0x1<<2; /* clear interrupt flag */
timer32_0_counter[2]++;
}
if ( LPC_CT32B0->IR & (0x01<<3) )
{
LPC_CT32B0->IR = 0x1<<3; /* clear interrupt flag */
timer32_0_counter[3]++;
}
if ( LPC_CT32B0->IR & (0x1<<4) )
{
LPC_CT32B0->IR = 0x1<<4; /* clear interrupt flag */
timer32_0_capture[0]++;
}
if ( LPC_CT32B0->IR & (0x1<<5) )
{
LPC_CT32B0->IR = 0x1<<5; /* clear interrupt flag */
timer32_0_capture[1]++;
}
if ( LPC_CT32B0->IR & (0x1<<6) )
{
LPC_CT32B0->IR = 0x1<<6; /* clear interrupt flag */
timer32_0_capture[2]++;
}
if ( LPC_CT32B0->IR & (0x1<<7) )
{
LPC_CT32B0->IR = 0x1<<7; /* clear interrupt flag */
timer32_0_capture[3]++;
}
return;
}
/******************************************************************************
** Function name: CT32B1_IRQHandler
**
** Descriptions: Timer/CounterX and captureX interrupt handler
**
** parameters: None
** Returned value: None
**
******************************************************************************/
void CT32B1_IRQHandler(void)
{
if ( LPC_CT32B1->IR & (0x01<<0) )
{
LPC_CT32B1->IR = 0x1<<0; /* clear interrupt flag */
timer32_1_counter[0]++;
}
if ( LPC_CT32B1->IR & (0x01<<1) )
{
LPC_CT32B1->IR = 0x1<<1; /* clear interrupt flag */
timer32_1_counter[1]++;
}
if ( LPC_CT32B1->IR & (0x01<<2) )
{
LPC_CT32B1->IR = 0x1<<2; /* clear interrupt flag */
timer32_1_counter[2]++;
}
if ( LPC_CT32B1->IR & (0x01<<3) )
{
LPC_CT32B1->IR = 0x1<<3; /* clear interrupt flag */
timer32_1_counter[3]++;
}
if ( LPC_CT32B1->IR & (0x1<<4) )
{
LPC_CT32B1->IR = 0x1<<4; /* clear interrupt flag */
timer32_1_capture[0]++;
}
if ( LPC_CT32B1->IR & (0x1<<5) )
{
LPC_CT32B1->IR = 0x1<<5; /* clear interrupt flag */
timer32_1_capture[1]++;
}
if ( LPC_CT32B1->IR & (0x1<<6) )
{
LPC_CT32B1->IR = 0x1<<6; /* clear interrupt flag */
timer32_1_capture[2]++;
}
if ( LPC_CT32B1->IR & (0x1<<7) )
{
LPC_CT32B1->IR = 0x1<<7; /* clear interrupt flag */
timer32_1_capture[3]++;
}
return;
}
/******************************************************************************
** Function name: enable_timer
**
** Descriptions: Enable timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void enable_timer32(uint8_t timer_num)
{
if ( timer_num == 0 )
{
LPC_CT32B0->TCR = 1;
}
else
{
LPC_CT32B1->TCR = 1;
}
return;
}
/******************************************************************************
** Function name: disable_timer
**
** Descriptions: Disable timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void disable_timer32(uint8_t timer_num)
{
if ( timer_num == 0 )
{
LPC_CT32B0->TCR = 0;
}
else
{
LPC_CT32B1->TCR = 0;
}
return;
}
/******************************************************************************
** Function name: reset_timer
**
** Descriptions: Reset timer
**
** parameters: timer number: 0 or 1
** Returned value: None
**
******************************************************************************/
void reset_timer32(uint8_t timer_num)
{
uint32_t regVal;
if ( timer_num == 0 )
{
regVal = LPC_CT32B0->TCR;
regVal |= 0x02;
LPC_CT32B0->TCR = regVal;
}
else
{
regVal = LPC_CT32B1->TCR;
regVal |= 0x02;
LPC_CT32B1->TCR = regVal;
}
return;
}
/******************************************************************************
** Function name: set_timer_capture
**
** Descriptions: Set timer capture based on location
**
** parameters: timer number: 0~1, location 0~2
** Returned value: None
**
******************************************************************************/
void set_timer32_capture(uint8_t timer_num, uint8_t location )
{
if ( timer_num == 0 )
{
/* Timer0_32 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO1_28 &= ~0x07;
LPC_IOCON->PIO1_28 |= 0x01; /* Timer0_32 CAP0 */
LPC_IOCON->PIO1_29 &= ~0x07;
LPC_IOCON->PIO1_29 |= 0x02; /* Timer0_32 CAP2 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO0_17 &= ~0x07;
LPC_IOCON->PIO0_17 |= 0x02; /* Timer0_32 CAP0 */
}
else
{
while ( 1 ); /* Fatal location number error */
}
}
else
{
/* Timer1_32 I/O config */
if ( location == 0 )
{
LPC_IOCON->PIO1_4 &= ~0x07; /* Timer1_32 I/O config */
LPC_IOCON->PIO1_4 |= 0x01; /* Timer1_32 CAP0 */
LPC_IOCON->PIO1_5 &= ~0x07;
LPC_IOCON->PIO1_5 |= 0x01; /* Timer1_32 CAP1 */
}
else if ( location == 1 )
{
LPC_IOCON->TMS_PIO0_12 &= ~0x07;
LPC_IOCON->TMS_PIO0_12 |= 0x03; /* Timer1_32 CAP0 */
}
else
{
while ( 1 ); /* Fatal location number error */
}
}
return;
}
/******************************************************************************
** Function name: set_timer_match
**
** Descriptions: Set timer match based on location
**
** parameters: timer number: 0~1, location 0~2
** Returned value: None
**
******************************************************************************/
void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location)
{
if ( timer_num == 0 )
{
if ( match_enable & 0x01 )
{
if ( location == 0 )
{
LPC_IOCON->PIO0_18 &= ~0x07;
LPC_IOCON->PIO0_18 |= 0x02; /* Timer0_32 MAT0 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_24 &= ~0x07;
LPC_IOCON->PIO1_24 |= 0x01; /* Timer0_32 MAT0 */
}
}
if ( match_enable & 0x02 )
{
if ( location == 0 )
{
LPC_IOCON->PIO0_19 &= ~0x07;
LPC_IOCON->PIO0_19 |= 0x02; /* Timer0_32 MAT1 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_25 &= ~0x07;
LPC_IOCON->PIO1_25 |= 0x01; /* Timer0_32 MAT1 */
}
}
if ( match_enable & 0x04 )
{
if ( location == 0 )
{
LPC_IOCON->PIO0_1 &= ~0x07;
LPC_IOCON->PIO0_1 |= 0x02; /* Timer0_32 MAT2 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_26 &= ~0x07;
LPC_IOCON->PIO1_26 |= 0x01; /* Timer0_32 MAT2 */
}
}
if ( match_enable & 0x08 )
{
if ( location == 0 )
{
LPC_IOCON->TDI_PIO0_11 &= ~0x07;
LPC_IOCON->TDI_PIO0_11 |= 0x03; /* Timer0_32 MAT3 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO1_27 &= ~0x07;
LPC_IOCON->PIO1_27 |= 0x01; /* Timer0_32 MAT3 */
}
}
}
else if ( timer_num == 1 )
{
if ( match_enable & 0x01 )
{
if ( location == 0 )
{
LPC_IOCON->PIO1_0 &= ~0x07;
LPC_IOCON->PIO1_0 |= 0x01; /* Timer1_32 MAT0 */
}
else if ( location == 1 )
{
LPC_IOCON->TDO_PIO0_13 &= ~0x07;
LPC_IOCON->TDO_PIO0_13 |= 0x03; /* Timer1_32 MAT0 */
}
}
if ( match_enable & 0x02 )
{
if ( location == 0 )
{
LPC_IOCON->PIO1_1 &= ~0x07;
LPC_IOCON->PIO1_1 |= 0x01; /* Timer1_32 MAT1 */
}
else if ( location == 1 )
{
LPC_IOCON->TRST_PIO0_14 &= ~0x07;
LPC_IOCON->TRST_PIO0_14 |= 0x03; /* Timer1_32 MAT1 */
}
}
if ( match_enable & 0x04 )
{
if ( location == 0 )
{
LPC_IOCON->PIO1_2 &= ~0x07;
LPC_IOCON->PIO1_2 |= 0x01; /* Timer1_32 MAT2 */
}
else if ( location == 1 )
{
#if __SWD_DISABLED
LPC_IOCON->SWDIO_PIO0_15 &= ~0x07;
LPC_IOCON->SWDIO_PIO0_15 |= 0x03; /* Timer1_32 MAT2 */
#endif
}
}
if ( match_enable & 0x08 )
{
if ( location == 0 )
{
LPC_IOCON->PIO1_3 &= ~0x07;
LPC_IOCON->PIO1_3 |= 0x01; /* Timer1_32 MAT3 */
}
else if ( location == 1 )
{
LPC_IOCON->PIO0_16 &= ~0x07;
LPC_IOCON->PIO0_16 |= 0x02; /* Timer1_32 MAT3 */
}
}
}
return;
}
/******************************************************************************
** Function name: init_timer
**
** Descriptions: Initialize timer, set timer interval, reset timer,
** install timer interrupt handler
**
** parameters: timer number and timer interval
** Returned value: None
**
******************************************************************************/
void init_timer32(uint8_t timer_num, uint32_t TimerInterval)
{
uint32_t i;
if ( timer_num == 0 )
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
LPC_CT32B0->MR0 = TimerInterval;
#if TIMER_MATCH
for ( i = 0; i < 4; i++ )
{
timer32_0_counter[i] = 0;
}
set_timer32_match(timer_num, 0x0F, 0);
LPC_CT32B0->EMR &= ~(0xFF<<4);
LPC_CT32B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10)); /* MR0/1/2/3 Toggle */
#else
for ( i = 0; i < 4; i++ )
{
timer32_0_capture[i] = 0;
}
set_timer32_capture(timer_num, 0 );
/* Capture 0 on rising edge, interrupt enable. */
LPC_CT32B0->CCR = (0x5<<0)|(0x5<<6);
#endif
LPC_CT32B0->MCR = 3; /* Interrupt and Reset on MR0 */
/* Enable the TIMER0 Interrupt */
#if NMI_ENABLED
NVIC_DisableIRQ( CT32B0_IRQn );
NMI_Init( CT32B0_IRQn );
#else
NVIC_EnableIRQ(CT32B0_IRQn);
#endif
}
else if ( timer_num == 1 )
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
LPC_CT32B1->MR0 = TimerInterval;
#if TIMER_MATCH
for ( i = 0; i < 4; i++ )
{
timer32_1_counter[i] = 0;
}
set_timer32_match(timer_num, 0x0F, 0);
LPC_CT32B1->EMR &= ~(0xFF<<4);
LPC_CT32B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10)); /* MR0/1/2 Toggle */
#else
for ( i = 0; i < 4; i++ )
{
timer32_1_capture[i] = 0;
}
set_timer32_capture(timer_num, 0 );
/* Capture 0 on rising edge, interrupt enable. */
LPC_CT32B1->CCR = (0x5<<0)|(0x5<<3);
#endif
LPC_CT32B1->MCR = 3; /* Interrupt and Reset on MR0 */
/* Enable the TIMER1 Interrupt */
#if NMI_ENABLED
NVIC_DisableIRQ( CT32B1_IRQn );
NMI_Init( CT32B1_IRQn );
#else
NVIC_EnableIRQ(CT32B1_IRQn);
#endif
}
return;
}
/******************************************************************************
** Function name: init_timer32PWM
**
** Descriptions: Initialize timer as PWM
**
** parameters: timer number, period and match enable:
** match_enable[0] = PWM for MAT0
** match_enable[1] = PWM for MAT1
** match_enable[2] = PWM for MAT2
** Returned value: None
**
******************************************************************************/
void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable)
{
disable_timer32(timer_num);
if (timer_num == 1)
{
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
/* Setup the external match register */
LPC_CT32B1->EMR = (1<<EMC3)|(1<<EMC2)|(2<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output, use location 0 for test. */
set_timer32_match( timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT32B1->PWMC = MATCH3|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer32_1_period = period;
LPC_CT32B1->MR3 = timer32_1_period;
LPC_CT32B1->MR0 = timer32_1_period/2;
LPC_CT32B1->MR1 = timer32_1_period/2;
LPC_CT32B1->MR2 = timer32_1_period/2;
LPC_CT32B1->MCR = 1<<10; /* Reset on MR3 */
}
else
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
/* Setup the external match register */
LPC_CT32B0->EMR = (1<<EMC3)|(2<<EMC2)|(1<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output, use location 0 for test. */
set_timer32_match( timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT32B0->PWMC = MATCH3|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer32_0_period = period;
LPC_CT32B0->MR3 = timer32_0_period;
LPC_CT32B0->MR0 = timer32_0_period/2;
LPC_CT32B0->MR1 = timer32_0_period/2;
LPC_CT32B0->MR2 = timer32_0_period/2;
LPC_CT32B0->MCR = 1<<10; /* Reset on MR3 */
}
}
/******************************************************************************
** Function name: pwm32_setMatch
**
** Descriptions: Set the pwm32 match values
**
** parameters: timer number, match numner and the value
**
** Returned value: None
**
******************************************************************************/
void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value)
{
if (timer_num)
{
switch (match_nr)
{
case 0:
LPC_CT32B1->MR0 = value;
break;
case 1:
LPC_CT32B1->MR1 = value;
break;
case 2:
LPC_CT32B1->MR2 = value;
break;
case 3:
LPC_CT32B1->MR3 = value;
break;
default:
break;
}
}
else
{
switch (match_nr)
{
case 0:
LPC_CT32B0->MR0 = value;
break;
case 1:
LPC_CT32B0->MR1 = value;
break;
case 2:
LPC_CT32B0->MR2 = value;
break;
case 3:
LPC_CT32B0->MR3 = value;
break;
default:
break;
}
}
}
/******************************************************************************
** End Of File
******************************************************************************/

437
hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/uart.c
View File

@ -1,437 +0,0 @@
/****************************************************************************
* $Id:: uart.c 7125 2011-04-15 00:22:12Z usb01267 $
* Project: NXP LPC13Uxx UART example
*
* Description:
* This file contains UART code example which include UART
* initialization, UART interrupt handler, and related APIs for
* UART access.
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC13Uxx.h"
#include "type.h"
#include "uart.h"
volatile uint32_t UARTStatus;
volatile uint8_t UARTTxEmpty = 1;
volatile uint8_t UARTBuffer[BUFSIZE];
volatile uint32_t UARTCount = 0;
#if AUTOBAUD_ENABLE
volatile uint32_t UARTAutoBaud = 0, AutoBaudTimeout = 0;
#endif
/*****************************************************************************
** Function name: USART_IRQHandler
**
** Descriptions: USART interrupt handler
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void USART_IRQHandler(void)
{
uint8_t IIRValue, LSRValue;
uint8_t Dummy = Dummy;
IIRValue = LPC_USART->IIR;
IIRValue >>= 1; /* skip pending bit in IIR */
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
if (IIRValue == IIR_RLS) /* Receive Line Status */
{
LSRValue = LPC_USART->LSR;
/* Receive Line Status */
if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
{
/* There are errors or break interrupt */
/* Read LSR will clear the interrupt */
UARTStatus = LSRValue;
Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
interrupt, then bail out */
return;
}
if (LSRValue & LSR_RDR) /* Receive Data Ready */
{
/* If no error on RLS, normal ready, save into the data buffer. */
/* Note: read RBR will clear the interrupt */
UARTBuffer[UARTCount++] = LPC_USART->RBR;
if (UARTCount == BUFSIZE)
{
UARTCount = 0; /* buffer overflow */
}
}
}
else if (IIRValue == IIR_RDA) /* Receive Data Available */
{
/* Receive Data Available */
UARTBuffer[UARTCount++] = LPC_USART->RBR;
if (UARTCount == BUFSIZE)
{
UARTCount = 0; /* buffer overflow */
}
}
else if (IIRValue == IIR_CTI) /* Character timeout indicator */
{
/* Character Time-out indicator */
UARTStatus |= 0x100; /* Bit 9 as the CTI error */
}
else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */
{
/* THRE interrupt */
LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
valid data in U0THR or not */
if (LSRValue & LSR_THRE)
{
UARTTxEmpty = 1;
}
else
{
UARTTxEmpty = 0;
}
}
#if AUTOBAUD_ENABLE
if (LPC_USART->IIR & IIR_ABEO) /* End of Auto baud */
{
LPC_USART->IER &= ~IIR_ABEO;
/* clear bit ABEOInt in the IIR by set ABEOIntClr in the ACR register */
LPC_USART->ACR |= IIR_ABEO;
UARTAutoBaud = 1;
}
else if (LPC_USART->IIR & IIR_ABTO)/* Auto baud time out */
{
LPC_USART->IER &= ~IIR_ABTO;
AutoBaudTimeout = 1;
/* clear bit ABTOInt in the IIR by set ABTOIntClr in the ACR register */
LPC_USART->ACR |= IIR_ABTO;
}
#endif
return;
}
#if MODEM_TEST
/*****************************************************************************
** Function name: ModemInit
**
** Descriptions: Initialize UART0 port as modem, setup pin select.
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void ModemInit( void )
{
LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */
LPC_IOCON->PIO0_17 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO0_17 |= 0x01; /* UART RTS */
#if 1
LPC_IOCON->PIO1_13 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_13 |= 0x01; /* UART DTR */
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_14 |= 0x01; /* UART DSR */
LPC_IOCON->PIO1_15 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_15 |= 0x01; /* UART DCD */
LPC_IOCON->PIO1_16 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_16 |= 0x01; /* UART RI */
#else
LPC_IOCON->PIO1_19 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_19 |= 0x01; /* UART DTR */
LPC_IOCON->PIO1_20 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_20 |= 0x01; /* UART DSR */
LPC_IOCON->PIO1_21 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_21 |= 0x01; /* UART DCD */
LPC_IOCON->PIO1_22 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_22 |= 0x01; /* UART RI */
#endif
LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */
return;
}
#endif
/***********************************************************************
*
* Function: uart_set_divisors
*
* Purpose: Determines best dividers to get a target clock rate
*
* Processing:
* See function.
*
* Parameters:
* UARTClk : UART clock
* baudrate : Desired UART baud rate
*
* Outputs:
* baudrate : Sets the estimated buadrate value in DLL, DLM, and FDR.
*
* Returns: Error status.
*
* Notes: None
*
**********************************************************************/
uint32_t uart_set_divisors(uint32_t UARTClk, uint32_t baudrate)
{
uint32_t uClk;
uint32_t calcBaudrate = 0;
uint32_t temp = 0;
uint32_t mulFracDiv, dividerAddFracDiv;
uint32_t diviser = 0 ;
uint32_t mulFracDivOptimal = 1;
uint32_t dividerAddOptimal = 0;
uint32_t diviserOptimal = 0;
uint32_t relativeError = 0;
uint32_t relativeOptimalError = 100000;
/* get UART block clock */
uClk = UARTClk >> 4; /* div by 16 */
/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
* The formula is :
* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
* It involves floating point calculations. That's the reason the formulae are adjusted with
* Multiply and divide method.*/
/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
for (mulFracDiv = 1; mulFracDiv <= 15; mulFracDiv++)
{
for (dividerAddFracDiv = 0; dividerAddFracDiv <= 15; dividerAddFracDiv++)
{
temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
diviser = temp / baudrate;
if ((temp % baudrate) > (baudrate / 2))
diviser++;
if (diviser > 2 && diviser < 65536)
{
calcBaudrate = temp / diviser;
if (calcBaudrate <= baudrate)
relativeError = baudrate - calcBaudrate;
else
relativeError = calcBaudrate - baudrate;
if ((relativeError < relativeOptimalError))
{
mulFracDivOptimal = mulFracDiv ;
dividerAddOptimal = dividerAddFracDiv;
diviserOptimal = diviser;
relativeOptimalError = relativeError;
if (relativeError == 0)
break;
}
} /* End of if */
} /* end of inner for loop */
if (relativeError == 0)
break;
} /* end of outer for loop */
if (relativeOptimalError < (baudrate / 30))
{
/* Set the `Divisor Latch Access Bit` and enable so the DLL/DLM access*/
/* Initialise the `Divisor latch LSB` and `Divisor latch MSB` registers */
LPC_USART->DLM = (diviserOptimal >> 8) & 0xFF;
LPC_USART->DLL = diviserOptimal & 0xFF;
/* Initialise the Fractional Divider Register */
LPC_USART->FDR = ((mulFracDivOptimal & 0xF) << 4) | (dividerAddOptimal & 0xF);
return( TRUE );
}
return ( FALSE );
}
/*****************************************************************************
** Function name: UARTInit
**
** Descriptions: Initialize UART0 port, setup pin select,
** clock, parity, stop bits, FIFO, etc.
**
** parameters: UART baudrate
** Returned value: None
**
*****************************************************************************/
void UARTInit(uint32_t baudrate)
{
#if !AUTOBAUD_ENABLE
uint32_t Fdiv;
#endif
volatile uint32_t regVal;
UARTTxEmpty = 1;
UARTCount = 0;
NVIC_DisableIRQ(USART_IRQn);
/* Select only one location from below. */
#if 1
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
LPC_IOCON->PIO0_19 &= ~0x07;
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_14 |= 0x03; /* UART RXD */
LPC_IOCON->PIO1_13 &= ~0x07;
LPC_IOCON->PIO1_13 |= 0x03; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_17 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_17 |= 0x02; /* UART RXD */
LPC_IOCON->PIO1_18 &= ~0x07;
LPC_IOCON->PIO1_18 |= 0x02; /* UART TXD */
#endif
#if 0
LPC_IOCON->PIO1_26 &= ~0x07; /* UART I/O config */
LPC_IOCON->PIO1_26 |= 0x02; /* UART RXD */
LPC_IOCON->PIO1_27 &= ~0x07;
LPC_IOCON->PIO1_27 |= 0x02; /* UART TXD */
#endif
/* Enable UART clock */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */
LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
#if !AUTOBAUD_ENABLE
#if FDR_CALIBRATION
if ( uart_set_divisors(SystemCoreClock/LPC_SYSCON->UARTCLKDIV, baudrate) != TRUE )
{
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
LPC_USART->DLM = Fdiv / 256;
LPC_USART->DLL = Fdiv % 256;
LPC_USART->FDR = 0x10; /* Default */
}
#else
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
LPC_USART->DLM = Fdiv / 256;
LPC_USART->DLL = Fdiv % 256;
LPC_USART->FDR = 0x10; /* Default */
#endif
#endif
LPC_USART->LCR = 0x03; /* DLAB = 0 */
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
/* Read to clear the line status. */
regVal = LPC_USART->LSR;
/* Ensure a clean start, no data in either TX or RX FIFO. */
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
while ( LPC_USART->LSR & LSR_RDR )
{
regVal = LPC_USART->RBR; /* Dump data from RX FIFO */
}
/* Enable the UART Interrupt */
NVIC_EnableIRQ(USART_IRQn);
#if TX_INTERRUPT
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
#else
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
#endif
#if AUTOBAUD_ENABLE
LPC_USART->IER |= IER_ABEO | IER_ABTO;
#endif
return;
}
/*****************************************************************************
** Function name: UARTSend
**
** Descriptions: Send a block of data to the UART 0 port based
** on the data length
**
** parameters: buffer pointer, and data length
** Returned value: None
**
*****************************************************************************/
void UARTSend(uint8_t *BufferPtr, uint32_t Length)
{
while ( Length != 0 )
{
/* THRE status, contain valid data */
#if !TX_INTERRUPT
while ( !(LPC_USART->LSR & LSR_THRE) );
LPC_USART->THR = *BufferPtr;
#else
/* Below flag is set inside the interrupt handler when THRE occurs. */
while ( !(UARTTxEmpty & 0x01) );
LPC_USART->THR = *BufferPtr;
UARTTxEmpty = 0; /* not empty in the THR until it shifts out */
#endif
BufferPtr++;
Length--;
}
return;
}
/*****************************************************************************
** Function name: print_string
**
** Descriptions: print out string on the terminal
**
** parameters: pointer to the string end with NULL char.
** Returned value: none.
**
*****************************************************************************/
void print_string( uint8_t *str_ptr )
{
while(*str_ptr != 0x00)
{
while((LPC_USART->LSR & 0x60) != 0x60);
LPC_USART->THR = *str_ptr;
str_ptr++;
}
return;
}
/*****************************************************************************
** Function name: get_key
**
** Descriptions: Get a character from the terminal
**
** parameters: None
** Returned value: character, zero is none.
**
*****************************************************************************/
uint8_t get_key( void )
{
uint8_t dummy;
while ( !(LPC_USART->LSR & 0x01) );
dummy = LPC_USART->RBR;
if ((dummy>=65) && (dummy<=90))
{
/* convert capital to non-capital character, A2a, B2b, C2c. */
dummy +=32;
}
/* echo */
LPC_USART->THR = dummy;
return(dummy);
}
/******************************************************************************
** End Of File
******************************************************************************/

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&lt;info chip="LPC1347" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
&lt;chip&gt;&#13;
&lt;name&gt;LPC1347&lt;/name&gt;&#13;
&lt;family&gt;LPC13xx (12bit ADC)&lt;/family&gt;&#13;
&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
&lt;memory id="RAM" type="RAM"/&gt;&#13;
&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/&gt;&#13;
&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_ITM" determined="infoFile" id="ITM" location="0xe0000000"/&gt;&#13;
&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
&lt;peripheralInstance derived_from="RITIMER" determined="infoFile" id="RITIMER" location="0x40064000"/&gt;&#13;
&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&#13;
&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="nxp_lpc13Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
&lt;/info&gt;&#13;
&lt;/infoList&gt;&#13;
&lt;/TargetConfig&gt;</projectStorage>
</storageModule>
</cproject>

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>lpc_chip_13xx</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
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</arguments>
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<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
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</projectDescription>

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hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/adc_13xx.h Normal file
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/*
* @brief LPC13xx A/D conversion driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __ADC_13XX_H_
#define __ADC_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup ADC_13XX CHIP: LPC13xx A/D conversion driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
#if defined(CHIP_LPC1347)
#define ADC_ACC_12BITS
#define ADC_TRIM_SUPPORT
#else
#define ADC_ACC_10BITS
#endif
#if defined(CHIP_LPC1347)
#define ADC_MAX_SAMPLE_RATE 500000
#else
#define ADC_MAX_SAMPLE_RATE 400000
#endif
/**
* @brief 10 or 12-bit ADC register block structure
*/
typedef struct { /*!< ADCn Structure */
__IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
__I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
__I uint32_t RESERVED0;
__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
__I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
__I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
#if defined(ADC_TRIM_SUPPORT)
__IO uint32_t ADTRM;
#endif
} LPC_ADC_T;
/**
* @brief ADC register support bitfields and mask
*/
#if defined(ADC_ACC_12BITS)
#define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF)) /*!< Mask for getting the 12 bits ADC data read value */
#else
#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */
#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */
#endif
#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */
#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */
#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */
#if defined(CHIP_LPC1347)
#define ADC_CR_LPWRMODE ((1UL << 22)) /*!<Enable the low-power ADC mode */
#define ADC_CR_MODE10BIT ((1UL << 23)) /*!<Enable the 10-bit conversion rate mode with high conversion rate. */
#else
#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert is operational */
#endif
#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */
#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */
#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */
#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */
#if defined(CHIP_LPC1347)
#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_MODE10BIT)
#else
#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))
#endif
/**
* @brief ADC status register used for IP drivers
*/
typedef enum IP_ADC_STATUS {
ADC_DR_DONE_STAT, /*!< ADC data register staus */
ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
ADC_DR_ADINT_STAT /*!< ADC interrupt status */
} ADC_STATUS_T;
/** The channels on one ADC peripheral*/
typedef enum CHIP_ADC_CHANNEL {
ADC_CH0 = 0, /**< ADC channel 0 */
ADC_CH1, /**< ADC channel 1 */
ADC_CH2, /**< ADC channel 2 */
ADC_CH3, /**< ADC channel 3 */
ADC_CH4, /**< ADC channel 4 */
ADC_CH5, /**< ADC channel 5 */
ADC_CH6, /**< ADC channel 6 */
ADC_CH7, /**< ADC channel 7 */
} ADC_CHANNEL_T;
#if defined(CHIP_LPC1347)
/** LPC1347 chip */
typedef enum CHIP_ADC_RESOLUTION {
ADC_12BITS = 0, /**< ADC 12 bits */
ADC_10BITS = 1, /**< ADC 10 bits */
} ADC_RESOLUTION_T;
#else
/** The number of bits of accuracy of the result in the LS bits of ADDR*/
typedef enum CHIP_ADC_RESOLUTION {
ADC_10BITS = 0, /**< ADC 10 bits */
ADC_9BITS, /**< ADC 9 bits */
ADC_8BITS, /**< ADC 8 bits */
ADC_7BITS, /**< ADC 7 bits */
ADC_6BITS, /**< ADC 6 bits */
ADC_5BITS, /**< ADC 5 bits */
ADC_4BITS, /**< ADC 4 bits */
ADC_3BITS, /**< ADC 3 bits */
} ADC_RESOLUTION_T;
#endif
/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
typedef enum CHIP_ADC_EDGE_CFG {
ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */
ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */
} ADC_EDGE_CFG_T;
/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
typedef enum CHIP_ADC_START_MODE {
ADC_NO_START = 0,
ADC_START_NOW, /*!< Start conversion now */
ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
} ADC_START_MODE_T;
/** Clock setup structure for ADC controller passed to the initialize function */
typedef struct {
uint32_t adcRate; /*!< ADC rate */
uint8_t bitsAccuracy; /*!< ADC bit accuracy */
bool burstMode; /*!< ADC Burt Mode */
} ADC_CLOCK_SETUP_T;
/**
* @brief Initialize the ADC peripheral and the ADC setup structure to default value
* @param pADC : The base of ADC peripheral on the chip
* @param ADCSetup : ADC setup structure to be set
* @return Nothing
* @note Default setting for ADC is 400kHz - 10bits
*/
void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup);
/**
* @brief Shutdown ADC
* @param pADC : The base of ADC peripheral on the chip
* @return Nothing
*/
void Chip_ADC_DeInit(LPC_ADC_T *pADC);
/**
* @brief Read the ADC value from a channel
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param data : Pointer to where to put data
* @return SUCCESS or ERROR if no conversion is ready
*/
Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data);
/**
* @brief Read the ADC value and convert it to 8bits value
* @param pADC : The base of ADC peripheral on the chip
* @param channel: selected channel
* @param data : Storage for data
* @return Status : ERROR or SUCCESS
*/
Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data);
/**
* @brief Read the ADC channel status
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param StatusType : Status type of ADC_DR_*
* @return SET or RESET
*/
FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType);
/**
* @brief Enable/Disable interrupt for ADC channel
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param NewState : New state, ENABLE or DISABLE
* @return SET or RESET
*/
void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState);
/**
* @brief Enable/Disable global interrupt for ADC channel
* @param pADC : The base of ADC peripheral on the chip
* @param NewState : New state, ENABLE or DISABLE
* @return Nothing
*/
STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState)
{
Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState);
}
/**
* @brief Select the mode starting the AD conversion
* @param pADC : The base of ADC peripheral on the chip
* @param mode : Stating mode, should be :
* - ADC_NO_START : Must be set for Burst mode
* - ADC_START_NOW : Start conversion now
* - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15
* - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8
* - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
* - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
* - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
* @param EdgeOption : Stating Edge Condition, should be :
* - ADC_TRIGGERMODE_RISING : Trigger event on rising edge
* - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge
* @return Nothing
*/
void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption);
/**
* @brief Set the ADC Sample rate
* @param pADC : The base of ADC peripheral on the chip
* @param ADCSetup : ADC setup structure to be modified
* @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
* @return Nothing
*/
void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate);
/**
* @brief Set the ADC accuracy bits
* @param pADC : The base of ADC peripheral on the chip
* @param ADCSetup : ADC setup structure to be modified
* @param resolution : The resolution, should be ADC_10BITS -> ADC_3BITS
* @return Nothing
*/
void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution);
/**
* @brief Enable or disable the ADC channel on ADC peripheral
* @param pADC : The base of ADC peripheral on the chip
* @param channel : Channel to be enable or disable
* @param NewState : New state, should be:
* - ENABLE
* - DISABLE
* @return Nothing
*/
void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState);
/**
* @brief Enable burst mode
* @param pADC : The base of ADC peripheral on the chip
* @param NewState : New state, should be:
* - ENABLE
* - DISABLE
* @return Nothing
*/
void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ADC_13XX_H_ */

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/*
* @brief LPC13xx basic chip inclusion file
*
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CHIP_H_
#define __CHIP_H_
#include "lpc_types.h"
#include "sys_config.h"
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef CORE_M3
#error CORE_M3 is not defined for the LPC13xx architecture
#error CORE_M3 should be defined as part of your compiler define list
#endif
#if !defined(CHIP_LPC1343) && !defined(CHIP_LPC1347)
#error CHIP_LPC1343 or CHIP_LPC1347 is not defined!
#endif
/* Peripheral mapping per device
Peripheral Device(s)
---------------------------- ------------------------------------------------------------------------------
I2C(40000000) CHIP_LPC1343/CHIP_LPC1347
WDT(40004000) CHIP_LPC1343/CHIP_LPC1347
TIMER0_16(4000C000) CHIP_LPC1343/CHIP_LPC1347
TIMER1_16(40010000) CHIP_LPC1343/CHIP_LPC1347
TIMER0_32(40014000) CHIP_LPC1343/CHIP_LPC1347
TIMER1_32(40018000) CHIP_LPC1343/CHIP_LPC1347
PMU(40038000) CHIP_LPC1343/CHIP_LPC1347
FLASH_CTRL(4003C000) CHIP_LPC1343/CHIP_LPC1347
SSP0(40040000) CHIP_LPC1343/CHIP_LPC1347
IOCONF(40044000) CHIP_LPC1343/CHIP_LPC1347
SYSCTL(40048000) CHIP_LPC1343/CHIP_LPC1347
SSP1(40058000) CHIP_LPC1347
ADC(4001C000) CHIP_LPC1343/CHIP_LPC1347
UART(40008000) CHIP_LPC1343 only
USB(40020000) CHIP_LPC1343 only
GPIO_PORT(50000000) CHIP_LPC1343 only
GPIO_PIO0(50000000) CHIP_LPC1343 only
GPIO_PIO1(50010000) CHIP_LPC1343 only
GPIO_PIO2(50020000) CHIP_LPC1343 only
GPIO_PIO3(50030000) CHIP_LPC1343 only
USART/SMARTCARD(40008000) CHIP_LPC1347 only
FLASH_EEPROM(4003C000) CHIP_LPC1347 only
GPIO_INT(4004C000) CHIP_LPC1347 only
GPIO_GRP0_INT(4005C000) CHIP_LPC1347 only
GPIO_GRP1_INT(40060000) CHIP_LPC1347 only
RITIMER(40064000) CHIP_LPC1347 only
*/
/** @defgroup PERIPH_13XX_BASE CHIP: LPC13xx Peripheral addresses and register set declarations
* @ingroup CHIP_13XX_Drivers
* @{
*/
#define LPC_I2C_BASE 0x40000000
#define LPC_WWDT_BASE 0x40004000
#define LPC_USART_BASE 0x40008000
#define LPC_TIMER16_0_BASE 0x4000C000
#define LPC_TIMER16_1_BASE 0x40010000
#define LPC_TIMER32_0_BASE 0x40014000
#define LPC_TIMER32_1_BASE 0x40018000
#define LPC_ADC_BASE 0x4001C000
#define LPC_PMU_BASE 0x40038000
#define LPC_FLASH_BASE 0x4003C000
#define LPC_SSP0_BASE 0x40040000
#define LPC_SSP1_BASE 0x40058000
#define LPC_IOCON_BASE 0x40044000
#define LPC_SYSCTL_BASE 0x40048000
#if defined(CHIP_LPC1347)
#define LPC_GPIO_PIN_INT_BASE 0x4004C000
#define LPC_GPIO_GROUP_INT0_BASE 0x4005C000
#define LPC_GPIO_GROUP_INT1_BASE 0x40060000
#define LPC_GPIO_PORT_BASE 0x50000000
#define LPC_USB0_BASE 0x40080000
#define LPC_RITIMER_BASE 0x40064000
#define IAP_ENTRY_LOCATION 0X1FFF1FF1
#define LPC_ROM_API_BASE_LOC 0x1FFF1FF8
#else /*CHIP_LPC1343*/
#define LPC_GPIO_PORT0_BASE 0x50000000
#define LPC_GPIO_PORT1_BASE 0x50010000
#define LPC_GPIO_PORT2_BASE 0x50020000
#define LPC_GPIO_PORT3_BASE 0x50030000
#define LPC_USB0_BASE 0x40020000
#endif
#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
#define LPC_I2C ((LPC_I2C_T *) LPC_I2C_BASE)
#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
#define LPC_USART ((LPC_USART_T *) LPC_USART_BASE)
#define LPC_TIMER16_0 ((LPC_TIMER_T *) LPC_TIMER16_0_BASE)
#define LPC_TIMER16_1 ((LPC_TIMER_T *) LPC_TIMER16_1_BASE)
#define LPC_TIMER32_0 ((LPC_TIMER_T *) LPC_TIMER32_0_BASE)
#define LPC_TIMER32_1 ((LPC_TIMER_T *) LPC_TIMER32_1_BASE)
#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
#define LPC_FMC ((LPC_FMC_T *) LPC_FLASH_BASE)
#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
#define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
#if defined(CHIP_LPC1347)
#define LPC_PININT ((LPC_PIN_INT_T *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIO_GROUP_INT0 ((LPC_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO_GROUP_INT1 ((LPC_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
#define LPC_USB ((LPC_USB_T *) LPC_USB0_BASE)
#define LPC_ROM_API (*((LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC))
#else
#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT0_BASE)
#endif
/**
* @}
*/
/** @ingroup CHIP_13XX_DRIVER_OPTIONS
* @{
*/
/**
* @brief System oscillator rate
* This value is defined externally to the chip layer and contains
* the value in Hz for the external oscillator for the board. If using the
* internal oscillator, this rate can be 0.
*/
extern const uint32_t OscRateIn;
/**
* @brief Clock rate on the CLKIN pin
* This value is defined externally to the chip layer and contains
* the value in Hz for the CLKIN pin for the board. If this pin isn't used,
* this rate can be 0.
*/
extern const uint32_t ExtRateIn;
/**
* @}
*/
#include "sysctl_13xx.h"
#include "clock_13xx.h"
#include "fmc_13xx.h"
#include "iocon_13xx.h"
#include "adc_13xx.h"
#include "i2c_13xx.h"
#include "i2cm_13xx.h"
#include "pmu_13xx.h"
#include "ssp_13xx.h"
#include "timer_13xx.h"
#include "uart_13xx.h"
#include "wwdt_13xx.h"
#include "flash_13xx.h"
#if defined(CHIP_LPC1347)
#include "gpio_13xx_1.h"
#include "gpiogroup_13xx.h"
#include "ritimer_13xx.h"
#include "usbd_13xx.h"
#include "romapi_13xx.h"
#include "pinint_13xx.h"
#else
#include "gpio_13xx_2.h"
#endif
/** @defgroup SUPPORT_13XX_FUNC CHIP: LPC13xx support functions
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief Current system clock rate, mainly used for sysTick
*/
extern uint32_t SystemCoreClock;
/**
* @brief Update system core clock rate, should be called if the
* system has a clock rate change
* @return None
*/
void SystemCoreClockUpdate(void);
/**
* @brief USB Pin and clock initialization
* Calling this function will initialize the USB pins and the clock
* @return None
* @note This function will assume that the chip is clocked by an
* external crystal oscillator of frequency 12MHz and the Oscillator
* is running.
*/
void Chip_USB_Init(void);
/**
* @brief Clock and PLL initialization based on the external oscillator
* @return None
* @note This function assumes an external crystal oscillator
* frequency of 12MHz.
*/
void Chip_SetupXtalClocking(void);
/**
* @brief Clock and PLL initialization based on the internal oscillator
* @return None
*/
void Chip_SetupIrcClocking(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CHIP_H_ */

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/*
* @brief LPC13XX Clock control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CLOCK_13XX_H_
#define __CLOCK_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CLOCK_13XX CHIP: LPC13xx Clock Control block driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
/** @defgroup CLOCK_13XX_OPTIONS CHIP: LPC13xx Clock Control driver options
* @ingroup CHIP_13XX_DRIVER_OPTIONS CLOCK_13XX
* The clock driver has options that configure it's operation at build-time.<br>
*
* <b>CRYSTAL_MAIN_FREQ_IN</b><br>
* This define is the external crystal frequency used for the main oscillator.<br>
* @{
*/
/**
* @}
*/
/** Internal oscillator frequency */
#define SYSCTL_IRC_FREQ (12000000)
/**
* @brief Set System PLL divider values
* @param msel : PLL feedback divider value. M = msel + 1.
* @param psel : PLL post divider value. P = (1<<psel).
* @return Nothing
* @note See the user manual for how to setup the PLL.
*/
STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
{
LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
}
/**
* @brief Read System PLL lock status
* @return true of the PLL is locked. false if not locked
*/
STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
{
return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
}
/**
* Clock sources for system and USB PLLs
*/
typedef enum CHIP_SYSCTL_PLLCLKSRC {
SYSCTL_PLLCLKSRC_IRC = 0, /*!< Internal oscillator in */
SYSCTL_PLLCLKSRC_SYSOSC, /*!< Crystal (main) oscillator in */
SYSCTL_PLLCLKSRC_RESERVED1, /*!< Reserved */
SYSCTL_PLLCLKSRC_RESERVED2, /*!< Reserved */
} CHIP_SYSCTL_PLLCLKSRC_T;
/**
* @brief Set System PLL clock source
* @param src : Clock source for system PLL
* @return Nothing
* @note This function will also toggle the clock source update register
* to update the clock source.
*/
void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
/**
* @brief Set USB PLL divider values
* @param msel : PLL feedback divider value. M = msel + 1.
* @param psel : PLL post divider value. P = (1<<psel).
* @return Nothing
* @note See the user manual for how to setup the PLL.
*/
STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
{
LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
}
/**
* @brief Read USB PLL lock status
* @return true of the PLL is locked. false if not locked
*/
STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
{
return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
}
/**
* @brief Set USB PLL clock source
* @param src : Clock source for USB PLL
* @return Nothing
* @note This function will also toggle the clock source update register
* to update the clock source.
*/
void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
/**
* @brief Bypass System Oscillator and set oscillator frequency range
* @param bypass : Flag to bypass oscillator
* @param highfr : Flag to set oscillator range from 15-25 MHz
* @return Nothing
* @note Sets the PLL input to bypass the oscillator. This would be
* used if an external clock that is not an oscillator is attached
* to the XTALIN pin.
*/
void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
/**
* Watchdog and low frequency oscillator frequencies plus or minus 40%
*/
typedef enum CHIP_WDTLFO_OSC {
WDTLFO_OSC_ILLEGAL,
WDTLFO_OSC_0_60, /*!< 0.6 MHz watchdog/LFO rate */
WDTLFO_OSC_1_05, /*!< 1.05 MHz watchdog/LFO rate */
WDTLFO_OSC_1_40, /*!< 1.4 MHz watchdog/LFO rate */
WDTLFO_OSC_1_75, /*!< 1.75 MHz watchdog/LFO rate */
WDTLFO_OSC_2_10, /*!< 2.1 MHz watchdog/LFO rate */
WDTLFO_OSC_2_40, /*!< 2.4 MHz watchdog/LFO rate */
WDTLFO_OSC_2_70, /*!< 2.7 MHz watchdog/LFO rate */
WDTLFO_OSC_3_00, /*!< 3.0 MHz watchdog/LFO rate */
WDTLFO_OSC_3_25, /*!< 3.25 MHz watchdog/LFO rate */
WDTLFO_OSC_3_50, /*!< 3.5 MHz watchdog/LFO rate */
WDTLFO_OSC_3_75, /*!< 3.75 MHz watchdog/LFO rate */
WDTLFO_OSC_4_00, /*!< 4.0 MHz watchdog/LFO rate */
WDTLFO_OSC_4_20, /*!< 4.2 MHz watchdog/LFO rate */
WDTLFO_OSC_4_40, /*!< 4.4 MHz watchdog/LFO rate */
WDTLFO_OSC_4_60 /*!< 4.6 MHz watchdog/LFO rate */
} CHIP_WDTLFO_OSC_T;
/**
* @brief Setup Watchdog oscillator rate and divider
* @param wdtclk : Selected watchdog clock rate
* @param div : Watchdog divider value, even value between 2 and 64
* @return Nothing
* @note Watchdog rate = selected rate divided by divider rate
*/
STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
{
LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
}
/**
* Clock sources for main system clock
*/
typedef enum CHIP_SYSCTL_MAINCLKSRC {
SYSCTL_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */
SYSCTL_MAINCLKSRC_PLLIN, /*!< System PLL input */
SYSCTL_MAINCLKSRC_WDTOSC, /*!< Watchdog oscillator rate */
SYSCTL_MAINCLKSRC_PLLOUT, /*!< System PLL output */
} CHIP_SYSCTL_MAINCLKSRC_T;
/**
* @brief Set main system clock source
* @param src : Clock source for main system
* @return Nothing
* @note This function will also toggle the clock source update register
* to update the clock source.
*/
void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
/**
* @brief Returns the main clock source
* @return Which clock is used for the core clock source?
*/
STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
{
return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
}
/**
* @brief Set system clock divider
* @param div : divider for system clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The system clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
{
LPC_SYSCTL->SYSAHBCLKDIV = div;
}
/**
* System and peripheral clocks
*/
typedef enum CHIP_SYSCTL_CLOCK {
SYSCTL_CLOCK_SYS = 0, /*!< 0: System clock */
SYSCTL_CLOCK_ROM, /*!<1: ROM clock */
SYSCTL_CLOCK_RAM, /*!< 2: RAM clock */
SYSCTL_CLOCK_FLASHREG, /*!< 3: FLASH register interface clock */
SYSCTL_CLOCK_FLASHARRAY, /*!< 4: FLASH array access clock */
SYSCTL_CLOCK_I2C, /*!< 5: I2C clock */
SYSCTL_CLOCK_GPIO, /*!< 6: GPIO clock */
SYSCTL_CLOCK_CT16B0, /*!< 7: 16-bit Counter/timer 0 clock */
SYSCTL_CLOCK_CT16B1, /*!< 8: 16-bit Counter/timer 1 clock */
SYSCTL_CLOCK_CT32B0, /*!< 9: 32-bit Counter/timer 0 clock */
SYSCTL_CLOCK_CT32B1, /*!< 10: 32-bit Counter/timer 1 clock */
SYSCTL_CLOCK_SSP0, /*!< 11: SSP0 clock */
SYSCTL_CLOCK_UART0, /*!< 12: UART0 clock */
SYSCTL_CLOCK_ADC, /*!< 13: ADC clock */
SYSCTL_CLOCK_USB, /*!< 14: USBREG clock */
SYSCTL_CLOCK_WDT, /*!< 15: Watchdog timer clock */
SYSCTL_CLOCK_IOCON, /*!< 16: IOCON block clock */
SYSCTL_CLOCK_RESERVED17, /*!< 17: Reserved */
SYSCTL_CLOCK_SSP1, /*!< 18: SSP1 clock */
#if defined(CHIP_LPC1347)
SYSCTL_CLOCK_PINT, /*!< 19: GPIO Pin interrupts register clock */
SYSCTL_CLOCK_RESERVED20, /*!< 20: Reserved */
SYSCTL_CLOCK_RESERVED21, /*!< 21: Reserved */
SYSCTL_CLOCK_RESERVED22, /*!< 22: Reserved */
SYSCTL_CLOCK_GROUP0INT, /*!< 23: GPIO GROUP0 interrupt register interface clock, LPC11E/Uxx only */
SYSCTL_CLOCK_GROUP1INT, /*!< 24: GPIO GROUP1 interrupt register interface clock, LPC11E/Uxx only */
SYSCTL_CLOCK_RESERVED25, /*!< 25: Reserved */
SYSCTL_CLOCK_RAM1, /*!< 26: SRAM block (0x20000000) clock, LPC11E/Uxx only */
SYSCTL_CLOCK_USBRAM, /*!< 27: USB SRAM block clock, LPC11Uxx only */
#endif
} CHIP_SYSCTL_CLOCK_T;
/**
* @brief Enable a system or peripheral clock
* @param clk : Clock to enable
* @return Nothing
*/
STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
{
LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
}
/**
* @brief Disable a system or peripheral clock
* @param clk : Clock to disable
* @return Nothing
*/
STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
{
LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
}
/**
* @brief Set SSP0 divider
* @param div : divider for SSP0 clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
{
LPC_SYSCTL->SSP0CLKDIV = div;
}
/**
* @brief Return SSP0 divider
* @return divider for SSP0 clock
* @note A value of 0 means the clock is disabled.
*/
STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
{
return LPC_SYSCTL->SSP0CLKDIV;
}
/**
* @brief Set UART divider clock
* @param div : divider for UART clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The UART clock
* rate is the main system clock divided by this value. <br>
* For the LPC1311/13/42/43, the UART pins must be configured in the
* IOCON block before the UART clock can be enabled
*/
STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
{
LPC_SYSCTL->USARTCLKDIV = div;
}
/**
* @brief Return UART divider
* @return divider for UART clock
* @note A value of 0 means the clock is disabled.
*/
STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
{
return LPC_SYSCTL->USARTCLKDIV;
}
/**
* @brief Set SSP1 divider clock
* @param div : divider for SSP1 clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
{
LPC_SYSCTL->SSP1CLKDIV = div;
}
/**
* @brief Return SSP1 divider
* @return divider for SSP1 clock
* @note A value of 0 means the clock is disabled.
*/
STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
{
return LPC_SYSCTL->SSP1CLKDIV;
}
/**
* @brief Set ARM trace clock divider
* @param div : divider for ARM trace clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The ARM trace clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetTraceClockDiv(uint32_t div)
{
LPC_SYSCTL->TRACECLKDIV = div;
}
/**
* @brief Return ARM trace clock divider
* @return divider for ARM trace clock
* @note A value of 0 means the clock is disabled.
*/
STATIC INLINE uint32_t Chip_Clock_GetTraceClockDiv(void)
{
return LPC_SYSCTL->TRACECLKDIV;
}
/**
* @brief Set SYSTICK clock divider
* @param div : divider for SYSTICK clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The SYSTICK clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetSystickClockDiv(uint32_t div)
{
LPC_SYSCTL->SYSTICKCLKDIV = div;
}
/**
* @brief Return SYSTICK clock divider
* @return divider for SYSTICK clock
* @note A value of 0 means the clock is disabled.
*/
STATIC INLINE uint32_t Chip_Clock_GetSystickClockDiv(void)
{
return LPC_SYSCTL->SYSTICKCLKDIV;
}
/**
* Clock sources for USB
*/
typedef enum CHIP_SYSCTL_USBCLKSRC {
SYSCTL_USBCLKSRC_PLLOUT = 0, /*!< USB PLL out */
SYSCTL_USBCLKSRC_MAINSYSCLK, /*!< Main system clock */
} CHIP_SYSCTL_USBCLKSRC_T;
/**
* @brief Set USB clock source and divider
* @param src : Clock source for USB
* @param div : divider for USB clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The USB clock
* rate is either the main system clock or USB PLL output clock divided
* by this value. This function will also toggle the clock source
* update register to update the clock source.
*/
void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
#if defined(CHIP_LPC1343)
/**
* Clock sources for WDT
*/
typedef enum CHIP_SYSCTL_WDTCLKSRC {
SYSCTL_WDTCLKSRC_IRC = 0, /*!< Internal oscillator for watchdog clock */
SYSCTL_WDTCLKSRC_MAINSYSCLK, /*!< Main system clock for watchdog clock */
SYSCTL_WDTCLKSRC_WDTOSC, /*!< Watchdog oscillator for watchdog clock */
} CHIP_SYSCTL_WDTCLKSRC_T;
/**
* @brief Set WDT clock source and divider
* @param src : Clock source for WDT
* @param div : divider for WDT clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The WDT clock
* rate is the clock source divided by the divider. This function will
* also toggle the clock source update register to update the clock
* source.
*/
void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div);
#endif
/**
* Clock sources for CLKOUT
*/
typedef enum CHIP_SYSCTL_CLKOUTSRC {
SYSCTL_CLKOUTSRC_IRC = 0, /*!< Internal oscillator for CLKOUT */
SYSCTL_CLKOUTSRC_SYSOSC, /*!< Main oscillator for CLKOUT */
SYSCTL_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */
SYSCTL_CLKOUTSRC_MAINSYSCLK, /*!< Main system clock for CLKOUT */
} CHIP_SYSCTL_CLKOUTSRC_T;
/**
* @brief Set CLKOUT clock source and divider
* @param src : Clock source for CLKOUT
* @param div : divider for CLKOUT clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
* rate is the clock source divided by the divider. This function will
* also toggle the clock source update register to update the clock
* source.
*/
void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
/**
* @brief Returns the main oscillator clock rate
* @return main oscillator clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
{
return OscRateIn;
}
/**
* @brief Returns the internal oscillator (IRC) clock rate
* @return internal oscillator (IRC) clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
{
return SYSCTL_IRC_FREQ;
}
/**
* @brief Return estimated watchdog oscillator rate
* @return Estimated watchdog oscillator rate
* @note This rate is accurate to plus or minus 40%.
*/
uint32_t Chip_Clock_GetWDTOSCRate(void);
/**
* @brief Return System PLL input clock rate
* @return System PLL input clock rate
*/
uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
/**
* @brief Return System PLL output clock rate
* @return System PLL output clock rate
*/
uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
/**
* @brief Return USB PLL input clock rate
* @return USB PLL input clock rate
*/
uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
/**
* @brief Return USB PLL output clock rate
* @return USB PLL output clock rate
*/
uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
/**
* @brief Return main clock rate
* @return main clock rate
*/
uint32_t Chip_Clock_GetMainClockRate(void);
/**
* @brief Return system clock rate
* @return system clock rate
*/
uint32_t Chip_Clock_GetSystemClockRate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CLOCK_13XX_H_ */

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/*
* @brief Basic CMSIS include file
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMSIS_H_
#define __CMSIS_H_
#include "lpc_types.h"
#include "sys_config.h"
/* Select correct CMSIS include file based on CHIP_* definition */
#if defined(CHIP_LPC1343)
#include "cmsis_1343.h"
typedef LPC1343_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC1347)
#include "cmsis_1347.h"
typedef LPC1347_IRQn_Type IRQn_Type;
#else
#error "No CHIP_* definition is defined"
#endif
/* Cortex-M3 processor and core peripherals */
#include "core_cm3.h"
#ifdef __cplusplus
}
#endif
#endif /* __CMSIS_H_ */

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/*
* @brief Basic CMSIS include file
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMSIS_1347_H_
#define __CMSIS_1347_H_
#include "lpc_types.h"
#include "sys_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CMSIS_1347 CHIP: LPC1347 CMSIS include file
* @ingroup CHIP_13XX_CMSIS_Drivers
* @{
*/
#if defined(__ARMCC_VERSION)
// Kill warning "#pragma push with no matching #pragma pop"
#pragma diag_suppress 2525
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
// #pragma push // FIXME not usable for IAR
#pragma language=extended
#else
#error Not supported compiler type
#endif
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
#if !defined(CHIP_LPC1347)
#error Incorrect or missing device variant (CHIP_LPC1347)
#endif
/** @defgroup CMSIS_1347_IRQ CHIP_1347: LPC1315/LPC1316/LPC1317/LPC1345/LPC1346/LPC1347 peripheral interrupt numbers
* @{
*/
typedef enum LPC1347_IRQn {
Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
/****** LPC1347 Specific Interrupt Numbers *******************************************************/
PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
GINT0_IRQn = 8, /*!< 8 GINT0 */
GINT1_IRQn = 9, /*!< 9 GINT1 */
Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
SSP1_IRQn = 14, /*!< 14 SSP1 */
I2C0_IRQn = 15, /*!< 15 I2C */
TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
SSP0_IRQn = 20, /*!< 20 SSP0 */
UART0_IRQn = 21, /*!< 21 USART */
USB0_IRQn = 22, /*!< 22 USB_IRQ */
USB0_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
ADC_IRQn = 24, /*!< 24 ADC */
WDT_IRQn = 25, /*!< 25 WDT */
BOD_IRQn = 26, /*!< 26 BOD */
FMC_IRQn = 27, /*!< 27 FMC */
Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
USB_WAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
} LPC1347_IRQn_Type;
/**
* @}
*/
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/** @defgroup CMSIS_1347_COMMON CHIP: Common LPC1347 Cortex CMSIS definitions
* @{
*/
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CMSIS_1347_H_ */

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/*
* @brief Error code returned by Boot ROM drivers/library functions
* @ingroup Common
*
* This file contains unified error codes to be used across driver,
* middleware, applications, hal and demo software.
*
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_ERROR_H__
#define __LPC_ERROR_H__
/** Error code returned by Boot ROM drivers/library functions
*
* Error codes are a 32-bit value with :
* - The 16 MSB contains the peripheral code number
* - The 16 LSB contains an error code number associated to that peripheral
*
*/
typedef enum {
/**\b 0x00000000*/ LPC_OK = 0, /**< enum value returned on Success */
/**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */
/**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2, /**< enum value returned on general timeout */
/**\b 0xFFFFFFFD*/ ERR_BUSY = -3, /**< enum value returned when resource is busy */
/* ISP related errors */
ERR_ISP_BASE = 0x00000000,
/*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,
/*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */
/*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */
/*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED,
/*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED,
/*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */
/*0x00000007*/ ERR_ISP_INVALID_SECTOR,
/*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,
/*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,
/*0x0000000A*/ ERR_ISP_COMPARE_ERROR,
/*0x0000000B*/ ERR_ISP_BUSY,/* Flash programming hardware interface is busy */
/*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */
/*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */
/*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,
/*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */
/*0x00000010*/ ERR_ISP_INVALID_CODE,/* Unlock code is invalid */
/*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,
/*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,
/*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED,
/* ROM API related errors */
ERR_API_BASE = 0x00010000,
/**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/
/**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */
/**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */
/**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */
/**\b 0x00010005*/ ERR_API_MOD_INIT,/**< API is called before module init */
/* SPIFI API related errors */
ERR_SPIFI_BASE = 0x00020000,
/*0x00020001*/ ERR_SPIFI_DEVICE_ERROR = ERR_SPIFI_BASE + 1,
/*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,
/*0x00020003*/ ERR_SPIFI_TIMEOUT,
/*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,
/*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,
/*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,
/*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,
/*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,
/*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,
/* Security API related errors */
ERR_SEC_BASE = 0x00030000,
/*0x00030001*/ ERR_SEC_AES_WRONG_CMD = ERR_SEC_BASE + 1,
/*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,
/*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,
/* USB device stack related errors */
ERR_USBD_BASE = 0x00040000,
/**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1,/**< invalid request */
/**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */
/**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */
/**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */
/**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */
/**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/
/**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC, /**< Bad config descriptor*/
/**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC, /**< Bad interface descriptor*/
/**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/
/**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF,/**< Bad alignment of buffer passed. */
/**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR,/**< Too many class handlers. */
/* CGU related errors */
ERR_CGU_BASE = 0x00050000,
/*0x00050001*/ ERR_CGU_NOT_IMPL = ERR_CGU_BASE + 1,
/*0x00050002*/ ERR_CGU_INVALID_PARAM,
/*0x00050003*/ ERR_CGU_INVALID_SLICE,
/*0x00050004*/ ERR_CGU_OUTPUT_GEN,
/*0x00050005*/ ERR_CGU_DIV_SRC,
/*0x00050006*/ ERR_CGU_DIV_VAL,
/*0x00050007*/ ERR_CGU_SRC,
/* I2C related errors */
ERR_I2C_BASE = 0x00060000,
/*0x00060001*/ ERR_I2C_NAK = ERR_I2C_BASE + 1,
/*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW,
/*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR,
/*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION,
/*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED,
/*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT,
/*0x00060007*/ ERR_I2C_GENERAL_FAILURE,
/*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT,
/*0x00060009*/ ERR_I2C_TIMEOUT,
/*0x0006000A*/ ERR_I2C_BUFFER_UNDERFLOW
} ErrorCode_t;
#ifndef offsetof
#define offsetof(s, m) (int) &(((s *) 0)->m)
#endif
#define COMPILE_TIME_ASSERT(pred) switch (0) { \
case 0: \
case pred:; }
#endif /* __LPC_ERROR_H__ */

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/*
* @brief LPC13xx Flash/EEPROM programming driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __FLASH_EEPROM_13XX_H_
#define __FLASH_EEPROM_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup FLASH_EEPROM_13XX CHIP: LPC13xx FLASH/EEPROM Programming driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
#if defined(CHIP_LPC1347)
#define ERASE_PAGE_SUPPORT
#define EEPROM_RW_SUPPORT
#endif
/** Flash Programming Entry Location */
#define FLASH_ENTRY_LOCATION (0x1fff1ff1)
/** The maximum number of flash programing parameters */
#define FLASH_PARAMETER_NUM (5)
/** The maximum number of flash programing results */
#define FLASH_RESULT_NUM (4)
/** Flash programming function type */
typedef void (*FLASH_ENTRY_T)(unsigned int[], unsigned int[]);
/**
* @brief Flash command code definitions
*/
typedef enum {
FLASH_PREPARE = 50, /*!< Prepare sector(s) for write operation */
FLASH_COPY_RAM_TO_FLASH = 51, /*!< Copy RAM to Flash */
FLASH_ERASE = 52, /*!< Erase sector(s) */
FLASH_BLANK_CHECK = 53, /*!< Blank check sector(s) */
FLASH_READ_PART_ID = 54, /*!< Read chip part ID */
FLASH_READ_BOOT_VER = 55, /*!< Read chip boot code version */
FLASH_COMPARE = 56, /*!< Compare memory areas */
FLASH_REINVOKE_ISP = 57, /*!< Reinvoke ISP */
FLASH_READ_UID = 58, /*!< Read UID */
#if defined(ERASE_PAGE_SUPPORT)
FLASH_ERASE_PAGE = 59, /*!< Erase page */
#endif
#if defined(EEPROM_RW_SUPPORT)
FLASH_EEPROM_WRITE = 61, /*!< EEPROM Write */
FLASH_EEPROM_READ = 62, /*!< EEPROM Read */
#endif
} FLASH_CMD_CODE_T;
/**
* @brief Flash status code definitions
*/
typedef enum {
CMD_SUCCESS, /*!< Command is executed successfully. */
INVALID_COMMAND, /*!< Invalid command. */
SRC_ADDR_ERROR, /*!< Source address is not on a word boundary. */
DST_ADDR_ERROR, /*!< Destination address is not on a correct boundary. */
SRC_ADDR_NOT_MAPPED, /*!< Source address is not mapped in the memory map. */
DST_ADDR_NOT_MAPPED, /*!< Destination address is not mapped in the memory map. */
COUNT_ERROR, /*!< Byte count is not multiple of 4 or is not a permitted value. */
INVALID_SECTOR, /*!< Sector number is invalid. */
SECTOR_NOT_BLANK, /*!< Sector is not blank. */
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, /*!< Command to prepare sector for write operation was not executed. */
COMPARE_ERROR, /*!< Source and destination data is not same. */
BUSY, /*!< Flash programming hardware interface is busy. */
} FLASH_STATUS_CODE_T;
#if defined(EEPROM_RW_SUPPORT)
/** EEPROM size */
#define EEPROM_SIZE (4 << 10)
#endif
/**
* @brief Command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t pParams[FLASH_PARAMETER_NUM]; /*!< Parameters*/
} FLASH_COMMAND_T;
/**
* @brief Command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
uint32_t pResult[FLASH_RESULT_NUM]; /*!< Results*/
} FLASH_OUTPUT_T;
/* Flash Programming Command Description
Command Parameters Return Code Result
----------------------------------------------------------------------------------------------------------
FLASH_PREPARE Start Sector Number CMD_SUCCESS None
End Sector Number BUSY
INVALID_SECTOR
FLASH_COPY_RAM2FLASH Destination Flash Addr CMD_SUCCESS None
Source RAM Addr SRC_ADDR_ERROR
Number of bytes written SRC_ADDR_NOT_MAPPED
CCLK in kHz DST_ADDR_NOT_MAPPED
COUNT_ERROR
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
BUSY
FLASH_ERASE Start Sector Number CMD_SUCCESS None
Emd Sector Number BUSY
CCLK in kHz SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
INVALID_SECTOR
FLASH_BLANK_CHECK Start Sector Number CMD_SUCCESS Non Blank Sector Offset(if Status code is SECTOR_NOT_BLANK)
End Sector Number BUSY Content of non blank word location
SECTOR_NOT_BLANK
INVALID_SECTOR
FLASH_READ_PART_ID None CMD_SUCCESS Part ID
FLASH_READ_BOOT_VER None CMD_SUCCESS <byte1(Major)>.<byte0(Minor)>
FLASH_COMPARE Destination Addr CMD_SUCCESS Offset of the first mismatch
Source Address COMPARE_ERROR
Number of bytes compared COUNT_ERROR
ADDR_ERROR
ADDR_NOT_MAPPED
FLASH_REINVOKE_ISP None None None
FLASH_READ_UID None CMD_SUCCESS The first 32-bit word
The second 32-bit word.
The third 32-bit word.
The fourth 32-bit word
FLASH_ERASE_PAGE Start Page Number CMD_SUCCESS None
End Page Number BUSY
CCLK in kHz SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
INVALID_SECTOR
FLASH_EEPROM_WRITE EEPROM Addr CMD_SUCCESS None
RAM Addr SRC_ADDR_NOT_MAPPED
Number of bytes written DST_ADDR_NOT_MAPPED
CCLK in kHz
FLASH_EEPROM_READ EEPROM Addr CMD_SUCCESS None
RAM Addr SRC_ADDR_NOT_MAPPED
Number of bytes read DST_ADDR_NOT_MAPPED
CCLK in kHz
*/
/**
* @brief [Prepare sectors] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t start; /*!< Start Sector Number */
uint32_t end; /*!<End Sector Number (should be greater than or equal to start sector number).*/
} FLASH_PREPARE_SECTORS_COMMAND_T;
/**
* @brief [Prepare sectors] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
} FLASH_PREPARE_SECTORS_OUTPUT_T;
/**
* @brief [Copy Ram to Flash] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t dst; /*!< Destination flash address where data bytes are to be written (256 byte boundary) */
uint32_t src; /*!<Source RAM address from which data bytes are to be read (a word boudary).*/
uint32_t byteNum; /*!<Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.*/
uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
} FLASH_COPY_RAM_TO_FLASH_COMMAND_T;
/**
* @brief [Copy Ram to Flash] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
} FLASH_COPY_RAM_TO_FLASH_OUTPUT_T;
/**
* @brief [Erase Sector(s)] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t start; /*!< Start Sector Number */
uint32_t end; /*!<End Sector Number (should be greater than or equal to start sector number).*/
uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
} FLASH_ERASE_SECTORS_COMMAND_T;
/**
* @brief [Erase Sector(s)] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
} FLASH_ERASE_SECTORS_OUTPUT_T;
/**
* @brief [Blank check sector(s)] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t start; /*!< Start Sector Number */
uint32_t end; /*!<End Sector Number (should be greater than or equal to start sector number).*/
} FLASH_BLANK_CHECK_SECTORS_COMMAND_T;
/**
* @brief [Blank check sector(s)] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
uint32_t firstNonBlankLoc; /*!< Offset of the first non blank word location if the Status Code is SECTOR_NOT_BLANK.*/
uint32_t firstNonBlankVal; /*!<Contents of non blank word location.*/
} FLASH_BLANK_CHECK_SECTORS_OUTPUT_T;
/**
* @brief [Read Part Identification number] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
} FLASH_READ_PART_ID_COMMAND_T;
/**
* @brief [Read Part Identification number] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
uint32_t partID; /*!< Part Identification Number*/
} FLASH_READ_PART_ID_OUTPUT_T;
/**
* @brief [Read Boot code version number] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
} FLASH_READ_BOOTCODE_VER_COMMAND_T;
/**
* @brief [Read Boot code version number] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
uint8_t minor; /*!< Minor*/
uint8_t major; /*!< Major*/
} FLASH_READ_BOOTCODE_VER_OUTPUT_T;
/**
* @brief [Compare memory] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t dst; /*!<Starting flash or RAM address of data bytes to be compared (a word boundary) */
uint32_t src; /*!<Starting flash or RAM address of data bytes to be compared (a word boudary).*/
uint32_t byteNum; /*!<Number of bytes to be compared; should be a multiple of 4.*/
} FLASH_COMPARE_MEM_COMMAND_T;
/**
* @brief [Compare memory] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
uint32_t offset; /*!< Offset of the first mismatch if the Status Code is COMPARE_ERROR.*/
} FLASH_COMPARE_MEM_OUTPUT_T;
/**
* @brief [Reinvoke ISP] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
} FLASH_REINVOKE_ISP_COMMAND_T;
/**
* @brief [Reinvoke ISP] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
} FLASH_REINVOKE_ISP_OUTPUT_T;
/**
* @brief [ReadUID] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
} FLASH_READ_UID_COMMAND_T;
/**
* @brief [ReadUID] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
uint32_t id[4]; /*!< UID*/
} FLASH_READ_UID_OUTPUT_T;
#if defined(ERASE_PAGE_SUPPORT)
/**
* @brief [Erase page(s)] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t start; /*!< Start Page Number */
uint32_t end; /*!<End Page Number (should be greater than or equal to start page number).*/
uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
} FLASH_ERASE_PAGES_COMMAND_T;
/**
* @brief [Erase page(s)] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
} FLASH_ERASE_PAGES_OUTPUT_T;
#endif /* defined(ERASE_PAGE_SUPPORT) */
#if defined(EEPROM_RW_SUPPORT)
/**
* @brief [Write EEPROM] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t eepromAddr; /*!< EEPROM address.*/
uint32_t ramAddr; /*!< RAM address.*/
uint32_t byteNum; /*!<Number of bytes to be written.*/
uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
} EEPROM_WRITE_COMMAND_T;
/**
* @brief [Write EEPROM] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
} EEPROM_WRITE_OUTPUT_T;
/**
* @brief [Read EEPROM] command parameter table structure
*/
typedef struct {
uint32_t cmd; /*!< Command code */
uint32_t eepromAddr; /*!< EEPROM address.*/
uint32_t ramAddr; /*!< RAM address.*/
uint32_t byteNum; /*!<Number of bytes to be written.*/
uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
} EEPROM_READ_COMMAND_T;
/**
* @brief [Read EEPROM] command result table structure
*/
typedef struct {
uint32_t status; /*!< Status code */
} EEPROM_READ_OUTPUT_T;
#endif /* defined(EEPROM_RW_SUPPORT) */
/**
* @brief Get sector number of the specified address
* @param adr : flash address.
* @return sector number
*/
STATIC INLINE uint32_t Chip_FLASH_GetSecNum(uint32_t adr)
{
return adr >> 12;
}
/**
* @brief Execute flash programming command
* @param pCommand : Command information
* @param pOutput : Output information
* @return Nothing
*/
STATIC INLINE void Chip_FLASH_Execute(FLASH_COMMAND_T *pCommand, FLASH_OUTPUT_T *pOutput)
{
((FLASH_ENTRY_T) FLASH_ENTRY_LOCATION)((unsigned int *) pCommand, (unsigned int *) pOutput);
}
/**
* @brief Prepare sector(s) for write operation
* @param pCommand : Command information
* @param pOutput : Output information
* @return Nothing
* @note This command must be executed before executing "Copy RAM to flash" or "Erase Sector(s)" command. <br>
* The boot sector can not be prepared by this command.
*/
STATIC INLINE void Chip_FLASH_PrepareSectors(FLASH_PREPARE_SECTORS_COMMAND_T *pCommand,
FLASH_PREPARE_SECTORS_OUTPUT_T *pOutput)
{
Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
}
/**
* @brief Copy RAM to flash
* @param pCommand : Command information
* @param pOutput : Output information
* @return Nothing
* @note The affected sectors should be prepared first by calling "Prepare Sector for Write Operation" command.<br>
* The boot sector can not be written by this command.
*/
STATIC INLINE void Chip_FLASH_CopyRamToFlash(FLASH_COPY_RAM_TO_FLASH_COMMAND_T *pCommand,
FLASH_COPY_RAM_TO_FLASH_OUTPUT_T *pOutput)
{
Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
}
/**
* @brief Erase Sector(s)
* @param pCommand : Command information
* @param pOutput : Output information
* @return Nothing
* @note The boot sector can not be erased by this command.
*/
STATIC INLINE void Chip_FLASH_EraseSectors(FLASH_ERASE_SECTORS_COMMAND_T *pCommand,
FLASH_ERASE_SECTORS_OUTPUT_T *pOutput)
{
Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
}
/**
* @brief Blank check sector(s)
* @param pCommand : Command information
* @param pOutput : Output information
* @return Nothing
*/
STATIC INLINE void Chip_FLASH_BlankCheckSectors(FLASH_BLANK_CHECK_SECTORS_COMMAND_T *pCommand,
FLASH_BLANK_CHECK_SECTORS_OUTPUT_T *pOutput)
{
Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
}
/**
* @brief Read Part Identification number
* @param pOutput : Output information
* @return Nothing
*/
void Chip_FLASH_ReadPartID(FLASH_READ_PART_ID_OUTPUT_T *pOutput);
/**
* @brief Read Boot code version number
* @param pOutput : Output information
* @return Nothing
*/
void Chip_FLASH_ReadBootCodeVersion(FLASH_READ_BOOTCODE_VER_OUTPUT_T *pOutput);
/**
* @brief Compare memory
* @param pCommand : parameters
* @param pOutput : results
* @return Nothing
* @note The result may not be correct when the source or destination includes any
* of the first 512 bytes starting from address zero. The first 512 bytes can be re-mapped to RAM.
*/
STATIC INLINE void Chip_FLASH_CompareMem(FLASH_COMPARE_MEM_COMMAND_T *pCommand,
FLASH_COMPARE_MEM_OUTPUT_T *pOutput)
{
Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
}
/**
* @brief Reinvoke ISP
* @return Nothing
*/
void Chip_FLASH_ReInvokeISP(void);
/**
* @brief Read UID
* @param pOutput : Output information
* @return Nothing
*/
void Chip_FLASH_ReadUID(FLASH_READ_UID_OUTPUT_T *pOutput);
#if defined(ERASE_PAGE_SUPPORT)
/**
* @brief Erase Page(s)
* @param pCommand : Command information
* @param pOutput : Output information
* @return Nothing
*/
STATIC INLINE void Chip_FLASH_ErasePages(FLASH_ERASE_PAGES_COMMAND_T *pCommand,
FLASH_ERASE_PAGES_OUTPUT_T *pOutput)
{
Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
}
#endif /* defined(ERASE_PAGE_SUPPORT) */
#if defined(EEPROM_RW_SUPPORT)
/**
* @brief Write EEPROM
* @param pCommand : Command information
* @param pOutput : Output information
* @return Nothing
* @note The top 64 bytes of the EEPROM memory are reserved and cannot be written to.
*/
STATIC INLINE void Chip_EEPROM_Write(EEPROM_WRITE_COMMAND_T *pCommand,
EEPROM_WRITE_OUTPUT_T *pOutput)
{
Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
}
/**
* @brief Read EEPROM
* @param pCommand : Command information
* @param pOutput : Output information
* @return Nothing
*/
STATIC INLINE void Chip_EEPROM_Read(EEPROM_READ_COMMAND_T *pCommand,
EEPROM_READ_OUTPUT_T *pOutput)
{
Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
}
#endif /*defined(EEPROM_RW_SUPPORT)*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __FLASH_EEPROM_13XX_H_ */

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/*
* @brief LPC13xx FLASH Memory Controller (FMC) registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __FMC_13XX_H_
#define __FMC_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup FMC_13XX CHIP: LPC13xx FLASH Memory Controller driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief FLASH Memory Controller Unit register block structure
*/
typedef struct {/*!< FMC Structure */
__I uint32_t RESERVED1[4];
__IO uint32_t FLASHCFG;
__I uint32_t RESERVED2[3];
__IO uint32_t FMSSTART;
__IO uint32_t FMSSTOP;
__I uint32_t RESERVED3;
__I uint32_t FMSW[4];
__I uint32_t RESERVED4[28];
__I uint32_t RESERVED5[974];
__I uint32_t FMSTAT;
__I uint32_t RESERVED6;
__O uint32_t FMSTATCLR;
} LPC_FMC_T;
/**
* @brief FLASH Access time definitions
*/
typedef enum {
FLASHTIM_20MHZ_CPU = 0, /*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock*/
FLASHTIM_40MHZ_CPU = 1, /*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock*/
FLASHTIM_72MHZ_CPU = 2, /*!< Flash accesses use 3 CPU clocks. Use for up to 72 MHz CPU clock*/
} FMC_FLASHTIM_T;
/**
* @brief Set FLASH access time in clocks
* @param clks : Clock cycles for FLASH access (minus 1)
* @return Nothing
*/
STATIC INLINE void Chip_FMC_SetFLASHAccess(FMC_FLASHTIM_T clks)
{
uint32_t tmp = LPC_FMC->FLASHCFG & (~(0x3));
/* Don't alter upper bits */
LPC_FMC->FLASHCFG = tmp | clks;
}
/**
* @brief Start computation of a signature for a FLASH memory range
* @param start : Starting FLASH address for computation
* @param stop : Ending FLASH address for computation
* @return Nothing
* @note Only bits 20..4 are used for the FLASH signature computation.
* Use the Chip_FMC_IsSignatureBusy() function to determine when the
* signature computation operation is complete and use the
* Chip_FMC_GetSignature() function to get the computed signature.
*/
STATIC INLINE void Chip_FMC_ComputeSignature(uint32_t start, uint32_t stop)
{
LPC_FMC->FMSSTART = (start >> 4);
LPC_FMC->FMSTATCLR = (1 << 2);
LPC_FMC->FMSSTOP = (stop >> 4) | (1 << 17);
}
/**
* @brief Clear signature generation completion flag
* @return Nothing
*/
STATIC INLINE void Chip_FMC_ClearSignatureBusy(void)
{
LPC_FMC->FMSTATCLR = (1 << 2);
}
/**
* @brief Check for signature generation completion
* @return true if the signature computation is running, false if finished
*/
STATIC INLINE bool Chip_FMC_IsSignatureBusy(void)
{
return (bool) ((LPC_FMC->FMSTAT & (1 << 2)) != 0);
}
/**
* @brief Returns the generated FLASH signature value
* @param index : Signature index to get - use 0 to FMSW0, 1 to FMSW1, etc.
* @return the generated FLASH signature value
*/
STATIC INLINE uint32_t Chip_FMC_GetSignature(int index)
{
return LPC_FMC->FMSW[index];
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __FMC_13XX_H_ */

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/*
* @brief LPC13xx GPIO chip driver for LPC13(15/16/17/45/46/47) families
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPIO_13XX_1_H_
#define __GPIO_13XX_1_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPIO_13XX_1 CHIP: LPC13xx GPIO chip driver for LPC13(15/16/17/45/46/47) families
* @ingroup CHIP_13XX_Drivers
* For device familes identified with CHIP definitions CHIP_LPC1315, CHIP_LPC1316, CHIP_LPC1317,
* CHIP_LPC1345, CHIP_LPC1346 and CHIP_LPC1347 only.
* @{
*/
#if defined(CHIP_LPC1347)
/**
* @brief GPIO port register block structure
*/
typedef struct { /*!< GPIO_PORT Structure */
__IO uint8_t B[128][32]; /*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
__IO uint32_t W[32][32]; /*!< Offset 0x1000: Word pin registers port 0 to n */
__IO uint32_t DIR[32]; /*!< Offset 0x2000: Direction registers port n */
__IO uint32_t MASK[32]; /*!< Offset 0x2080: Mask register port n */
__IO uint32_t PIN[32]; /*!< Offset 0x2100: Portpin register port n */
__IO uint32_t MPIN[32]; /*!< Offset 0x2180: Masked port register port n */
__IO uint32_t SET[32]; /*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */
__O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */
__O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */
} LPC_GPIO_T;
/**
* @brief Initialize GPIO block
* @param pGPIO : The base of GPIO peripheral on the chip
* @return Nothing
*/
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO);
/**
* @brief De-Initialize GPIO block
* @param pGPIO : The base of GPIO peripheral on the chip
* @return Nothing
*/
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO);
/**
* @brief Set a GPIO port/bit state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to set
* @param pin : GPIO pin to set
* @param setting : true for high, false for low
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting)
{
pGPIO->B[port][pin] = setting;
}
/**
* @brief Set a GPIO pin state via the GPIO byte register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to set
* @param setting : true for high, false for low
* @return Nothing
* @note This function replaces Chip_GPIO_WritePortBit()
*/
STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting)
{
pGPIO->B[port][pin] = setting;
}
/**
* @brief Read a GPIO state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to read
* @param pin : GPIO pin to read
* @return true of the GPIO is high, false if low
* @note It is recommended to use the Chip_GPIO_GetPinState() function instead.
*/
STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin)
{
return (bool) pGPIO->B[port][pin];
}
/**
* @brief Get a GPIO pin state via the GPIO byte register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to get state for
* @return true if the GPIO is high, false if low
* @note This function replaces Chip_GPIO_ReadPortBit()
*/
STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
return (bool) pGPIO->B[port][pin];
}
/**
* @brief Set a GPIO direction
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to set
* @param bit : GPIO bit to set
* @param setting : true for output, false for input
* @return Nothing
* @note It is recommended to use the Chip_GPIO_SetPinDIROutput(),
* Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead
* of this function.
*/
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting);
/**
* @brief Set GPIO direction for a single GPIO pin to an output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to set direction on as output
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->DIR[port] |= 1UL << pin;
}
/**
* @brief Set GPIO direction for a single GPIO pin to an input
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to set direction on as input
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->DIR[port] &= ~(1UL << pin);
}
/**
* @brief Set GPIO direction for a single GPIO pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to set direction for
* @param output : true for output, false for input
* @return Nothing
*/
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output);
/**
* @brief Read a GPIO direction (out or in)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to read
* @param bit : GPIO bit to read
* @return true of the GPIO is an output, false if input
* @note It is recommended to use the Chip_GPIO_GetPinDIR() function instead.
*/
STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
{
return (bool) (((pGPIO->DIR[port]) >> bit) & 1);
}
/**
* @brief Get GPIO direction for a single GPIO pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to get direction for
* @return true if the GPIO is an output, false if input
*/
STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
return (bool) (((pGPIO->DIR[port]) >> pin) & 1);
}
/**
* @brief Set Direction for a GPIO port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port Number
* @param bitValue : GPIO bit to set
* @param out : Direction value, 0 = input, !0 = output
* @return None
* @note Bits set to '0' are not altered. It is recommended to use the
* Chip_GPIO_SetPortDIR() function instead.
*/
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out);
/**
* @brief Set GPIO direction for a all selected GPIO pins to an output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pinMask : GPIO pin mask to set direction on as output (bits 0..b for pins 0..n)
* @return Nothing
* @note Sets multiple GPIO pins to the output direction, each bit's position that is
* high sets the corresponding pin number for that bit to an output.
*/
STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask)
{
pGPIO->DIR[port] |= pinMask;
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an input
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pinMask : GPIO pin mask to set direction on as input (bits 0..b for pins 0..n)
* @return Nothing
* @note Sets multiple GPIO pins to the input direction, each bit's position that is
* high sets the corresponding pin number for that bit to an input.
*/
STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask)
{
pGPIO->DIR[port] &= ~pinMask;
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an input or output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pinMask : GPIO pin mask to set direction on (bits 0..b for pins 0..n)
* @param outSet : Direction value, false = set as inputs, true = set as outputs
* @return Nothing
* @note Sets multiple GPIO pins to the input direction, each bit's position that is
* high sets the corresponding pin number for that bit to an input.
*/
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask, bool outSet);
/**
* @brief Get GPIO direction for a all GPIO pins
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @return a bitfield containing the input and output states for each pin
* @note For pins 0..n, a high state in a bit corresponds to an output state for the
* same pin, while a low state corresponds to an input state.
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO->DIR[port];
}
/**
* @brief Set GPIO port mask value for GPIO masked read and write
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param mask : Mask value for read and write
* @return Nothing
* @note Controls which bits corresponding to PIO0_n are active in the P0MPORT
* register (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17).
*/
STATIC INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint32_t port, uint32_t mask)
{
pGPIO->MASK[port] = mask;
}
/**
* @brief Get GPIO port mask value used for GPIO masked read and write
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @return Returns value set with the Chip_GPIO_SetPortMask() function.
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO->MASK[port];
}
/**
* @brief Set all GPIO raw pin states (regardless of masking)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param value : Value to set all GPIO pin states (0..n) to
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
{
pGPIO->PIN[port] = value;
}
/**
* @brief Get all GPIO raw pin states (regardless of masking)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @return Current (raw) state of all GPIO pins
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO->PIN[port];
}
/**
* @brief Set all GPIO pin states, but mask via the MASKP0 register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param value : Value to set all GPIO pin states (0..n) to
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
{
pGPIO->MPIN[port] = value;
}
/**
* @brief Get all GPIO pin statesm but mask via the MASKP0 register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @return Current (masked) state of all GPIO pins
*/
STATIC INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO->MPIN[port];
}
/**
* @brief Set a GPIO port/bit to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number
* @param bitValue : bit(s) in the port to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output. It is recommended to use the
* Chip_GPIO_SetPortOutHigh() function instead.
*/
STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
{
pGPIO->SET[portNum] = bitValue;
}
/**
* @brief Set selected GPIO output pins to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pins : pins (0..n) to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO->SET[port] = pins;
}
/**
* @brief Set an individual GPIO output pin to the high state
* @param pGPIO : The base of GPIO peripheral on the chip'
* @param port : GPIO Port number where @a pin is located
* @param pin : pin number (0..n) to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->SET[port] = (1 << pin);
}
/**
* @brief Set a GPIO port/bit to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number
* @param bitValue : bit(s) in the port to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
{
pGPIO->CLR[portNum] = bitValue;
}
/**
* @brief Set selected GPIO output pins to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pins : pins (0..n) to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO->CLR[port] = pins;
}
/**
* @brief Set an individual GPIO output pin to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : pin number (0..n) to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->CLR[port] = (1 << pin);
}
/**
* @brief Toggle selected GPIO output pins to the opposite state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pins : pins (0..n) to toggle
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO->NOT[port] = pins;
}
/**
* @brief Toggle an individual GPIO output pin to the opposite state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : pin number (0..n) to toggle
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->NOT[port] = (1 << pin);
}
/**
* @brief Read current bit states for the selected port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number to read
* @return Current value of GPIO port
* @note The current states of the bits for the port are read, regardless of
* whether the GPIO port bits are input or output.
*/
STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)
{
return pGPIO->PIN[portNum];
}
#endif /* defined(CHIP_LPC1347) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GPIO_13XX_1_H_ */

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/*
* @brief LPC13xx GPIO chip driver for LPC13(11/13/42/43) families
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPIO_13XX_2_H_
#define __GPIO_13XX_2_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPIO_13XX_2 CHIP: LPC13xx GPIO chip driver for LPC13(11/13/42/43) families
* @ingroup CHIP_13XX_Drivers
* For device familes identified with CHIP definitions CHIP_LPC1311, CHIP_LPC1313
* CHIP_LPC1342 and CHIP_LPC1343 only.
* @{
*/
#if defined(CHIP_LPC1343)
/**
* @brief GPIO port register block structure
*/
typedef struct { /*!< GPIO_PORT Structure */
__IO uint32_t DATA[4096]; /*!< Offset: 0x0000 to 0x3FFC Data address masking register (R/W) */
uint32_t RESERVED1[4096];
__IO uint32_t DIR; /*!< Offset: 0x8000 Data direction register (R/W) */
__IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense register (R/W) */
__IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges register (R/W) */
__IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event register (R/W) */
__IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask register (R/W) */
__I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status register (R/ ) */
__I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status register (R/ ) */
__O uint32_t IC; /*!< Offset: 0x801C Interrupt clear register (W) */
uint32_t RESERVED2[8184]; /* Padding added for aligning contiguous GPIO blocks */
} LPC_GPIO_T;
/**
* @brief Initialize GPIO block
* @param pGPIO : The base of GPIO peripheral on the chip
* @return Nothing
*/
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO);
/**
* @brief De-Initialize GPIO block
* @param pGPIO : The base of GPIO peripheral on the chip
* @return Nothing
*/
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO);
/**
* @brief Set a GPIO port/bit state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to set
* @param bit : GPIO bit to set
* @param setting : true for high, false for low
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
{
pGPIO[port].DATA[1 << bit] = setting << bit;
}
/**
* @brief Set a GPIO pin state via the GPIO byte register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : GPIO pin to set
* @param setting : true for high, false for low
* @return Nothing
* @note This function replaces Chip_GPIO_WritePortBit()
*/
STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting)
{
pGPIO[port].DATA[1 << pin] = setting << pin;
}
/**
* @brief Read a GPIO state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to read
* @param bit : GPIO bit to read
* @return true of the GPIO is high, false if low
* @note It is recommended to use the Chip_GPIO_GetPinState() function instead.
*/
STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
{
return (bool) ((pGPIO[port].DATA[1 << bit] >> bit) & 1);
}
/**
* @brief Get a GPIO pin state via the GPIO byte register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : GPIO pin to get state for
* @return true if the GPIO is high, false if low
* @note This function replaces Chip_GPIO_ReadPortBit()
*/
STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
return (pGPIO[port].DATA[1 << pin]) != 0;
}
/**
* @brief Seta GPIO direction
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to set
* @param bit : GPIO bit to set
* @param setting : true for output, false for input
* @return Nothing
* @note It is recommended to use the Chip_GPIO_SetPinDIROutput(),
* Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead
* of this function.
*/
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting);
/**
* @brief Set GPIO direction for a single GPIO pin to an output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : GPIO pin to set direction on as output
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].DIR |= (1UL << pin);
}
/**
* @brief Set GPIO direction for a single GPIO pin to an input
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : GPIO pin to set direction on as input
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].DIR &= ~(1UL << pin);
}
/**
* @brief Set GPIO direction for a single GPIO pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : GPIO pin to set direction for
* @param output : true for output, false for input
* @return Nothing
*/
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output);
/**
* @brief Read a GPIO direction (out or in)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to read
* @param bit : GPIO bit to read
* @return true of the GPIO is an output, false if input
* @note It is recommended to use the Chip_GPIO_GetPinDIR() function instead.
*/
STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
{
return (bool) (((pGPIO[port].DIR) >> bit) & 1);
}
/**
* @brief Get GPIO direction for a single GPIO pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : GPIO pin to get direction for
* @return true if the GPIO is an output, false if input
*/
STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
return (bool) (pGPIO[port].DIR >> pin) & 1;
}
/**
* @brief Set Direction for a GPIO port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port Number
* @param bit : GPIO bit to set
* @param out : Direction value, 0 = input, !0 = output
* @return None
* @note Bits set to '0' are not altered. It is recommended to use the
* Chip_GPIO_SetPortDIR() function instead.
*/
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit, uint8_t out);
/**
* @brief Set GPIO direction for a all selected GPIO pins to an output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinMask : GPIO pin mask to set direction on as output (bits 0..n for pins 0..n)
* @return Nothing
* @note Sets multiple GPIO pins to the output direction, each bit's position that is
* high sets the corresponding pin number for that bit to an output.
*/
STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
{
pGPIO[port].DIR |= pinMask;
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an input
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinMask : GPIO pin mask to set direction on as input (bits 0..b for pins 0..n)
* @return Nothing
* @note Sets multiple GPIO pins to the input direction, each bit's position that is
* high sets the corresponding pin number for that bit to an input.
*/
STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
{
pGPIO[port].DIR &= ~pinMask;
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an input or output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinMask : GPIO pin mask to set direction on (bits 0..b for pins 0..n)
* @param outSet : Direction value, false = set as inputs, true = set as outputs
* @return Nothing
* @note Sets multiple GPIO pins to the input direction, each bit's position that is
* high sets the corresponding pin number for that bit to an input.
*/
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet);
/**
* @brief Get GPIO direction for a all GPIO pins
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @return a bitfield containing the input and output states for each pin
* @note For pins 0..n, a high state in a bit corresponds to an output state for the
* same pin, while a low state corresponds to an input state.
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].DIR;
}
/**
* @brief Set all GPIO raw pin states (regardless of masking)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param value : Value to set all GPIO pin states (0..n) to
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
{
pGPIO[port].DATA[0xFFF] = value;
}
/**
* @brief Get all GPIO raw pin states (regardless of masking)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @return Current (raw) state of all GPIO pins
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].DATA[0xFFF];
}
/**
* @brief Set a GPIO port/bit to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param bit : Bit(s) in the port to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output. It is recommended to use the
* Chip_GPIO_SetPortOutHigh() function instead.
*/
STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit)
{
pGPIO[port].DATA[bit] = bit;
}
/**
* @brief Set selected GPIO output pins to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pins : pins (0..n) to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO[port].DATA[pins] = 0xFFF;
}
/**
* @brief Set an individual GPIO output pin to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : pin number (0..n) to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].DATA[1 << pin] = (1 << pin);
}
/**
* @brief Set a GPIO port/bit to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param bit : Bit(s) in the port to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit)
{
pGPIO[port].DATA[bit] = ~bit;
}
/**
* @brief Set selected GPIO output pins to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pins : pins (0..n) to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO[port].DATA[pins] = 0;
}
/**
* @brief Set an individual GPIO output pin to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : pin number (0..n) to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].DATA[1 << pin] = 0;
}
/**
* @brief Toggle selected GPIO output pins to the opposite state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pins : pins (0..n) to toggle
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO[port].DATA[pins] ^= 0xFFF;
}
/**
* @brief Toggle an individual GPIO output pin to the opposite state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : pin number (0..n) to toggle
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO[port].DATA[1 << pin] ^= (1 << pin);
}
/**
* @brief Read current bit states for the selected port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number to read
* @return Current value of GPIO port
* @note The current states of the bits for the port are read, regardless of
* whether the GPIO port bits are input or output.
*/
STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].DATA[4095];
}
/**
* @brief Configure the pins as edge sensitive for interrupts
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to set to edge mode (ORed value of bits 0..11)
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinModeEdge(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IS &= ~pinmask;
}
/**
* @brief Configure the pins as level sensitive for interrupts
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to set to level mode (ORed value of bits 0..11)
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinModeLevel(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IS |= pinmask;
}
/**
* @brief Returns current GPIO edge or high level interrupt configuration for all pins for a port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @return A bifield containing the edge/level interrupt configuration for each
* pin for the selected port. Bit 0 = pin 0, 1 = pin 1.
* For each bit, a 0 means the edge interrupt is configured, while a 1 means a level
* interrupt is configured. Mask with this return value to determine the
* edge/level configuration for each pin in a port.
*/
STATIC INLINE uint32_t Chip_GPIO_IsLevelEnabled(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].IS;
}
/**
* @brief Sets GPIO interrupt configuration for both edges for selected pins
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to set to dual edge mode (ORed value of bits 0..11)
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetEdgeModeBoth(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IBE |= pinmask;
}
/**
* @brief Sets GPIO interrupt configuration for a single edge for selected pins
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to set to single edge mode (ORed value of bits 0..11)
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetEdgeModeSingle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IBE &= ~pinmask;
}
/**
* @brief Returns current GPIO interrupt dual or single edge configuration for all pins for a port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @return A bifield containing the single/dual interrupt configuration for each
* pin for the selected port. Bit 0 = pin 0, 1 = pin 1.
* For each bit, a 0 means the interrupt triggers on a single edge (use the
* Chip_GPIO_SetEdgeModeHigh() and Chip_GPIO_SetEdgeModeLow() functions to configure
* selected edge), while a 1 means the interrupt triggers on both edges. Mask
* with this return value to determine the edge/level configuration for each pin in
* a port.
*/
STATIC INLINE uint32_t Chip_GPIO_GetEdgeModeDir(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].IBE;
}
/**
* @brief Sets GPIO interrupt configuration when in single edge or level mode to high edge trigger or high level
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to set to high mode (ORed value of bits 0..11)
* @return Nothing
* @note Use this function to select high level or high edge interrupt mode
* for the selected pins on the selected port when not in dual edge mode.
*/
STATIC INLINE void Chip_GPIO_SetModeHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IEV |= pinmask;
}
/**
* @brief Sets GPIO interrupt configuration when in single edge or level mode to low edge trigger or low level
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to set to low mode (ORed value of bits 0..11)
* @return Nothing
* @note Use this function to select low level or low edge interrupt mode
* for the selected pins on the selected port when not in dual edge mode.
*/
STATIC INLINE void Chip_GPIO_SetModeLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IEV &= ~pinmask;
}
/**
* @brief Returns current GPIO interrupt edge direction or level mode
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @return A bifield containing the low or high direction of the interrupt
* configuration for each pin for the selected port. Bit 0 = pin 0, 1 = pin 1.
* For each bit, a 0 means the interrupt triggers on a low level or edge, while a
* 1 means the interrupt triggers on a high level or edge. Mask with this
* return value to determine the high/low configuration for each pin in a port.
*/
STATIC INLINE uint32_t Chip_GPIO_GetModeHighLow(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].IEV;
}
/**
* @brief Enables interrupts for selected pins on a port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to enable interrupts for (ORed value of bits 0..11)
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_EnableInt(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IE |= pinmask;
}
/**
* @brief Disables interrupts for selected pins on a port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to disable interrupts for (ORed value of bits 0..11)
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_DisableInt(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IE &= ~pinmask;
}
/**
* @brief Returns current enable pin interrupts for a port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @return A bifield containing the enabled pin interrupts (0..11)
*/
STATIC INLINE uint32_t Chip_GPIO_GetEnabledInts(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].IE;
}
/**
* @brief Returns raw interrupt pending status for pin interrupts for a port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @return A bifield containing the raw pending interrupt states for each pin (0..11) on the port
*/
STATIC INLINE uint32_t Chip_GPIO_GetRawInts(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].RIS;
}
/**
* @brief Returns masked interrupt pending status for pin interrupts for a port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @return A bifield containing the masked pending interrupt states for each pin (0..11) on the port
*/
STATIC INLINE uint32_t Chip_GPIO_GetMaskedInts(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO[port].MIS;
}
/**
* @brief Clears pending interrupts for selected pins for a port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pinmask : Pins to clear interrupts for (ORed value of bits 0..11)
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_ClearInts(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
{
pGPIO[port].IC = pinmask;
}
/**
* @brief GPIO interrupt mode definitions
*/
typedef enum {
GPIO_INT_ACTIVE_LOW_LEVEL = 0x0, /*!< Selects interrupt on pin to be triggered on LOW level */
GPIO_INT_ACTIVE_HIGH_LEVEL = 0x1, /*!< Selects interrupt on pin to be triggered on HIGH level */
GPIO_INT_FALLING_EDGE = 0x2, /*!< Selects interrupt on pin to be triggered on FALLING level */
GPIO_INT_RISING_EDGE = 0x3, /*!< Selects interrupt on pin to be triggered on RISING level */
GPIO_INT_BOTH_EDGES = 0x6 /*!< Selects interrupt on pin to be triggered on both edges */
} GPIO_INT_MODE_T;
/**
* @brief Composite function for setting up a full interrupt configuration for a single pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : Port number
* @param pin : Pin number (0..11)
* @param modeFlags : GPIO interrupt mode selection
* @return Nothing
*/
void Chip_GPIO_SetupPinInt(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, GPIO_INT_MODE_T mode);
#endif /* defined(CHIP_LPC1343) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GPIO_13XX_2_H_ */

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/*
* @brief LPC13xx GPIO group driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPIOGROUP_13XX_H_
#define __GPIOGROUP_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPIOGP_13XX CHIP: LPC13xx GPIO group driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
#if defined(CHIP_LPC1347)
/**
* @brief GPIO grouped interrupt register block structure
*/
typedef struct { /*!< GPIO_GROUP_INTn Structure */
__IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */
__IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */
uint32_t RESERVED1[1000];
} LPC_GPIOGROUPINT_T;
/**
* LPC13xx GPIO group bit definitions
*/
#define GPIOGR_INT (1 << 0) /*!< GPIO interrupt pending/clear bit */
#define GPIOGR_COMB (1 << 1) /*!< GPIO interrupt OR(0)/AND(1) mode bit */
#define GPIOGR_TRIG (1 << 2) /*!< GPIO interrupt edge(0)/level(1) mode bit */
/**
* @brief Clear interrupt pending status for the selected group
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
uint32_t temp;
temp = pGPIOGPINT[group].CTRL;
pGPIOGPINT[group].CTRL = temp | GPIOGR_INT;
}
/**
* @brief Returns current GPIO group inetrrupt pending status
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return true if the group interrupt is pending, otherwise false.
*/
STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0);
}
/**
* @brief Selected GPIO group functionality for trigger on any pin in group (OR mode)
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
pGPIOGPINT[group].CTRL &= ~GPIOGR_COMB;
}
/**
* @brief Selected GPIO group functionality for trigger on all matching pins in group (AND mode)
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectAndMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
pGPIOGPINT[group].CTRL |= GPIOGR_COMB;
}
/**
* @brief Selected GPIO group functionality edge trigger mode
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectEdgeMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
pGPIOGPINT[group].CTRL &= ~GPIOGR_TRIG;
}
/**
* @brief Selected GPIO group functionality level trigger mode
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectLevelMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
pGPIOGPINT[group].CTRL |= GPIOGR_TRIG;
}
/**
* @brief Set selected pins for the group and port to low level trigger
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @param port : GPIO port number
* @param pinMask : Or'ed value of pins to select for low level (bit 0 = pin 0, 1 = pin1, etc.)
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectLowLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
uint8_t group,
uint8_t port,
uint32_t pinMask)
{
pGPIOGPINT[group].PORT_POL[port] &= ~pinMask;
}
/**
* @brief Set selected pins for the group and port to high level trigger
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @param port : GPIO port number
* @param pinMask : Or'ed value of pins to select for high level (bit 0 = pin 0, 1 = pin1, etc.)
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectHighLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
uint8_t group,
uint8_t port,
uint32_t pinMask)
{
pGPIOGPINT[group].PORT_POL[port] |= pinMask;
}
/**
* @brief Disabled selected pins for the group interrupt
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @param port : GPIO port number
* @param pinMask : Or'ed value of pins to disable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
* @return None
* @note Disabled pins do not contrinute to the group interrupt.
*/
STATIC INLINE void Chip_GPIOGP_DisableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
uint8_t group,
uint8_t port,
uint32_t pinMask)
{
pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask;
}
/**
* @brief Enable selected pins for the group interrupt
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @param port : GPIO port number
* @param pinMask : Or'ed value of pins to enable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
* @return None
* @note Enabled pins contribute to the group interrupt.
*/
STATIC INLINE void Chip_GPIOGP_EnableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
uint8_t group,
uint8_t port,
uint32_t pinMask)
{
pGPIOGPINT[group].PORT_ENA[port] |= pinMask;
}
#endif /* defined(CHIP_LPC1347) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GPIOGROUP_13XX_H_ */

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/*
* @brief LPC13xx I2C driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __I2C_13XX_H_
#define __I2C_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup I2C_13XX CHIP: LPC13xx I2C driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief I2C register block structure
*/
typedef struct { /* I2C0 Structure */
__IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
__IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
__IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
__IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
__O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__IO uint32_t MMCTRL; /*!< Monitor mode control register. */
__IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
__IO uint32_t MASK[4]; /*!< I2C Slave address mask register */
} LPC_I2C_T;
/**
* @brief Return values for SLAVE handler
* @note
* Chip drivers will usally be designed to match their events with this value
*/
#define RET_SLAVE_TX 6 /**< Return value, when 1 byte TX'd successfully */
#define RET_SLAVE_RX 5 /**< Return value, when 1 byte RX'd successfully */
#define RET_SLAVE_IDLE 2 /**< Return value, when slave enter idle mode */
#define RET_SLAVE_BUSY 0 /**< Return value, when slave is busy */
/**
* @brief I2C state handle return values
*/
#define I2C_STA_STO_RECV 0x20
/*
* @brief I2C Control Set register description
*/
#define I2C_I2CONSET_AA ((0x04))/*!< Assert acknowledge flag */
#define I2C_I2CONSET_SI ((0x08))/*!< I2C interrupt flag */
#define I2C_I2CONSET_STO ((0x10))/*!< STOP flag */
#define I2C_I2CONSET_STA ((0x20))/*!< START flag */
#define I2C_I2CONSET_I2EN ((0x40))/*!< I2C interface enable */
/*
* @brief I2C Control Clear register description
*/
#define I2C_I2CONCLR_AAC ((1 << 2)) /*!< Assert acknowledge Clear bit */
#define I2C_I2CONCLR_SIC ((1 << 3)) /*!< I2C interrupt Clear bit */
#define I2C_I2CONCLR_STOC ((1 << 4)) /*!< I2C STOP Clear bit */
#define I2C_I2CONCLR_STAC ((1 << 5)) /*!< START flag Clear bit */
#define I2C_I2CONCLR_I2ENC ((1 << 6)) /*!< I2C interface Disable bit */
/*
* @brief I2C Common Control register description
*/
#define I2C_CON_AA (1UL << 2) /*!< Assert acknowledge bit */
#define I2C_CON_SI (1UL << 3) /*!< I2C interrupt bit */
#define I2C_CON_STO (1UL << 4) /*!< I2C STOP bit */
#define I2C_CON_STA (1UL << 5) /*!< START flag bit */
#define I2C_CON_I2EN (1UL << 6) /*!< I2C interface bit */
/*
* @brief I2C Status Code definition (I2C Status register)
*/
#define I2C_STAT_CODE_BITMASK ((0xF8))/*!< Return Code mask in I2C status register */
#define I2C_STAT_CODE_ERROR ((0xFF))/*!< Return Code error mask in I2C status register */
/*
* @brief I2C return status code definitions
*/
#define I2C_I2STAT_NO_INF ((0xF8))/*!< No relevant information */
#define I2C_I2STAT_BUS_ERROR ((0x00))/*!< Bus Error */
/*
* @brief I2C Master transmit mode
*/
#define I2C_I2STAT_M_TX_START ((0x08))/*!< A start condition has been transmitted */
#define I2C_I2STAT_M_TX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))/*!< SLA+W has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))/*!< SLA+W has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))/*!< Data has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))/*!< Data has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */
/*
* @brief I2C Master receive mode
*/
#define I2C_I2STAT_M_RX_START ((0x08))/*!< A start condition has been transmitted */
#define I2C_I2STAT_M_RX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))/*!< Arbitration lost */
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))/*!< SLA+R has been transmitted, ACK has been received */
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))/*!< SLA+R has been transmitted, NACK has been received */
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))/*!< Data has been received, ACK has been returned */
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))/*!< Data has been received, NACK has been returned */
/*
* @brief I2C Slave receive mode
*/
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))/*!< Own slave address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))/*!< Arbitration lost in SLA+R/W as master */
// #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) /*!< Own SLA+W has been received, ACK returned */
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))/*!< General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */
// #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) /*!< General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or
SLV/TRX (Slave Transmit) */
/*
* @brief I2C Slave transmit mode
*/
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))/*!< Arbitration lost in SLA+R/W as master */
// #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))/*!< Data has been transmitted, ACK has been received */
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))/*!< Data has been transmitted, NACK has been received */
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */
#define I2C_SLAVE_TIME_OUT 0x10000000UL/*!< Time out in case of using I2C slave mode */
/*
* @brief I2C Data register definition
*/
#define I2C_I2DAT_BITMASK ((0xFF))/*!< Mask for I2DAT register */
#define I2C_I2DAT_IDLE_CHAR (0xFF) /*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than
its sending data length that can be supported */
/*
* @brief I2C Monitor mode control register description
*/
#define I2C_I2MMCTRL_MM_ENA ((1 << 0)) /**< Monitor mode enable */
#define I2C_I2MMCTRL_ENA_SCL ((1 << 1)) /**< SCL output enable */
#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) /**< Select interrupt register match */
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
/*
* @brief I2C Data buffer register description
*/
#define I2DATA_BUFFER_BITMASK ((0xFF))/*!< I2C Data buffer register bit mask */
/*
* @brief I2C Slave Address registers definition
*/
#define I2C_I2ADR_GC ((1 << 0)) /*!< General Call enable bit */
#define I2C_I2ADR_BITMASK ((0xFF))/*!< I2C Slave Address registers bit mask */
/*
* @brief I2C Mask Register definition
*/
#define I2C_I2MASK_MASK(n) ((n & 0xFE))/*!< I2C Mask Register mask field */
/*
* @brief I2C SCL HIGH duty cycle Register definition
*/
#define I2C_I2SCLH_BITMASK ((0xFFFF)) /*!< I2C SCL HIGH duty cycle Register bit mask */
/*
* @brief I2C SCL LOW duty cycle Register definition
*/
#define I2C_I2SCLL_BITMASK ((0xFFFF)) /*!< I2C SCL LOW duty cycle Register bit mask */
/*
* @brief I2C status values
*/
#define I2C_SETUP_STATUS_ARBF (1 << 8) /**< Arbitration false */
#define I2C_SETUP_STATUS_NOACKF (1 << 9) /**< No ACK returned */
#define I2C_SETUP_STATUS_DONE (1 << 10) /**< Status DONE */
/*
* @brief I2C state handle return values
*/
#define I2C_OK 0x00
#define I2C_BYTE_SENT 0x01
#define I2C_BYTE_RECV 0x02
#define I2C_LAST_BYTE_RECV 0x04
#define I2C_SEND_END 0x08
#define I2C_RECV_END 0x10
#define I2C_STA_STO_RECV 0x20
#define I2C_ERR (0x10000000)
#define I2C_NAK_RECV (0x10000000 | 0x01)
#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
/*
* @brief I2C monitor control configuration defines
*/
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
/**
* @brief I2C Slave Identifiers
*/
typedef enum {
I2C_SLAVE_GENERAL, /**< Slave ID for general calls */
I2C_SLAVE_0, /**< Slave ID fo Slave Address 0 */
I2C_SLAVE_1, /**< Slave ID fo Slave Address 1 */
I2C_SLAVE_2, /**< Slave ID fo Slave Address 2 */
I2C_SLAVE_3, /**< Slave ID fo Slave Address 3 */
I2C_SLAVE_NUM_INTERFACE /**< Number of slave interfaces */
} I2C_SLAVE_ID;
/**
* @brief I2C transfer status
*/
typedef enum {
I2C_STATUS_DONE, /**< Transfer done successfully */
I2C_STATUS_NAK, /**< NAK received during transfer */
I2C_STATUS_ARBLOST, /**< Aribitration lost during transfer */
I2C_STATUS_BUSERR, /**< Bus error in I2C transfer */
I2C_STATUS_BUSY, /**< I2C is busy doing transfer */
} I2C_STATUS_T;
/**
* @brief Master transfer data structure definitions
*/
typedef struct {
uint8_t slaveAddr; /**< 7-bit I2C Slave address */
const uint8_t *txBuff; /**< Pointer to array of bytes to be transmitted */
int txSz; /**< Number of bytes in transmit array,
if 0 only receive transfer will be carried on */
uint8_t *rxBuff; /**< Pointer memory where bytes received from I2C be stored */
int rxSz; /**< Number of bytes to received,
if 0 only transmission we be carried on */
I2C_STATUS_T status; /**< Status of the current I2C transfer */
} I2C_XFER_T;
/**
* @brief I2C interface IDs
* @note
* All Chip functions will take this as the first parameter,
* I2C_NUM_INTERFACE must never be used for calling any Chip
* functions, it is only used to find the number of interfaces
* available in the Chip.
*/
typedef enum I2C_ID {
I2C0, /**< ID I2C0 */
I2C_NUM_INTERFACE /**< Number of I2C interfaces in the chip */
} I2C_ID_T;
/**
* @brief I2C master events
*/
typedef enum {
I2C_EVENT_WAIT = 1, /**< I2C Wait event */
I2C_EVENT_DONE, /**< Done event that wakes up Wait event */
I2C_EVENT_LOCK, /**< Re-entrency lock event for I2C transfer */
I2C_EVENT_UNLOCK, /**< Re-entrency unlock event for I2C transfer */
I2C_EVENT_SLAVE_RX, /**< Slave receive event */
I2C_EVENT_SLAVE_TX, /**< Slave transmit event */
} I2C_EVENT_T;
/**
* @brief Event handler function type
*/
typedef void (*I2C_EVENTHANDLER_T)(I2C_ID_T, I2C_EVENT_T);
/**
* @brief Initializes the LPC_I2C peripheral with specified parameter.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_Init(I2C_ID_T id);
/**
* @brief De-initializes the I2C peripheral registers to their default reset values
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_DeInit(I2C_ID_T id);
/**
* @brief Set up clock rate for LPC_I2C peripheral.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param clockrate : Target clock rate value to initialized I2C peripheral (Hz)
* @return Nothing
* @note
* Parameter @a clockrate for I2C0 should be from 1000 up to 1000000
* (1 KHz to 1 MHz), as I2C0 support Fast Mode Plus. If the @a clockrate
* is more than 400 KHz (Fast Plus Mode) Board_I2C_EnableFastPlus()
* must be called prior to calling this function.
*/
void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate);
/**
* @brief Get current clock rate for LPC_I2C peripheral.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return The current I2C peripheral clock rate
*/
uint32_t Chip_I2C_GetClockRate(I2C_ID_T id);
/**
* @brief Transmit and Receive data in master mode
* @param id : I2C peripheral selected (I2C0, I2C1 etc)
* @param xfer : Pointer to a I2C_XFER_T structure see notes below
* @return
* Any of #I2C_STATUS_T values, xfer->txSz will have number of bytes
* not sent due to error, xfer->rxSz will have the number of bytes yet
* to be received.
* @note
* The parameter @a xfer should have its member @a slaveAddr initialized
* to the 7-Bit slave address to which the master will do the xfer, Bit0
* to bit6 should have the address and Bit8 is ignored. During the transfer
* no code (like event handler) must change the content of the memory
* pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
* initialized to the memory from which the I2C must pick the data to be
* transfered to slave and the number of bytes to send respectively, similarly
* @a rxBuff and @a rxSz must have pointer to memroy where data received
* from slave be stored and the number of data to get from slave respectilvely.
*/
int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer);
/**
* @brief Transmit data to I2C slave using I2C Master mode
* @param id : I2C peripheral ID (I2C0, I2C1 .. etc)
* @param slaveAddr : Slave address to which the data be written
* @param buff : Pointer to buffer having the array of data
* @param len : Number of bytes to be transfered from @a buff
* @return Number of bytes successfully transfered
*/
int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len);
/**
* @brief Transfer a command to slave and receive data from slave after a repeated start
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param slaveAddr : Slave address of the I2C device
* @param cmd : Command (Address/Register) to be written
* @param buff : Pointer to memory that will hold the data received
* @param len : Number of bytes to receive
* @return Number of bytes successfully received
*/
int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len);
/**
* @brief Get pointer to current function handling the events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Pointer to function handing events of I2C
*/
I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id);
/**
* @brief Set function that must handle I2C events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Pointer to function that will handle the event (Should not be NULL)
* @return 1 when successful, 0 when a transfer is on going with its own event handler
*/
int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event);
/**
* @brief Set function that must handle I2C events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param slaveAddr : Slave address from which data be read
* @param buff : Pointer to memory where data read be stored
* @param len : Number of bytes to read from slave
* @return Number of bytes read successfully
*/
int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len);
/**
* @brief Default event handler for polling operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Event ID of the event that called the function
* @return Nothing
*/
void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event);
/**
* @brief Default event handler for interrupt base operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Event ID of the event that called the function
* @return Nothing
*/
void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event);
/**
* @brief I2C Master transfer state change handler
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
* @note Usually called from the appropriate Interrupt handler
*/
void Chip_I2C_MasterStateHandler(I2C_ID_T id);
/**
* @brief Disable I2C peripheral's operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_Disable(I2C_ID_T id);
/**
* @brief Checks if master xfer in progress
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return 1 if master xfer in progress 0 otherwise
* @note
* This API is generally used in interrupt handler
* of the application to decide whether to call
* master state handler or to call slave state handler
*/
int Chip_I2C_IsMasterActive(I2C_ID_T id);
/**
* @brief Setup a slave I2C device
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param sid : I2C Slave peripheral ID (I2C_SLAVE_0, I2C_SLAVE_1 etc)
* @param xfer : Pointer to transfer structure (see note below for more info)
* @param event : Event handler for slave transfers
* @param addrMask : Address mask to use along with slave address (see notes below for more info)
* @return Nothing
* @note
* Parameter @a xfer should point to a valid I2C_XFER_T structure object
* and must have @a slaveAddr initialized with 7bit Slave address (From Bit1 to Bit7),
* Bit0 when set enables general call handling, @a slaveAddr along with @a addrMask will
* be used to match the slave address. @a rxBuff and @a txBuff must point to valid buffers
* where slave can receive or send the data from, size of which will be provided by
* @a rxSz and @a txSz respectively. Function pointed to by @a event will be called
* for the following events #I2C_EVENT_SLAVE_RX (One byte of data received successfully
* from the master and stored inside memory pointed by xfer->rxBuff, incremented
* the pointer and decremented the @a xfer->rxSz), #I2C_EVENT_SLAVE_TX (One byte of
* data from xfer->txBuff was sent to master successfully, incremented the pointer
* and decremented xfer->txSz), #I2C_EVENT_DONE (Master is done doing its transfers
* with the slave).<br>
* <br>Bit-0 of the parameter @a addrMask is reserved and should always be 0. Any bit (BIT1
* to BIT7) set in @a addrMask will make the corresponding bit in *xfer->slaveAddr* as
* don't care. Thit is, if *xfer->slaveAddr* is (0x10 << 1) and @a addrMask is (0x03 << 1) then
* 0x10, 0x11, 0x12, 0x13 will all be considered as valid slave addresses for the registered
* slave. Upon receving any event *xfer->slaveAddr* (BIT1 to BIT7) will hold the actual
* address which was received from master.<br>
* <br><b>General Call Handling</b><br>
* Slave can receive data from master using general call address (0x00). General call
* handling must be setup as given below
* - Call Chip_I2C_SlaveSetup() with argument @a sid as I2C_SLAVE_GENERAL
* - xfer->slaveAddr ignored, argument @a addrMask ignored
* - function provided by @a event will registered to be called when slave received data using addr 0x00
* - xfer->rxBuff and xfer->rxSz should be valid in argument @a xfer
* - To handle General Call only (No other slaves are configured)
* - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
* - setup @a xfer with slaveAddr member set to 0, @a event is ignored hence can be NULL
* - provide @a addrMask (typically 0, if not you better be knowing what you are doing)
* - To handler General Call when other slave is active
* - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
* - setup @a xfer with slaveAddr member set to 7-Bit Slave address [from Bit1 to 7]
* - Set Bit0 of @a xfer->slaveAddr as 1
* - Provide appropriate @a addrMask
* - Argument @a event must point to function, that handles events from actual slaveAddress and not the GC
* @warning
* If the slave has only one byte in its txBuff, once that byte is transfered to master the event handler
* will be called for event #I2C_EVENT_DONE. If the master attempts to read more bytes in the same transfer
* then the slave hardware will send 0xFF to master till the end of transfer, event handler will not be
* called to notify this. For more info see section below<br>
* <br><b> Last data handling in slave </b><br>
* If the user wants to implement a slave which will read a byte from a specific location over and over
* again whenever master reads the slave. If the user initializes the xfer->txBuff as the location to read
* the byte from and xfer->txSz as 1, then say, if master reads one byte; slave will send the byte read from
* xfer->txBuff and will call the event handler with #I2C_EVENT_DONE. If the master attempts to read another
* byte instead of sending the byte read from xfer->txBuff the slave hardware will send 0xFF and no event will
* occur. To handle this issue, slave should set xfer->txSz to 2, in which case when master reads the byte
* event handler will be called with #I2C_EVENT_SLAVE_TX, in which the slave implementation can reset the buffer
* and size back to original location (i.e, xfer->txBuff--, xfer->txSz++), if the master reads another byte
* in the same transfer, byte read from xfer->txBuff will be sent and #I2C_EVENT_SLAVE_TX will be called again, and
* the process repeats.
*/
void Chip_I2C_SlaveSetup(I2C_ID_T id,
I2C_SLAVE_ID sid,
I2C_XFER_T *xfer,
I2C_EVENTHANDLER_T event,
uint8_t addrMask);
/**
* @brief I2C Slave event handler
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_SlaveStateHandler(I2C_ID_T id);
/**
* @brief I2C peripheral state change checking
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return 1 if I2C peripheral @a id has changed its state,
* 0 if there is no state change
* @note
* This function must be used by the application when
* the polling has to be done based on state change.
*/
int Chip_I2C_IsStateChanged(I2C_ID_T id);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __I2C_13XX_H_ */

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/*
* @brief LPC13XX I2C master driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __I2CM_13XX_H_
#define __I2CM_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup I2CM_13XX CHIP: LPC13xx I2C master-only driver
* @ingroup I2C_13XX
* This driver only works in master mode. To describe the I2C transactions
* following symbols are used in driver documentation.
*
* Key to symbols
* ==============
* S (1 bit) : Start bit
* P (1 bit) : Stop bit
* Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
* A, NA (1 bit) : Acknowledge and Not-Acknowledge bit.
* Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
* get a 10 bit I2C address.
* Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
* for 16 bit data.
* [..]: Data sent by I2C device, as opposed to data sent by the host adapter.
* @{
*/
/** I2CM_13XX_OPTIONS_TYPES I2C master transfer options
* @{
*/
/** Ignore NACK during data transfer. By default transfer is aborted. */
#define I2CM_XFER_OPTION_IGNORE_NACK 0x01
/** ACK last byte received. By default we NACK last byte we receive per I2C spec. */
#define I2CM_XFER_OPTION_LAST_RX_ACK 0x02
/**
* @}
*/
/** I2CM_13XX_STATUS_TYPES I2C master transfer status types
* @{
*/
#define I2CM_STATUS_OK 0x00 /*!< Requested Request was executed successfully. */
#define I2CM_STATUS_ERROR 0x01 /*!< Unknown error condition. */
#define I2CM_STATUS_NAK 0x02 /*!< No acknowledgement received from slave. */
#define I2CM_STATUS_BUS_ERROR 0x03 /*!< I2C bus error */
#define I2CM_STATUS_SLAVE_NAK 0x04 /*!< No device responded for given slave address during SLA+W or SLA+R */
#define I2CM_STATUS_ARBLOST 0x05 /*!< Arbitration lost. */
#define I2CM_STATUS_BUSY 0xFF /*!< I2C transmistter is busy. */
/**
* @}
*/
/**
* @brief Master transfer data structure definitions
*/
typedef struct {
uint8_t slaveAddr; /*!< 7-bit I2C Slave address */
uint8_t options; /*!< Options for transfer*/
uint16_t status; /*!< Status of the current I2C transfer */
uint16_t txSz; /*!< Number of bytes in transmit array,
if 0 only receive transfer will be carried on */
uint16_t rxSz; /*!< Number of bytes to received,
if 0 only transmission we be carried on */
const uint8_t *txBuff; /*!< Pointer to array of bytes to be transmitted */
uint8_t *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */
} I2CM_XFER_T;
/**
* @brief Initialize I2C Interface
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function enables the I2C clock.
*/
void Chip_I2CM_Init(LPC_I2C_T *pI2C);
/**
* @brief Shutdown I2C Interface
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function disables the I2C clock.
*/
void Chip_I2CM_DeInit(LPC_I2C_T *pI2C);
/**
* @brief Sets HIGH and LOW duty cycle registers
* @param pI2C : Pointer to selected I2C peripheral
* @param sclH : Number of I2C_PCLK cycles for the SCL HIGH time.
* @param sclL : Number of I2C_PCLK cycles for the SCL LOW time.
* @return Nothing
* @note The frequency is determined by the following formula (I2C_PCLK
* is the frequency of the peripheral I2C clock): <br>
* I2C_bitFrequency = (I2C_PCLK)/(sclH + sclL);
*/
static INLINE void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL)
{
pI2C->SCLH = (uint32_t) sclH;
pI2C->SCLL = (uint32_t) sclL;
}
/**
* @brief Set up bus speed for LPC_I2C controller
* @param pI2C : Pointer to selected I2C peripheral
* @param busSpeed : I2C bus clock rate
* @return Nothing
* @note Per I2C specification the busSpeed should be
* @li 100000 for Standard mode
* @li 400000 for Fast mode
* @li 1000000 for Fast mode plus
* IOCON registers corresponding to I2C pads should be updated
* according to the bus mode.
*/
void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed);
/**
* @brief Transmit START or Repeat-START signal on I2C bus
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function sets the controller to transmit START condition when
* the bus becomes free.
*/
static INLINE void Chip_I2CM_SendStart(LPC_I2C_T *pI2C)
{
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
}
/**
* @brief Reset I2C controller state
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function clears all control/status flags.
*/
static INLINE void Chip_I2CM_ResetControl(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
}
/**
* @brief Transmit a single data byte through the I2C peripheral
* @param pI2C : Pointer to selected I2C peripheral
* @param data : Byte to transmit
* @return Nothing
* @note This function attempts to place a byte into the UART transmit
* FIFO or transmit hold register regard regardless of UART state
*
*/
static INLINE void Chip_I2CM_WriteByte(LPC_I2C_T *pI2C, uint8_t data)
{
pI2C->DAT = (uint32_t) data;
}
/**
* @brief Read a single byte data from the I2C peripheral
* @param pI2C : Pointer to selected I2C peripheral
* @return A single byte of data read
* @note This function reads a byte from the I2C receive hold register
* regardless of I2C state. The I2C status should be read first prior
* to using this function.
*/
static INLINE uint8_t Chip_I2CM_ReadByte(LPC_I2C_T *pI2C)
{
return (uint8_t) (pI2C->DAT & I2C_I2DAT_BITMASK);
}
/**
* @brief Generate NACK after receiving next byte
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function sets the controller to NACK after receiving next
* byte from slave transmitter. Used before receiving last byte.
*/
static INLINE void Chip_I2CM_NackNextByte(LPC_I2C_T *pI2C)
{
pI2C->CONCLR = I2C_CON_AA;
}
/**
* @brief Transmit STOP signal on I2C bus
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function sets the controller to transmit STOP condition.
*/
static INLINE void Chip_I2CM_SendStop(LPC_I2C_T *pI2C)
{
pI2C->CONSET = I2C_CON_STO;
}
/**
* @brief Force start I2C transmit
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function force I2C state machine to start transmitting.
* If an uncontrolled source generates a superfluous START or masks
* a STOP condition, then the I2C-bus stays busy indefinitely. If
* the STA flag is set and bus access is not obtained within a
* reasonable amount of time, then a forced access to the I2C-bus is
* possible. This is achieved by setting the STO flag while the STA
* flag is still set. No STOP condition is transmitted.
*/
static INLINE void Chip_I2CM_ForceStart(LPC_I2C_T *pI2C)
{
/* check if we are pending on start */
if (pI2C->CONSET & I2C_CON_STA) {
pI2C->CONSET = I2C_CON_STO;
}
else {
Chip_I2CM_SendStart(pI2C);
}
}
/**
* @brief Transmit STOP+START signal on I2C bus
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function sets the controller to transmit STOP condition
* followed by a START condition.
*/
static INLINE void Chip_I2CM_SendStartAfterStop(LPC_I2C_T *pI2C)
{
pI2C->CONSET = I2C_CON_STO | I2C_CON_STA;
}
/**
* @brief Check if I2C controller state changed
* @param pI2C : Pointer to selected I2C peripheral
* @return Returns 0 if state didn't change
* @note
*/
static INLINE uint32_t Chip_I2CM_StateChanged(LPC_I2C_T *pI2C)
{
return pI2C->CONSET & I2C_CON_SI;
}
/**
* @brief Clear state change interrupt flag
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note
*/
static INLINE void Chip_I2CM_ClearSI(LPC_I2C_T *pI2C)
{
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
}
/**
* @brief Check if I2C bus is free per our controller
* @param pI2C : Pointer to selected I2C peripheral
* @return Returns 0 if busy else a non-zero value.
* @note I2C controller clears STO bit when it sees STOP
* condition after a START condition on the bus.
*/
static INLINE uint32_t Chip_I2CM_BusFree(LPC_I2C_T *pI2C)
{
return !(pI2C->CONSET & I2C_CON_STO);
}
/**
* @brief Get current state of the I2C controller
* @param pI2C : Pointer to selected I2C peripheral
* @return Returns 0 if busy else a non-zero value.
* @note I2C controller clears STO bit when it sees STOP
* condition after a START condition on the bus.
*/
static INLINE uint32_t Chip_I2CM_GetCurState(LPC_I2C_T *pI2C)
{
return pI2C->STAT & I2C_STAT_CODE_BITMASK;
}
/**
* @brief Disable I2C interface
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note
*/
static INLINE void Chip_I2CM_Disable(LPC_I2C_T *pI2C)
{
pI2C->CONCLR = I2C_CON_I2EN;
}
/**
* @brief Transfer state change handler handler
* @param pI2C : Pointer to selected I2C peripheral
* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
* @return Returns non-zero value on completion of transfer. The @a status
* member of @a xfer structure contains the current status of the
* transfer at the end of the call.
* @note
* The parameter @a xfer should be same as the one passed to Chip_I2CM_Xfer()
* routine.
*/
uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
/**
* @brief Transmit and Receive data in master mode
* @param pI2C : Pointer to selected I2C peripheral
* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
* @return Nothing.
* @note
* The parameter @a xfer should have its member @a slaveAddr initialized
* to the 7-Bit slave address to which the master will do the xfer, Bit0
* to bit6 should have the address and Bit8 is ignored. During the transfer
* no code (like event handler) must change the content of the memory
* pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
* initialized to the memory from which the I2C must pick the data to be
* transfered to slave and the number of bytes to send respectively, similarly
* @a rxBuff and @a rxSz must have pointer to memroy where data received
* from slave be stored and the number of data to get from slave respectilvely.
* Following types of transfers are possible:
* - Write-only transfer: When @a rxSz member of @a xfer is set to 0.
*
* S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] P
*
* - If I2CM_XFER_OPTION_IGNORE_NACK is set in @a options memeber
*
* S Addr Wr [A] txBuff0 [A or NA] ... txBuffN [A or NA] P
*
* - Read-only transfer: When @a txSz member of @a xfer is set to 0.
*
* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P
*
* - If I2CM_XFER_OPTION_LAST_RX_ACK is set in @a options memeber
*
* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] A P
*
* - Read-Write transfer: When @a rxSz and @ txSz members of @a xfer are non-zero.
*
* S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A]
* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P
*
*/
void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
/**
* @brief Transmit and Receive data in master mode
* @param pI2C : Pointer to selected I2C peripheral
* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
* @return Returns non-zero value on succesful completion of transfer.
* @note
* This function operates same as Chip_I2CM_Xfer(), but is a blocking call.
*/
uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
/**
* @brief Write given buffer of data to I2C interface
* @param pI2C : Pointer to selected I2C peripheral
* @param buff : Pointer to buffer to be transmitted
* @param len : Length of the buffer
* @return Returns number of bytes written.
* @note This function is a blocking call. The function generates
* START/repeat-START condition on bus and starts transmitting
* data untill transfer finishes or a NACK is received. No
* STOP condition is transmitted on the bus.
*
* S Data0 [A] Data1 [A] ... DataN [A]
*/
uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len);
/**
* @brief Read data from I2C slave to given buffer
* @param pI2C : Pointer to selected I2C peripheral
* @param buff : Pointer to buffer for data received from I2C slave
* @param len : Length of the buffer
* @return Returns number of bytes read.
* @note This function is a blocking call. The function generates
* START/repeat-START condition on bus and starts reading
* data untill requested number of bytes are read. No
* STOP condition is transmitted on the bus.
*
* S [Data0] A [Data1] A ... [DataN] A
*/
uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __I2C_13XX_H_ */

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/*
* @brief LPC13xx IOCON registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __IOCON_13XX_H_
#define __IOCON_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup IOCON_13XX CHIP: LPC13xx IO Control driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief Array of IOCON pin definitions passed to Chip_IOCON_SetPinMuxing() must be in this format
*/
typedef struct {
#if defined(CHIP_LPC1347)
uint32_t port:8; /* Pin port */
uint32_t pin:8; /* Pin number */
uint32_t modefunc:16; /* Function and mode */
#else
uint32_t pin:8; /* Pin number */
uint32_t modefunc:24; /* Function and mode */
#endif
} PINMUX_GRP_T;
/**
* @brief IO Configuration Unit register block structure
*/
#if defined(CHIP_LPC1347)
typedef struct { /*!< LPC1347 IOCON Structure */
__IO uint32_t PIO0[24];
__IO uint32_t PIO1[32];
} LPC_IOCON_T;
#else
/**
* @brief LPC13XX I/O Configuration register offset
*/
typedef enum CHIP_IOCON_PIO {
IOCON_PIO0_0 = (0x00C >> 2),
IOCON_PIO0_1 = (0x010 >> 2),
IOCON_PIO0_2 = (0x01C >> 2),
IOCON_PIO0_3 = (0x02C >> 2),
IOCON_PIO0_4 = (0x030 >> 2),
IOCON_PIO0_5 = (0x034 >> 2),
IOCON_PIO0_6 = (0x04C >> 2),
IOCON_PIO0_7 = (0x050 >> 2),
IOCON_PIO0_8 = (0x060 >> 2),
IOCON_PIO0_9 = (0x064 >> 2),
IOCON_PIO0_11 = (0x074 >> 2),
IOCON_PIO1_0 = (0x078 >> 2),
IOCON_PIO1_1 = (0x07C >> 2),
IOCON_PIO1_2 = (0x080 >> 2),
IOCON_PIO1_3 = (0x090 >> 2),
IOCON_PIO1_4 = (0x094 >> 2),
IOCON_PIO1_5 = (0x0A0 >> 2),
IOCON_PIO1_6 = (0x0A4 >> 2),
IOCON_PIO1_7 = (0x0A8 >> 2),
IOCON_PIO1_8 = (0x014 >> 2),
IOCON_PIO1_9 = (0x038 >> 2),
IOCON_PIO1_10 = (0x06C >> 2),
IOCON_PIO1_11 = (0x098 >> 2),
IOCON_PIO2_0 = (0x008 >> 2),
IOCON_PIO2_1 = (0x028 >> 2),
IOCON_PIO2_2 = (0x05C >> 2),
IOCON_PIO2_3 = (0x08C >> 2),
IOCON_PIO2_4 = (0x040 >> 2),
IOCON_PIO2_5 = (0x044 >> 2),
IOCON_PIO2_6 = (0x000 >> 2),
IOCON_PIO2_7 = (0x020 >> 2),
IOCON_PIO2_8 = (0x024 >> 2),
IOCON_PIO2_9 = (0x054 >> 2),
IOCON_PIO2_10 = (0x058 >> 2),
IOCON_PIO2_11 = (0x070 >> 2),
IOCON_PIO3_0 = (0x084 >> 2),
IOCON_PIO3_1 = (0x088 >> 2),
IOCON_PIO3_2 = (0x09C >> 2),
IOCON_PIO3_3 = (0x0AC >> 2),
IOCON_PIO3_4 = (0x03C >> 2),
IOCON_PIO3_5 = (0x048 >> 2),
} CHIP_IOCON_PIO_T;
/**
* @brief LPC13XX Pin location select
*/
typedef enum CHIP_IOCON_PIN_LOC {
IOCON_SCKLOC_PIO0_10 = (0xB0), /*!< Selects SCK0 function in pin location PIO0_10 */
IOCON_SCKLOC_PIO2_11 = (0xB0 | 1), /*!< Selects SCK0 function in pin location PIO2_11 */
IOCON_SCKLOC_PIO0_6 = (0xB0 | 2), /*!< Selects SCK0 function in pin location PIO0_6 */
IOCON_DSRLOC_PIO2_1 = (0xB4), /*!< Selects DSR function in pin location PIO2_1 */
IOCON_DSRLOC_PIO3_1 = (0xB4 | 1), /*!< Selects DSR function in pin location PIO3_1 */
IOCON_DCDLOC_PIO2_2 = (0xB8), /*!< Selects DCD function in pin location PIO2_2 */
IOCON_DCDLOC_PIO3_2 = (0xB8 | 1), /*!< Selects DCD function in pin location PIO3_2 */
IOCON_RILOC_PIO2_3 = (0xBC), /*!< Selects RI function in pin location PIO2_3 */
IOCON_RILOC_PIO3_3 = (0xBC | 1), /*!< Selects Ri function in pin location PIO3_3 */
} CHIP_IOCON_PIN_LOC_T;
typedef struct { /*!< LPC1343 IOCON Structure */
__IO uint32_t REG[48];
} LPC_IOCON_T;
#endif
/**
* IOCON function and mode selection definitions
* See the User Manual for specific modes and functions supoprted by the
* various LPC13xx devices. Functionality can vary per device.
*/
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */
#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */
#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */
#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */
#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */
#define IOCON_RESERVED_BIT_6 (0x1 << 6) /*!< Reserved, must be set. */
#define IOCON_RESERVED_BIT_7 (0x1 << 7) /*!< Reserved, must be set. */
#define IOCON_ADMODE_EN (0x0 << 7) /*!< Enables analog input function (analog pins only) */
#define IOCON_DIGMODE_EN (0x1 << 7) /*!< Enables digital function (analog pins only) */
#define IOCON_SFI2C_EN (0x0 << 8) /*!< I2C standard mode/fast-mode */
#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard I/O functionality */
#define IOCON_FASTI2C_EN (0x2 << 8) /*!< I2C Fast-mode Plus */
#define IOCON_FILT_DIS (0x1 << 8) /*!< Disables noise pulses filtering (10nS glitch filter) */
#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */
/**
* IOCON function and mode selection definitions (old)
* For backwards compatibility.
*/
#define MD_PLN (0x0 << 3) /*!< Disable pull-down and pull-up resistor at resistor at pad */
#define MD_PDN (0x1 << 3) /*!< Enable pull-down resistor at pad */
#define MD_PUP (0x2 << 3) /*!< Enable pull-up resistor at pad */
#define MD_BUK (0x3 << 3) /*!< Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
#define MD_HYS (0x1 << 5) /*!< Enable hysteresis */
#define MD_INV (0x1 << 6) /*!< Invert enable */
#define MD_ADMODE (0x0 << 7) /*!< Select analog mode */
#define MD_DIGMODE (0x1 << 7) /*!< Select digitial mode */
#define MD_DISFIL (0x0 << 8) /*!< Disable 10nS input glitch filter */
#define MD_ENFIL (0x1 << 8) /*!< Enable 10nS input glitch filter */
#define MD_SFI2C (0x0 << 8) /*!< I2C standard mode/fast-mode */
#define MD_STDI2C (0x1 << 8) /*!< I2C standard I/O functionality */
#define MD_FASTI2C (0x2 << 8) /*!< I2C Fast-mode Plus */
#define MD_OPENDRAIN (0x1 << 10) /*!< Open drain mode bit */
#define FUNC0 0x0
#define FUNC1 0x1
#define FUNC2 0x2
#define FUNC3 0x3
#define FUNC4 0x4
#define FUNC5 0x5
#define FUNC6 0x6
#define FUNC7 0x7
#if defined(CHIP_LPC1347)
/**
* @brief Sets I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : GPIO port to mux
* @param pin : GPIO pin to mux
* @param modefunc : OR'ed values or type IOCON_*
* @return Nothing
*/
void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc);
/**
* @brief I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : GPIO port to mux
* @param pin : GPIO pin to mux
* @param mode : OR'ed values or type IOCON_*
* @param func : Pin function, value of type IOCON_FUNC?
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
{
Chip_IOCON_PinMuxSet(pIOCON, port, pin, (uint32_t) (mode | func));
}
#else
/**
* @brief Sets I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param pin : GPIO pin to mux
* @param modefunc : OR'ed values or type IOCON_*
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIO_T pin, uint32_t modefunc)
{
pIOCON->REG[pin] = modefunc;
}
/**
* @brief I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param pin : GPIO pin to mux
* @param mode : OR'ed values or type IOCON_*
* @param func : Pin function, value of type IOCON_FUNC?
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIO_T pin, uint16_t mode, uint8_t func)
{
Chip_IOCON_PinMuxSet(pIOCON, pin, (uint32_t) (mode | func));
}
/**
* @brief Select pin location
* @param pIOCON : The base of IOCON peripheral on the chip
* @param sel : location selection
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinLocSel(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIN_LOC_T sel)
{
pIOCON->REG[sel >> 2] = sel & 0x03;
}
#endif /* defined(CHIP_LPC1347) */
/**
* @brief Set all I/O Control pin muxing
* @param pIOCON : The base of IOCON peripheral on the chip
* @param pinArray : Pointer to array of pin mux selections
* @param arrayLength : Number of entries in pinArray
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T* pinArray, uint32_t arrayLength)
{
uint32_t ix;
for (ix = 0; ix < arrayLength; ix++ ) {
#if defined(CHIP_LPC1347)
Chip_IOCON_PinMuxSet(pIOCON, pinArray[ix].port, pinArray[ix].pin, pinArray[ix].modefunc);
#else
Chip_IOCON_PinMuxSet(pIOCON, (CHIP_IOCON_PIO_T) pinArray[ix].pin, pinArray[ix].modefunc);
#endif
}
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __IOCON_13XX_H_ */

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/*
* @brief Common types used in LPC functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_TYPES_H_
#define __LPC_TYPES_H_
#include <stdint.h>
#include <stdbool.h>
/** @defgroup LPC_Types CHIP: LPC Common Types
* @ingroup CHIP_Common
* @{
*/
/** @defgroup LPC_Types_Public_Types LPC Public Types
* @{
*/
/**
* @brief Boolean Type definition
*/
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
/**
* @brief Boolean Type definition
*/
#if !defined(__cplusplus)
// typedef enum {false = 0, true = !false} bool;
#endif
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
/**
* Read/Write transfer type mode (Block or non-block)
*/
typedef enum {
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)();
/**
* @}
*/
/** @defgroup LPC_Types_Public_Macros LPC Public Macros
* @{
*/
/* _BIT(n) sets the bit at position "n"
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*/
#undef _BIT
/* Set bit macro */
#define _BIT(n) (1 << (n))
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*/
#undef _SBF
/* Set bit field macro */
#define _SBF(f, v) ((v) << (f))
/* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*/
#undef _BITMASK
/* Bitmask creation macro */
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
/* NULL pointer */
#ifndef NULL
#define NULL ((void *) 0)
#endif
/* Number of elements in an array */
#define NELEMENTS(array) (sizeof(array) / sizeof(array[0]))
/* Static data/function define */
#define STATIC static
/* External data/function define */
#define EXTERN extern
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
/**
* @}
*/
/* Old Type Definition compatibility */
/** @addtogroup LPC_Types_Public_Types
* @{
*/
/** LPC type for character type */
typedef char CHAR;
/** LPC type for 8 bit unsigned value */
typedef uint8_t UNS_8;
/** LPC type for 8 bit signed value */
typedef int8_t INT_8;
/** LPC type for 16 bit unsigned value */
typedef uint16_t UNS_16;
/** LPC type for 16 bit signed value */
typedef int16_t INT_16;
/** LPC type for 32 bit unsigned value */
typedef uint32_t UNS_32;
/** LPC type for 32 bit signed value */
typedef int32_t INT_32;
/** LPC type for 64 bit signed value */
typedef int64_t INT_64;
/** LPC type for 64 bit unsigned value */
typedef uint64_t UNS_64;
#ifdef __CODE_RED
#define BOOL_32 bool
#define BOOL_16 bool
#define BOOL_8 bool
#else
/** 32 bit boolean type */
typedef bool BOOL_32;
/** 16 bit boolean type */
typedef bool BOOL_16;
/** 8 bit boolean type */
typedef bool BOOL_8;
#endif
#ifdef __CC_ARM
#define INLINE __inline
#else
#define INLINE inline
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* __LPC_TYPES_H_ */

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/*
* @brief LPC13XX Pin Interrupt and Pattern Match Registers and driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __PININT_13XX_H_
#define __PININT_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup PININT_13XX CHIP: LPC13xx Pin Interrupt and Pattern Match driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
#if defined(CHIP_LPC1347)
/**
* @brief LPC13xx Pin Interrupt and Pattern Match register block structure
*/
typedef struct { /*!< PIN_INT Structure */
__IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */
__IO uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */
__IO uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< Pin Interrupt Status register */
} LPC_PIN_INT_T;
/**
* LPC13xx Pin Interrupt channel values
*/
#define PININTCH0 (1 << 0)
#define PININTCH1 (1 << 1)
#define PININTCH2 (1 << 2)
#define PININTCH3 (1 << 3)
#define PININTCH4 (1 << 4)
#define PININTCH5 (1 << 5)
#define PININTCH6 (1 << 6)
#define PININTCH7 (1 << 7)
#define PININTCH(ch) (1 << (ch))
/**
* @brief Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @return Nothing
* @note This function should be used after the Chip_GPIO_Init() function.
*/
STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {}
/**
* @brief De-Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @return Nothing
*/
STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {}
/**
* @brief Configure the pins as edge sensitive in Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->ISEL &= ~pins;
}
/**
* @brief Configure the pins as level sensitive in Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->ISEL |= pins;
}
/**
* @brief Return current PININT rising edge or high level interrupt enable state
* @param pPININT : The base address of Pin interrupt block
* @return A bifield containing the high edge/level interrupt enables for each
* interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
* For each bit, a 0 means the high edge/level interrupt is disabled, while a 1
* means it's enabled.
*/
STATIC INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PIN_INT_T *pPININT)
{
return pPININT->IENR;
}
/**
* @brief Enable high edge/level PININT interrupts for pins
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins to enable (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->SIENR = pins;
}
/**
* @brief Disable high edge/level PININT interrupts for pins
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins to disable (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_DisableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->CIENR = pins;
}
/**
* @brief Return current PININT falling edge or low level interrupt enable state
* @param pPININT : The base address of Pin interrupt block
* @return A bifield containing the low edge/level interrupt enables for each
* interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
* For each bit, a 0 means the low edge/level interrupt is disabled, while a 1
* means it's enabled.
*/
STATIC INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PIN_INT_T *pPININT)
{
return pPININT->IENF;
}
/**
* @brief Enable low edge/level PININT interrupts for pins
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins to enable (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->SIENF = pins;
}
/**
* @brief Disable low edge/level PININT interrupts for pins
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins to disable (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_DisableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->CIENF = pins;
}
/**
* @brief Return pin states that have a detected latched high edge (RISE) state
* @param pPININT : The base address of Pin interrupt block
* @return PININT states (bit n = high) with a latched rise state detected
*/
STATIC INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PIN_INT_T *pPININT)
{
return pPININT->RISE;
}
/**
* @brief Clears pin states that had a latched high edge (RISE) state
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins with latched states to clear
* @return Nothing
*/
STATIC INLINE void Chip_PININT_ClearRiseStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->RISE = pins;
}
/**
* @brief Return pin states that have a detected latched falling edge (FALL) state
* @param pPININT : The base address of Pin interrupt block
* @return PININT states (bit n = high) with a latched rise state detected
*/
STATIC INLINE uint32_t Chip_PININT_GetFallStates(LPC_PIN_INT_T *pPININT)
{
return pPININT->FALL;
}
/**
* @brief Clears pin states that had a latched falling edge (FALL) state
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins with latched states to clear
* @return Nothing
*/
STATIC INLINE void Chip_PININT_ClearFallStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->FALL = pins;
}
/**
* @brief Get interrupt status from Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @return Interrupt status (bit n for PININTn = high means interrupt ie pending)
*/
STATIC INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PIN_INT_T *pPININT)
{
return pPININT->IST;
}
/**
* @brief Clear interrupt status in Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pin interrupts to clear (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_ClearIntStatus(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->IST = pins;
}
#endif /* if defined(CHIP_LPC1347) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __PININT_13XX_H_ */

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/*
* @brief LPC13xx PMU chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __PMU_13XX_H_
#define __PMU_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup PMU_13XX CHIP: LPC13xx Power Management Unit block driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief LPC13xx Power Management Unit register block structure
*/
typedef struct {
__IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
__IO uint32_t GPREG[4]; /*!< Offset: 0x004 General purpose Registers 0..3 (R/W) */
__IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
} LPC_PMU_T;
/**
* @brief LPC13xx low power mode type definitions
*/
typedef enum CHIP_PMU_MCUPOWER {
PMU_MCU_SLEEP = 0, /*!< Sleep mode */
PMU_MCU_DEEP_SLEEP, /*!< Deep Sleep mode */
#if defined(CHIP_LPC1347)
PMU_MCU_POWER_DOWN, /*!< Power down mode */
#endif
PMU_MCU_DEEP_PWRDOWN /*!< Deep power down mode */
} CHIP_PMU_MCUPOWER_T;
/**
* PMU PCON register bit fields & masks
*/
#define PMU_PCON_PM_SLEEP (0x0) /*!< ARM WFI enter sleep mode */
#if defined(CHIP_LPC1347)
#define PMU_PCON_PM_DEEPSLEEP (0x1) /*!< ARM WFI enter Deep-sleep mode */
#define PMU_PCON_PM_POWERDOWN (0x2) /*!< ARM WFI enter Power-down mode */
#define PMU_PCON_PM_DEEPPOWERDOWN (0x3) /*!< ARM WFI enter Deep Power-down mode */
#elif defined(CHIP_LPC1343)
#define PMU_PCON_PM_DEEPPOWERDOWN (0x2) /*!< ARM WFI enter Deep Power-down mode */
#endif
#define PMU_PCON_NODPD (1 << 3) /*!< Disable deep power-down mode */
#define PMU_PCON_SLEEPFLAG (1 << 8) /*!< Sleep mode flag */
#define PMU_PCON_DPDFLAG (1 << 11) /*!< Deep power-down flag */
/**
* PMU DPDCTRL register bit fields & masks
*/
#define PMU_DPDCTRL_WAKEUPPHYS (1 << 10) /** Enable wake-up pin hysteresis */
/**
* @brief Write a value to a GPREG register
* @param pPMU : Pointer to PMU register block
* @param regIndex : Register index to write to, must be 0..3
* @param value : Value to write
* @return None
*/
STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value)
{
pPMU->GPREG[regIndex] = value;
}
/**
* @brief Read a value to a GPREG register
* @param pPMU : Pointer to PMU register block
* @param regIndex : Register index to read from, must be 0..3
* @return Value read from the GPREG register
*/
STATIC INLINE uint32_t Chip_PMU_ReadGPREG(LPC_PMU_T *pPMU, uint8_t regIndex)
{
return pPMU->GPREG[regIndex];
}
/**
* @brief Enter MCU Sleep mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note The sleep mode affects the ARM Cortex-M0+ core only. Peripherals
* and memories are active.
*/
void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
/**
* @brief Enter MCU Deep Sleep mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note In Deep-sleep mode, the peripherals receive no internal clocks.
* The flash is in stand-by mode. The SRAM memory and all peripheral registers
* as well as the processor maintain their internal states. The WWDT, WKT,
* and BOD can remain active to wake up the system on an interrupt.
*/
void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU);
/**
* @brief Enter MCU Power down mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note In Power-down mode, the peripherals receive no internal clocks.
* The internal SRAM memory and all peripheral registers as well as the
* processor maintain their internal states. The flash memory is powered
* down. The WWDT, WKT, and BOD can remain active to wake up the system
* on an interrupt.
*/
#if defined(CHIP_LPC1347)
void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU);
#endif
/**
* @brief Enter MCU Deep Power down mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note For maximal power savings, the entire system is shut down
* except for the general purpose registers in the PMU and the self
* wake-up timer. Only the general purpose registers in the PMU maintain
* their internal states. The part can wake up on a pulse on the WAKEUP
* pin or when the self wake-up timer times out. On wake-up, the part
* reboots.
*/
void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU);
/**
* @brief Place the MCU in a low power state
* @param pPMU : Pointer to PMU register block
* @param SleepMode : Sleep mode
* @return None
*/
void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
/**
* @brief Disables deep power-down mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note Calling this functions prevents entry to Deep power-down
* mode. Once set, this can only be cleared by power-on reset.
*/
STATIC INLINE void Chip_PMU_DisableDeepPowerDown(LPC_PMU_T *pPMU)
{
pPMU->PCON |= PMU_PCON_NODPD;
}
/**
* @brief Returns sleep/power-down flags
* @param pPMU : Pointer to PMU register block
* @return Or'ed values of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
* @note These indicate that the PMU is setup for entry into a low
* power state on the next WFI() instruction.
*/
STATIC INLINE uint32_t Chip_PMU_GetSleepFlags(LPC_PMU_T *pPMU)
{
return pPMU->PCON & (PMU_PCON_SLEEPFLAG | PMU_PCON_DPDFLAG);
}
/**
* @brief Clears sleep/power-down flags
* @param pPMU : Pointer to PMU register block
* @param flags : Or'ed value of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
* @return Nothing
* @note Use this function to clear a low power state prior to calling
* WFI().
*/
STATIC INLINE void Chip_PMU_ClearSleepFlags(LPC_PMU_T *pPMU, uint32_t flags)
{
pPMU->PCON &= ~flags;
}
/**
* @brief Sets deep power-down functions
* @param pPMU : Pointer to PMU register block
* @param flags : Or'ed value of PMU_DPDCTRL_* values
* @return Nothing
* @note Some of these functions may need to be set prior to going
* into a low power mode. Note that some calls to this function enable
* functions while others disable it based on the PMU_DPDCTRL_*
* definitions.
*/
STATIC INLINE void Chip_PMU_SetPowerDownControl(LPC_PMU_T *pPMU, uint32_t flags)
{
pPMU->DPDCTRL |= flags;
}
/**
* @brief Cleats deep power-down functions
* @param pPMU : Pointer to PMU register block
* @param flags : Or'ed value of PMU_DPDCTRL_* values
* @return Nothing
* @note Some of these functions may need to be cleared prior to going
* into a low power mode. Note that some calls to this function enable
* functions while others disable it based on the PMU_DPDCTRL_*
* definitions.
*/
STATIC INLINE void Chip_PMU_ClearPowerDownControl(LPC_PMU_T *pPMU, uint32_t flags)
{
pPMU->DPDCTRL &= ~flags;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __PMU_13XX_H_ */

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/*
* @brief Common ring buffer support functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __RING_BUFFER_H_
#define __RING_BUFFER_H_
#include "lpc_types.h"
/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation
* @ingroup CHIP_Common
* @{
*/
/**
* @brief Ring buffer structure
*/
typedef struct {
void *data;
int count;
int itemSz;
uint32_t head;
uint32_t tail;
} RINGBUFF_T;
/**
* @def RB_VHEAD(rb)
* volatile typecasted head index
*/
#define RB_VHEAD(rb) (*(volatile uint32_t *) &(rb)->head)
/**
* @def RB_VTAIL(rb)
* volatile typecasted tail index
*/
#define RB_VTAIL(rb) (*(volatile uint32_t *) &(rb)->tail)
/**
* @brief Initialize ring buffer
* @param RingBuff : Pointer to ring buffer to initialize
* @param buffer : Pointer to buffer to associate with RingBuff
* @param itemSize : Size of each buffer item size
* @param count : Size of ring buffer
* @note Memory pointed by @a buffer must have correct alignment of
* @a itemSize, and @a count must be a power of 2 and must at
* least be 2 or greater.
* @return Nothing
*/
int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count);
/**
* @brief Resets the ring buffer to empty
* @param RingBuff : Pointer to ring buffer
* @return Nothing
*/
STATIC INLINE void RingBuffer_Flush(RINGBUFF_T *RingBuff)
{
RingBuff->head = RingBuff->tail = 0;
}
/**
* @brief Return size the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Size of the ring buffer in bytes
*/
STATIC INLINE int RingBuffer_GetSize(RINGBUFF_T *RingBuff)
{
return RingBuff->count;
}
/**
* @brief Return number of items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Number of items in the ring buffer
*/
STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff)
{
return RB_VHEAD(RingBuff) - RB_VTAIL(RingBuff);
}
/**
* @brief Return number of free items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Number of free items in the ring buffer
*/
STATIC INLINE int RingBuffer_GetFree(RINGBUFF_T *RingBuff)
{
return RingBuff->count - RingBuffer_GetCount(RingBuff);
}
/**
* @brief Return number of items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return 1 if the ring buffer is full, otherwise 0
*/
STATIC INLINE int RingBuffer_IsFull(RINGBUFF_T *RingBuff)
{
return (RingBuffer_GetCount(RingBuff) >= RingBuff->count);
}
/**
* @brief Return empty status of ring buffer
* @param RingBuff : Pointer to ring buffer
* @return 1 if the ring buffer is empty, otherwise 0
*/
STATIC INLINE int RingBuffer_IsEmpty(RINGBUFF_T *RingBuff)
{
return RB_VHEAD(RingBuff) == RB_VTAIL(RingBuff);
}
/**
* @brief Insert a single item into ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : pointer to item
* @return 1 when successfully inserted,
* 0 on error (Buffer not initialized using
* RingBuffer_Init() or attempted to insert
* when buffer is full)
*/
int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data);
/**
* @brief Insert an array of items into ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to first element of the item array
* @param num : Number of items in the array
* @return number of items successfully inserted,
* 0 on error (Buffer not initialized using
* RingBuffer_Init() or attempted to insert
* when buffer is full)
*/
int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num);
/**
* @brief Pop an item from the ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to memory where popped item be stored
* @return 1 when item popped successfuly onto @a data,
* 0 When error (Buffer not initialized using
* RingBuffer_Init() or attempted to pop item when
* the buffer is empty)
*/
int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data);
/**
* @brief Pop an array of items from the ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to memory where popped items be stored
* @param num : Max number of items array @a data can hold
* @return Number of items popped onto @a data,
* 0 on error (Buffer not initialized using RingBuffer_Init()
* or attempted to pop when the buffer is empty)
*/
int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num);
/**
* @}
*/
#endif /* __RING_BUFFER_H_ */

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/*
* @brief LPC13xx RITimer chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __RITIMER_13XX_H_
#define __RITIMER_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup RIT_13XX CHIP: LPC13xx Repetitive Interrupt Timer driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
#if defined(CHIP_LPC1347)
/**
* @brief Repetitive Interrupt Timer register block structure
*/
typedef struct { /*!< RITIMER Structure */
__IO uint32_t COMPVAL; /*!< Compare register */
__IO uint32_t MASK; /*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
__IO uint32_t CTRL; /*!< Control register. */
__IO uint32_t COUNTER; /*!< 32-bit counter */
__IO uint32_t COMPVAL_H; /*!< Compare upper register */
__IO uint32_t MASK_H; /*!< Mask upper register */
__I uint32_t RESERVED0[1];
__IO uint32_t COUNTER_H; /*!< Counter upper register */
} LPC_RITIMER_T;
/*
* @brief RITIMER register support bitfields and mask
*/
/*
* RIT control register
*/
/** Set by H/W when the counter value equals the masked compare value */
#define RIT_CTRL_INT ((uint32_t) (1))
/** Set timer enable clear to 0 when the counter value equals the masked compare value */
#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))
/** Set timer enable on debug */
#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))
/** Set timer enable */
#define RIT_CTRL_TEN ((uint32_t) _BIT(3))
/**
* @brief Initialize the RIT
* @param pRITimer : RITimer peripheral selected
* @return None
*/
void Chip_RIT_Init(LPC_RITIMER_T *pRITimer);
/**
* @brief Shutdown the RIT
* @param pRITimer : RITimer peripheral selected
* @return None
*/
void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer);
/**
* @brief Enable Timer
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL |= RIT_CTRL_TEN;
}
/**
* @brief Disable Timer
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL &= ~RIT_CTRL_TEN;
}
/**
* @brief Enable timer debug
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_TimerDebugEnable(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL |= RIT_CTRL_ENBR;
}
/**
* @brief Disable timer debug
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_TimerDebugDisable(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL &= ~RIT_CTRL_ENBR;
}
/**
* @brief Check whether interrupt flag is set or not
* @param pRITimer : RITimer peripheral selected
* @return Current interrupt status, either ET or UNSET
*/
IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer);
/**
* @brief Set a tick value for the interrupt to time out
* @param pRITimer : RITimer peripheral selected
* @param val : value (in ticks) of the interrupt to be set
* @return None
*/
STATIC INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val)
{
pRITimer->COMPVAL = val;
}
/**
* @brief Enables or clears the RIT or interrupt
* @param pRITimer : RITimer peripheral selected
* @param val : RIT to be set, one or more RIT_CTRL_* values
* @return None
*/
STATIC INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val)
{
pRITimer->CTRL |= val;
}
/**
* @brief Clears the RIT interrupt
* @param pRITimer : RITimer peripheral selected
* @return None
*/
STATIC INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer)
{
pRITimer->CTRL |= RIT_CTRL_INT;
}
/**
* @brief Returns the current RIT Counter value
* @param pRITimer : RITimer peripheral selected
* @return the current timer counter value
*/
STATIC INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer)
{
return pRITimer->COUNTER;
}
/**
* @brief Set timer interval value
* @param pRITimer : RITimer peripheral selected
* @param time_interval : timer interval value (ms)
* @return None
*/
void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval);
#endif /* defined(CHIP_LPC1347) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __RITIMER_13XX_H_ */

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/*
* @brief LPC13XX ROM API declarations and functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __ROMAPI_13XX_H_
#define __ROMAPI_13XX_H_
#include "error.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup ROMAPI_13XX CHIP: LPC13xx ROM API declarations and functions
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief LPC13XX High level ROM API structure
*/
typedef struct {
const uint32_t usbdApiBase; /*!< USBD API function table base address */
const uint32_t reserved0; /*!< Reserved */
const uint32_t candApiBase; /*!< CAN API function table base address */
const uint32_t pwrApiBase; /*!< Power API function table base address */
const uint32_t reserved1; /*!< Reserved */
const uint32_t reserved2; /*!< Reserved */
const uint32_t reserved3; /*!< Reserved */
const uint32_t reserved4; /*!< Reserved */
} LPC_ROM_API_T;
/**
* @brief LPC13XX IAP_ENTRY API function type
*/
typedef void (*IAP_ENTRY_T)(unsigned int[], unsigned int[]);
static INLINE void iap_entry(unsigned int cmd_param[], unsigned int status_result[])
{
((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ROMAPI_13XX_H_ */

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/*
* @brief LPC13xx SSP Registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SSP_13XX_H_
#define __SSP_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SSP_13XX CHIP: LPC13xx SSP register block and driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief SSP register block structure
*/
typedef struct { /*!< SSPn Structure */
__IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< Status Register */
__IO uint32_t CPSR; /*!< Clock Prescale Register */
__IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< Raw Interrupt Status Register */
__I uint32_t MIS; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
!defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
__IO uint32_t DMACR; /*!< SSPn DMA control register */
#endif
} LPC_SSP_T;
/**
* Macro defines for CR0 register
*/
/** SSP data size select, must be 4 bits to 16 bits */
#define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
/** SSP control 0 Motorola SPI mode */
#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
/** SSP control 0 TI synchronous serial mode */
#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
/** SSP control 0 National Micro-wire mode */
#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
bus clock high between frames, (0) = low */
#define SSP_CR0_CPOL_LO ((uint32_t) (0))
#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
on the second clock transition of the frame, (0) = first */
#define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
/**
* Macro defines for CR1 register
*/
/** SSP control 1 loopback mode enable bit */
#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
/** SSP control 1 enable bit */
#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
/** SSP control 1 slave enable */
#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
#define SSP_CR1_MASTER_EN ((uint32_t) (0))
/** SSP control 1 slave out disable bit, disables transmit line in slave
mode */
#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
/** SSP CR1 bit mask */
#define SSP_CR1_BITMASK ((uint32_t) (0x0F))
/** SSP CPSR bit mask */
#define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
/**
* Macro defines for DR register
*/
/** SSP data bit mask */
#define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
/**
* Macro defines for SR register
*/
/** SSP SR bit mask */
#define SSP_SR_BITMASK ((uint32_t) (0x1F))
/** ICR bit mask */
#define SSP_ICR_BITMASK ((uint32_t) (0x03))
/**
* @brief SSP Type of Status
*/
typedef enum _SSP_STATUS {
SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
} SSP_STATUS_T;
/**
* @brief SSP Type of Interrupt Mask
*/
typedef enum _SSP_INTMASK {
SSP_RORIM = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
} SSP_INTMASK_T;
/**
* @brief SSP Type of Mask Interrupt Status
*/
typedef enum _SSP_MASKINTSTATUS {
SSP_RORMIS = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTMIS = ((uint32_t)(1 << 1)), /**< TimeOut */
SSP_RXMIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
SSP_TXMIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} SSP_MASKINTSTATUS_T;
/**
* @brief SSP Type of Raw Interrupt Status
*/
typedef enum _SSP_RAWINTSTATUS {
SSP_RORRIS = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTRIS = ((uint32_t)(1 << 1)), /**< TimeOut */
SSP_RXRIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
SSP_TXRIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} SSP_RAWINTSTATUS_T;
typedef enum _SSP_INTCLEAR {
SSP_RORIC = 0x0,
SSP_RTIC = 0x1,
SSP_INT_CLEAR_BITMASK = 0x3,
} SSP_INTCLEAR_T;
typedef enum _SSP_DMA {
SSP_DMA_RX = (1u), /**< DMA RX Enable */
SSP_DMA_TX = (1u << 1), /**< DMA TX Enable */
SSP_DMA_BITMASK = ((uint32_t)(0x3)),
} SSP_DMA_T;
/*
* @brief SSP clock format
*/
typedef enum CHIP_SSP_CLOCK_FORMAT {
SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), /**< CPHA = 0, CPOL = 0 */
SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), /**< CPHA = 0, CPOL = 1 */
SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), /**< CPHA = 1, CPOL = 0 */
SSP_CLOCK_CPHA1_CPOL1 = (3u << 6), /**< CPHA = 1, CPOL = 1 */
SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
} CHIP_SSP_CLOCK_MODE_T;
/*
* @brief SSP frame format
*/
typedef enum CHIP_SSP_FRAME_FORMAT {
SSP_FRAMEFORMAT_SPI = (0 << 4), /**< Frame format: SPI */
CHIP_SSP_FRAME_FORMAT_TI = (1u << 4), /**< Frame format: TI SSI */
SSP_FRAMEFORMAT_MICROWIRE = (2u << 4), /**< Frame format: Microwire */
} CHIP_SSP_FRAME_FORMAT_T;
/*
* @brief Number of bits per frame
*/
typedef enum CHIP_SSP_BITS {
SSP_BITS_4 = (3u << 0), /*!< 4 bits/frame */
SSP_BITS_5 = (4u << 0), /*!< 5 bits/frame */
SSP_BITS_6 = (5u << 0), /*!< 6 bits/frame */
SSP_BITS_7 = (6u << 0), /*!< 7 bits/frame */
SSP_BITS_8 = (7u << 0), /*!< 8 bits/frame */
SSP_BITS_9 = (8u << 0), /*!< 9 bits/frame */
SSP_BITS_10 = (9u << 0), /*!< 10 bits/frame */
SSP_BITS_11 = (10u << 0), /*!< 11 bits/frame */
SSP_BITS_12 = (11u << 0), /*!< 12 bits/frame */
SSP_BITS_13 = (12u << 0), /*!< 13 bits/frame */
SSP_BITS_14 = (13u << 0), /*!< 14 bits/frame */
SSP_BITS_15 = (14u << 0), /*!< 15 bits/frame */
SSP_BITS_16 = (15u << 0), /*!< 16 bits/frame */
} CHIP_SSP_BITS_T;
/*
* @brief SSP config format
*/
typedef struct SSP_ConfigFormat {
CHIP_SSP_BITS_T bits; /*!< Format config: bits/frame */
CHIP_SSP_CLOCK_MODE_T clockMode; /*!< Format config: clock phase/polarity */
CHIP_SSP_FRAME_FORMAT_T frameFormat; /*!< Format config: SPI/TI/Microwire */
} SSP_ConfigFormat;
/**
* @brief Enable SSP operation
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
{
pSSP->CR1 |= SSP_CR1_SSP_EN;
}
/**
* @brief Disable SSP operation
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
{
pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}
/**
* @brief Enable loopback mode
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note Serial input is taken from the serial output (MOSI or MISO) rather
* than the serial input pin
*/
STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
{
pSSP->CR1 |= SSP_CR1_LBM_EN;
}
/**
* @brief Disable loopback mode
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note Serial input is taken from the serial output (MOSI or MISO) rather
* than the serial input pin
*/
STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
{
pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
}
/**
* @brief Get the current status of SSP controller
* @param pSSP : The base of SSP peripheral on the chip
* @param Stat : Type of status, should be :
* - SSP_STAT_TFE
* - SSP_STAT_TNF
* - SSP_STAT_RNE
* - SSP_STAT_RFF
* - SSP_STAT_BSY
* @return SSP controller status, SET or RESET
*/
STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, SSP_STATUS_T Stat)
{
return (pSSP->SR & Stat) ? SET : RESET;
}
/**
* @brief Get the masked interrupt status
* @param pSSP : The base of SSP peripheral on the chip
* @return SSP Masked Interrupt Status Register value
* @note The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
*/
STATIC INLINE uint32_t Chip_SSP_GetIntStatus(LPC_SSP_T *pSSP)
{
return pSSP->MIS;
}
/**
* @brief Get the raw interrupt status
* @param pSSP : The base of SSP peripheral on the chip
* @param RawInt : Interrupt condition to be get status, shoud be :
* - SSP_RORRIS
* - SSP_RTRIS
* - SSP_RXRIS
* - SSP_TXRIS
* @return Raw interrupt status corresponding to interrupt condition , SET or RESET
* @note Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
*/
STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus(LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
{
return (pSSP->RIS & RawInt) ? SET : RESET;
}
/**
* @brief Get the number of bits transferred in each frame
* @param pSSP : The base of SSP peripheral on the chip
* @return the number of bits transferred in each frame minus one
* @note The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
*/
STATIC INLINE uint8_t Chip_SSP_GetDataSize(LPC_SSP_T *pSSP)
{
return SSP_CR0_DSS(pSSP->CR0);
}
/**
* @brief Clear the corresponding interrupt condition(s) in the SSP controller
* @param pSSP : The base of SSP peripheral on the chip
* @param IntClear: Type of cleared interrupt, should be :
* - SSP_RORIC
* - SSP_RTIC
* @return Nothing
* @note Software can clear one or more interrupt condition(s) in the SSP controller
*/
STATIC INLINE void Chip_SSP_ClearIntPending(LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
{
pSSP->ICR = IntClear;
}
/**
* @brief Enable interrupt for the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
{
pSSP->IMSC |= SSP_TXIM;
}
/**
* @brief Disable interrupt for the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
{
pSSP->IMSC &= (~SSP_TXIM);
}
/**
* @brief Get received SSP data
* @param pSSP : The base of SSP peripheral on the chip
* @return SSP 16-bit data received
*/
STATIC INLINE uint16_t Chip_SSP_ReceiveFrame(LPC_SSP_T *pSSP)
{
return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
}
/**
* @brief Send SSP 16-bit data
* @param pSSP : The base of SSP peripheral on the chip
* @param tx_data : SSP 16-bit data to be transmited
* @return Nothing
*/
STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
{
pSSP->DR = SSP_DR_BITMASK(tx_data);
}
/**
* @brief Set up output clocks per bit for SSP bus
* @param pSSP : The base of SSP peripheral on the chip
* @param clk_rate fs: The number of prescaler-output clocks per bit on the bus, minus one
* @param prescale : The factor by which the Prescaler divides the SSP peripheral clock PCLK
* @return Nothing
* @note The bit frequency is PCLK / (prescale x[clk_rate+1])
*/
void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
/**
* @brief Set up the SSP frame format
* @param pSSP : The base of SSP peripheral on the chip
* @param bits : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
* @param frameFormat : Frame format, should be :
* - SSP_FRAMEFORMAT_SPI
* - SSP_FRAME_FORMAT_TI
* - SSP_FRAMEFORMAT_MICROWIRE
* @param clockMode : Select Clock polarity and Clock phase, should be :
* - SSP_CLOCK_CPHA0_CPOL0
* - SSP_CLOCK_CPHA0_CPOL1
* - SSP_CLOCK_CPHA1_CPOL0
* - SSP_CLOCK_CPHA1_CPOL1
* @return Nothing
* @note Note: The clockFormat is only used in SPI mode
*/
STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
{
pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
}
/**
* @brief Set the SSP working as master or slave mode
* @param pSSP : The base of SSP peripheral on the chip
* @param mode : Operating mode, should be
* - SSP_MODE_MASTER
* - SSP_MODE_SLAVE
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
{
pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
}
#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
!defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
/**
* @brief Enable DMA for SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_DMA_Enable(LPC_SSP_T *pSSP)
{
pSSP->DMACR |= SSP_DMA_BITMASK;
}
/**
* @brief Disable DMA for SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_DMA_Disable(LPC_SSP_T *pSSP)
{
pSSP->DMACR &= ~SSP_DMA_BITMASK;
}
#endif
/*
* @brief SSP mode
*/
typedef enum CHIP_SSP_MODE {
SSP_MODE_MASTER = (0 << 2), /**< Master mode */
SSP_MODE_SLAVE = (1u << 2), /**< Slave mode */
} CHIP_SSP_MODE_T;
/*
* @brief SPI address
*/
typedef struct {
uint8_t port; /*!< Port Number */
uint8_t pin; /*!< Pin number */
} SPI_Address_t;
/*
* @brief SSP data setup structure
*/
typedef struct {
void *tx_data; /*!< Pointer to transmit data */
uint32_t tx_cnt; /*!< Transmit counter */
void *rx_data; /*!< Pointer to transmit data */
uint32_t rx_cnt; /*!< Receive counter */
uint32_t length; /*!< Length of transfer data */
} Chip_SSP_DATA_SETUP_T;
/** SSP configuration parameter defines */
/** Clock phase control bit */
#define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
/** Clock polarity control bit */
/* There's no bug here!!!
* - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
* That means the active clock is in HI state.
* - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
* high between frames. That means the active clock is in LO state.
*/
#define SSP_CPOL_HI SSP_CR0_CPOL_LO
#define SSP_CPOL_LO SSP_CR0_CPOL_HI
/** SSP master mode enable */
#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
#define SSP_MASTER_MODE SSP_CR1_MASTER_EN
/**
* @brief Clean all data in RX FIFO of SSP
* @param pSSP : The base SSP peripheral on the chip
* @return Nothing
*/
void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
/**
* @brief SSP Interrupt Read/Write with 8-bit frame width
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return SUCCESS or ERROR
*/
Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Interrupt Read/Write with 16-bit frame width
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return SUCCESS or ERROR
*/
Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Polling Read/Write in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. It starts with writing phase and after that,
* a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
* through xf_setup param.
*/
uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Polling Write in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param buffer : Buffer address
* @param buffer_len : Buffer length
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. First, a writing operation will send
* the needed data. After that, a dummy reading operation is generated to clear data buffer
*/
uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
/**
* @brief SSP Polling Read in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param buffer : Buffer address
* @param buffer_len : The length of buffer
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. First, a dummy writing operation is generated
* to clear data buffer. After that, a reading operation will receive the needed data
*/
uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
/**
* @brief Initialize the SSP
* @param pSSP : The base SSP peripheral on the chip
* @return Nothing
*/
void Chip_SSP_Init(LPC_SSP_T *pSSP);
/**
* @brief Deinitialise the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note The SSP controller is disabled
*/
void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
/**
* @brief Set the SSP operating modes, master or slave
* @param pSSP : The base SSP peripheral on the chip
* @param master : 1 to set master, 0 to set slave
* @return Nothing
*/
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
/**
* @brief Set the clock frequency for SSP interface
* @param pSSP : The base SSP peripheral on the chip
* @param bitRate : The SSP bit rate
* @return Nothing
*/
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SSP_13XX_H_ */

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/*
* @brief Common stopwatch support
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __STOPWATCH_H_
#define __STOPWATCH_H_
#include "cmsis.h"
/** @defgroup Stop_Watch CHIP: Stopwatch primitives.
* @ingroup CHIP_Common
* @{
*/
/**
* @brief Initialize stopwatch
* @return Nothing
*/
void StopWatch_Init(void);
/**
* @brief Start a stopwatch
* @return Current cycle count
*/
uint32_t StopWatch_Start(void);
/**
* @brief Returns number of ticks elapsed since stopwatch was started
* @param startTime : Time returned by StopWatch_Start().
* @return Number of ticks elapsed since stopwatch was started
*/
STATIC INLINE uint32_t StopWatch_Elapsed(uint32_t startTime)
{
return StopWatch_Start() - startTime;
}
/**
* @brief Returns number of ticks per second of the stopwatch timer
* @return Number of ticks per second of the stopwatch timer
*/
uint32_t StopWatch_TicksPerSecond(void);
/**
* @brief Converts from stopwatch ticks to mS.
* @param ticks : Duration in ticks to convert to mS.
* @return Number of mS in given number of ticks
*/
uint32_t StopWatch_TicksToMs(uint32_t ticks);
/**
* @brief Converts from stopwatch ticks to uS.
* @param ticks : Duration in ticks to convert to uS.
* @return Number of uS in given number of ticks
*/
uint32_t StopWatch_TicksToUs(uint32_t ticks);
/**
* @brief Converts from mS to stopwatch ticks.
* @param mS : Duration in mS to convert to ticks.
* @return Number of ticks in given number of mS
*/
uint32_t StopWatch_MsToTicks(uint32_t mS);
/**
* @brief Converts from uS to stopwatch ticks.
* @param uS : Duration in uS to convert to ticks.
* @return Number of ticks in given number of uS
*/
uint32_t StopWatch_UsToTicks(uint32_t uS);
/**
* @brief Delays the given number of ticks using stopwatch primitives
* @param ticks : Number of ticks to delay
* @return Nothing
*/
STATIC INLINE void StopWatch_DelayTicks(uint32_t ticks)
{
uint32_t startTime = StopWatch_Start();
while (StopWatch_Elapsed(startTime) < ticks) {}
}
/**
* @brief Delays the given number of mS using stopwatch primitives
* @param mS : Number of mS to delay
* @return Nothing
*/
STATIC INLINE void StopWatch_DelayMs(uint32_t mS)
{
uint32_t ticks = StopWatch_MsToTicks(mS);
uint32_t startTime = StopWatch_Start();
while (StopWatch_Elapsed(startTime) < ticks) {}
}
/**
* @brief Delays the given number of uS using stopwatch primitives
* @param uS : Number of uS to delay
* @return Nothing
*/
STATIC INLINE void StopWatch_DelayUs(uint32_t uS)
{
uint32_t ticks = StopWatch_UsToTicks(uS);
uint32_t startTime = StopWatch_Start();
while (StopWatch_Elapsed(startTime) < ticks) {}
}
/**
* @}
*/
#endif /* __STOPWATCH_H_ */

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/*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SYS_CONFIG_H_
#define __SYS_CONFIG_H_
/* Pick only one. Build for LPC1347 chip family */
#define CHIP_LPC1347
/* The LPC1347 platform code hasn't been tested on a board and it's possble
it may have problems although it builds fine. Enable the ENABLE_UNTESTED_CODE
definition to allow the LPC110x platform to build. */
// #define ENABLE_UNTESTED_CODE
#endif /* __SYS_CONFIG_H_ */

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/*
* @brief LPC13xx System Control registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SYSCTL_13XX_H_
#define __SYSCTL_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SYSCTL_13XX CHIP: LPC13xx System Control block driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
#if defined(CHIP_LPC1343)
/**
* @brief Start state control structure
*/
typedef struct {
__IO uint32_t STARTAPR; /*!< Start logic edge control register */
__IO uint32_t STARTER; /*!< Start logic signal enable register */
__IO uint32_t STARTRSRCLR; /*!< Start logic reset register */
__IO uint32_t STARTSR; /*!< Start logic status register */
} LPC_SYSCTL_STARTST_T;
#endif
/**
* @brief LPC13XX System Control block structure
*/
typedef struct { /*!< SYSCTL Structure */
__IO uint32_t SYSMEMREMAP; /*!< System Memory remap register */
__IO uint32_t PRESETCTRL; /*!< Peripheral reset Control register */
__IO uint32_t SYSPLLCTRL; /*!< System PLL control register */
__I uint32_t SYSPLLSTAT; /*!< System PLL status register */
__IO uint32_t USBPLLCTRL; /*!< USB PLL control register, LPC134x only */
__I uint32_t USBPLLSTAT; /*!< USB PLL status register, LPC134x only */
__I uint32_t RESERVED1[2];
__IO uint32_t SYSOSCCTRL; /*!< System Oscillator control register */
__IO uint32_t WDTOSCCTRL; /*!< Watchdog Oscillator control register */
#if defined(CHIP_LPC1347)
__I uint32_t RESERVED2[2];
#else
__IO uint32_t IRCCTRL; /*!< IRC control register */
__I uint32_t RESERVED2[1];
#endif
__IO uint32_t SYSRSTSTAT; /*!< System Reset Status register */
__I uint32_t RESERVED3[3];
__IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select register */
#if defined(CHIP_LPC1347)
__I uint32_t RESERVED4;
#else
__IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable register*/
#endif
__IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select register, LPC134x only */
#if defined(CHIP_LPC1347)
__I uint32_t RESERVED4A[1];
#else
__IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable register, LPC1342/43 only */
#endif
__I uint32_t RESERVED5[8];
__IO uint32_t MAINCLKSEL; /*!< Main clock source select register */
#if defined(CHIP_LPC1347)
__IO uint32_t RESERVED6;
#else
__IO uint32_t MAINCLKUEN; /*!< Main clock source update enable register */
#endif
__IO uint32_t SYSAHBCLKDIV; /*!< System Clock divider register */
__I uint32_t RESERVED6A;
__IO uint32_t SYSAHBCLKCTRL; /*!< System Clock control register */
__I uint32_t RESERVED7[4];
__IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider register */
__IO uint32_t USARTCLKDIV; /*!< UART clock divider register */
__IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider register */
__I uint32_t RESERVED8[3];
__IO uint32_t TRACECLKDIV; /*!< ARM trace clock divider register */
__IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider register */
__I uint32_t RESERVED9[3];
__IO uint32_t USBCLKSEL; /*!< USB clock source select register, LPC134x only */
#if defined(CHIP_LPC1347)
__I uint32_t RESERVED10;
#else
__IO uint32_t USBCLKUEN; /*!< USB clock source update enable register, LPC1342/43 only */
#endif
__IO uint32_t USBCLKDIV; /*!< USB clock source divider register, LPC134x only */
#if defined(CHIP_LPC1347)
__I uint32_t RESERVED11[4];
#else
__I uint32_t RESERVED11;
__IO uint32_t WDTCLKSEL; /*!< WDT clock source select register, some parts only */
__IO uint32_t WDTCLKUEN; /*!< WDT clock source update enable register, some parts only */
__IO uint32_t WDTCLKDIV; /*!< WDT clock divider register, some parts only */
#endif
__I uint32_t RESERVED13;
__IO uint32_t CLKOUTSEL; /*!< Clock out source select register */
#if defined(CHIP_LPC1347)
__I uint32_t RESERVED12;
#else
__IO uint32_t CLKOUTUEN; /*!< Clock out source update enable register, not on LPC1311/13/42/43 only */
#endif
__IO uint32_t CLKOUTDIV; /*!< Clock out divider register */
__I uint32_t RESERVED14[5];
__I uint32_t PIOPORCAP[2]; /*!< POR captured PIO status registers */
__I uint32_t RESERVED15[18];
__IO uint32_t BODCTRL; /*!< Brown Out Detect register */
__IO uint32_t SYSTCKCAL; /*!< System tick counter calibration register */
#if defined(CHIP_LPC1347)
__I uint32_t RESERVED16[6];
__IO uint32_t IRQLATENCY; /*!< IRQ delay register */
__IO uint32_t NMISRC; /*!< NMI source control register,some parts only */
__IO uint32_t PINTSEL[8]; /*!< GPIO pin interrupt select register 0-7 */
__IO uint32_t USBCLKCTRL; /*!< USB clock control register, LPC134x only */
__I uint32_t USBCLKST; /*!< USB clock status register, LPC134x only */
__I uint32_t RESERVED17[25];
__IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register */
__I uint32_t RESERVED18[3];
__IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register */
__I uint32_t RESERVED19[6];
#else
__I uint32_t RESERVED16[42];
LPC_SYSCTL_STARTST_T STARTLOGIC[2];
__I uint32_t RESERVED17[4];
#endif
__IO uint32_t PDSLEEPCFG; /*!< Power down states in deep sleep mode register */
__IO uint32_t PDWAKECFG; /*!< Power down states in wake up from deep sleep register */
__IO uint32_t PDRUNCFG; /*!< Power configuration register*/
__I uint32_t RESERVED20[110];
__I uint32_t DEVICEID; /*!< Device ID register */
} LPC_SYSCTL_T;
/**
* System memory remap modes used to remap interrupt vectors
*/
typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
REMAP_BOOT_LOADER_MODE, /*!< Interrupt vectors are re-mapped to Boot ROM */
REMAP_USER_RAM_MODE, /*!< Interrupt vectors are re-mapped to Static RAM */
REMAP_USER_FLASH_MODE /*!< Interrupt vectors are not re-mapped and reside in Flash */
} CHIP_SYSCTL_BOOT_MODE_REMAP_T;
/**
* @brief Re-map interrupt vectors
* @param remap : system memory map value
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
{
LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
}
/**
* Peripheral reset identifiers, not available on all devices
*/
typedef enum CHIP_SYSCTL_PERIPH_RESET {
RESET_SSP0, /*!< SSP0 reset control */
RESET_I2C0, /*!< I2C0 reset control */
RESET_SSP1 /*!< SSP1 reset control */
} CHIP_SYSCTL_PERIPH_RESET_T;
/**
* @brief Assert reset for a peripheral
* @param periph : Peripheral to assert reset for
* @return Nothing
* @note The peripheral will stay in reset until reset is de-asserted. Call
* Chip_SYSCTL_DeassertPeriphReset() to de-assert the reset.
*/
STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
}
/**
* @brief De-assert reset for a peripheral
* @param periph : Peripheral to de-assert reset for
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
}
/**
* @brief Resets a peripheral
* @param periph : Peripheral to reset
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
Chip_SYSCTL_AssertPeriphReset(periph);
Chip_SYSCTL_DeassertPeriphReset(periph);
}
/**
* System reset status
*/
#define SYSCTL_RST_POR (1 << 0) /*!< POR reset status */
#define SYSCTL_RST_EXTRST (1 << 1) /*!< External reset status */
#define SYSCTL_RST_WDT (1 << 2) /*!< Watchdog reset status */
#define SYSCTL_RST_BOD (1 << 3) /*!< Brown-out detect reset status */
#define SYSCTL_RST_SYSRST (1 << 4) /*!< software system reset status */
/**
* @brief Get system reset status
* @return An Or'ed value of SYSCTL_RST_*
* @note This function returns the detected reset source(s).
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
{
return LPC_SYSCTL->SYSRSTSTAT;
}
/**
* @brief Clear system reset status
* @param reset : An Or'ed value of SYSCTL_RST_* status to clear
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
{
LPC_SYSCTL->SYSRSTSTAT = reset;
}
/**
* @brief Read POR captured PIO status
* @param index : POR register index, 0 or 1
* @return captured POR PIO status
* @note See the user manual for decoing of these bits.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
{
return LPC_SYSCTL->PIOPORCAP[index];
}
/**
* Brown-out detector reset level
*/
typedef enum CHIP_SYSCTL_BODRSTLVL {
SYSCTL_BODRSTLVL_1_46V, /*!< Brown-out reset at 1.46v */
SYSCTL_BODRSTLVL_2_06V, /*!< Brown-out reset at 2.06v */
SYSCTL_BODRSTLVL_2_35V, /*!< Brown-out reset at 2.35v */
SYSCTL_BODRSTLVL_2_63V, /*!< Brown-out reset at 2.63v */
} CHIP_SYSCTL_BODRSTLVL_T;
/**
* Brown-out detector interrupt level
*/
typedef enum CHIP_SYSCTL_BODRINTVAL {
#if defined(CHIP_LPC1343)
SYSCTL_BODINTVAL_1_69V, /*!< Brown-out interrupt at 1.65v */
#else
SYSCTL_BODINTVAL_RESERVED1,
#endif
SYSCTL_BODINTVAL_2_22V, /*!< Brown-out interrupt at 2.22v */
SYSCTL_BODINTVAL_2_52V, /*!< Brown-out interrupt at 2.52v */
SYSCTL_BODINTVAL_2_80V, /*!< Brown-out interrupt at 2.8v */
} CHIP_SYSCTL_BODRINTVAL_T;
/**
* @brief Set brown-out detection interrupt and reset levels
* @param rstlvl : Brown-out detector reset level
* @param intlvl : Brown-out interrupt level
* @return Nothing
* @note Brown-out detection reset will be disabled upon exiting this function.
* Use Chip_SYSCTL_EnableBODReset() to re-enable.
*/
STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
CHIP_SYSCTL_BODRINTVAL_T intlvl)
{
LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
}
/**
* @brief Enable brown-out detection reset
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
{
LPC_SYSCTL->BODCTRL |= (1 << 4);
}
/**
* @brief Disable brown-out detection reset
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
{
LPC_SYSCTL->BODCTRL &= ~(1 << 4);
}
/**
* @brief Set System tick timer calibration value
* @param sysCalVal : System tick timer calibration value
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
{
LPC_SYSCTL->SYSTCKCAL = sysCalVal;
}
#if defined(CHIP_LPC1347)
/**
* @brief Set System IRQ latency
* @param latency : Latency in clock ticks
* @return Nothing
* @note Sets the IRQ latency, a value between 0 and 255 clocks. Lower
* values allow better latency.
*/
STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
{
LPC_SYSCTL->IRQLATENCY = latency;
}
/**
* @brief Get System IRQ latency
* @return Latency in clock ticks
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
{
return LPC_SYSCTL->IRQLATENCY;
}
/**
* Non-Maskable Interrupt Enable/Disable value
*/
#define SYSCTL_NMISRC_ENABLE ((uint32_t) 1 << 31) /*!< Enable the Non-Maskable Interrupt (NMI) source */
/**
* @brief Set source for non-maskable interrupt (NMI)
* @param intsrc : IRQ number to assign to the NMI
* @return Nothing
* @note The NMI source will be disabled upon exiting this function. use the
* Chip_SYSCTL_EnableNMISource() function to enable the NMI source.
*/
STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
{
LPC_SYSCTL->NMISRC = intsrc;
}
/**
* @brief Enable interrupt used for NMI source
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
{
LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
}
/**
* @brief Disable interrupt used for NMI source
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
{
LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
}
/**
* @brief Setup a pin source for the pin interrupts (0-7)
* @param intno : IRQ number
* @param port : port number 0/1)
* @param pin : pin number (0->23 for GPIO Port 0 and 0->31 for GPIO Port 1)
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
{
LPC_SYSCTL->PINTSEL[intno] = (uint32_t) (port * 24 + pin);
}
/**
* @brief Setup USB clock control
* @param ap_clk : USB need_clock signal control (0 or 1)
* @param pol_clk : USB need_clock polarity for triggering the USB wake-up interrupt (0 or 1)
* @return Nothing
* @note See the USBCLKCTRL register in the user manual for these settings.
*/
STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
{
LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
}
/**
* @brief Returns the status of the USB need_clock signal
* @return true if USB need_clock statis is high, otherwise false
*/
STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
{
return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
}
#endif
#if defined(CHIP_LPC1347)
/**
* @brief Enable PIO start logic for a pin (ERP0)
* @param pin : PIO pin number (0 - 7)
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint32_t pin)
{
LPC_SYSCTL->STARTERP0 |= (1 << pin);
}
/**
* @brief Disable PIO start logic for a pin
* @param pin : PIO pin number (0 - 7)
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint32_t pin)
{
LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
}
/**
* Peripheral interrupt wakeup events
*/
#define SYSCTL_WAKEUP_WWDTINT (1 << 12) /*!< WWDT interrupt wake-up */
#define SYSCTL_WAKEUP_BODINT (1 << 13) /*!< Brown Out Detect (BOD) interrupt wake-up */
#define SYSCTL_WAKEUP_USB_WAKEUP (1 << 19) /*!< USB need_clock signal wake-up, LPC1134x only */
#define SYSCTL_WAKEUP_GPIOINT0 (1 << 20) /*!< GPIO GROUP0 interrupt wake-up */
#define SYSCTL_WAKEUP_GPIOINT1 (1 << 21) /*!< GPIO GROUP1 interrupt wake-up */
/**
* @brief Enables a peripheral's wakeup logic
* @param periphmask : OR'ed values of SYSCTL_WAKEUP_* for wakeup
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
{
LPC_SYSCTL->STARTERP1 |= periphmask;
}
/**
* @brief Disables a peripheral's wakeup logic
* @param periphmask : OR'ed values of SYSCTL_WAKEUP_* for wakeup
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
{
LPC_SYSCTL->STARTERP1 &= ~periphmask;
}
#else /* defined(CHIP_LPC1343) */
/* Macro for Chip_SYSCTL_SetStartPinRising and Chip_SYSCTL_SetStartPinFalling
functions */
#define SYSCTL_STARTST_PIN_BIT(port, pin) (((port) * 12) + pin)
#define SYSCTL_STARTST_PIN_INDEX(port, pin) (SYSCTL_STARTST_PIN_BIT(port, pin) / 32)
#define SYSCTL_STARTST_PIN(port, pin) (1 << (SYSCTL_STARTST_PIN_BIT(port, pin) % 32))
/**
* @brief Set rising edge for PIO start logic (APRP0)
* @param index : register index (0/1)
* @param pins : PIO pin(s) mask for setting rising edge start (see note)
* @return Nothing
* @note Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
* is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
* Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
* Multiple pins can be setup for rising edge start with this function
* by Or'ing together the pin values in the call. For example, the
* following call would enable PIO0_5 and PIO_1_10 as rising edge start
* conditions.<br>
* Chip_SYSCTL_SetStartPinRising(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
*
*/
STATIC INLINE void Chip_SYSCTL_SetStartPinRising(uint8_t index, uint32_t pins)
{
LPC_SYSCTL->STARTLOGIC[index].STARTAPR |= pins;
}
/**
* @brief Set falling edge for PIO start logic (APRP0)
* @param index : register index (0/1)
* @param pins : PIO pin(s) mask for setting falling edge start (see note)
* @return Nothing
* @note Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
* is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
* Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
* Multiple pins can be setup for falling edge start with this function
* by Or'ing together the pin values in the call. For example, the
* following call would enable PIO0_5 and PIO_1_10 as falling edge start
* conditions.<br>
* Chip_SYSCTL_SetStartPinFalling(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
*/
STATIC INLINE void Chip_SYSCTL_SetStartPinFalling(uint8_t index, uint32_t pins)
{
LPC_SYSCTL->STARTLOGIC[index].STARTAPR &= ~pins;
}
/**
* @brief Enables start signal for PIO start logic
* @param index : register index (0/1)
* @param pins : PIO pin(s) mask for enabling start (see note)
* @return Nothing
* @note Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
* is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
* Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
* Multiple pins can be enabled with this function by Or'ing together the pin values
* in the call. For example, the following call would enable PIO0_5 and PIO_1_10 <br>
* Chip_SYSCTL_EnableStartPin(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
*/
STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint8_t index, uint32_t pins)
{
LPC_SYSCTL->STARTLOGIC[index].STARTER |= pins;
}
/**
* @brief Disables start signal for PIO start logic
* @param index : register index (0/1)
* @param pins : PIO pin(s) mask for disabling start (see note)
* @return Nothing
* @note Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
* is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
* Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
* Multiple pins can be disabled with this function by Or'ing together the pin values
* in the call. For example, the following call would disable PIO0_5 and PIO_1_10 <br>
* Chip_SYSCTL_DisableStartPin(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
*/
STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint8_t index, uint32_t pins)
{
LPC_SYSCTL->STARTLOGIC[index].STARTER &= ~pins;
}
/**
* @brief Resets start logic state for PIO start logic
* @param index : register index (0/1)
* @param pins : PIO pin(s) mask for resetting state (see note)
* @return Nothing
* @note Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
* is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
* Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
* Multiple pins can be reset with this function by Or'ing together the pin values
* in the call. For example, the following call would reset start logic signal for PIO0_5 and PIO_1_10 <br>
* Chip_SYSCTL_ResetStartPin(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
*/
STATIC INLINE void Chip_SYSCTL_ResetStartPin(uint8_t index, uint32_t pins)
{
LPC_SYSCTL->STARTLOGIC[index].STARTRSRCLR |= pins;
}
/**
* @brief Returns start logic state for PIO pins
* @return The start status of all PIO pins (STARTSRP0 register)
* @note Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
* is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
* Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
* Use the SYSCTL_STARTST_PIN(port, pin) to mask out status conditions.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetStartPinStatus(uint8_t index)
{
return LPC_SYSCTL->STARTLOGIC[index].STARTSR;
}
#endif
/**
* Deep sleep setup values
*/
#define SYSCTL_DEEPSLP_BOD_PD (1 << 3) /*!< BOD power-down control in Deep-sleep mode, powered down */
#define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator power control in Deep-sleep, powered down */
/**
* @brief Setup deep sleep behaviour for power down
* @param sleepmask : OR'ed values of SYSCTL_DEEPSLP_* values (high to powerdown on deepsleep)
* @return Nothing
* @note This must be setup prior to using deep sleep. See the user manual
* *(PDSLEEPCFG register) for more info on setting this up. This function selects
* which peripherals are powered down on deep sleep.
* This function should only be called once with all options for power-down
* in that call.
*/
void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);
/**
* @brief Returns current deep sleep mask
* @return OR'ed values of SYSCTL_DEEPSLP_* values
* @note A high bit indicates the peripheral will power down on deep sleep.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
{
return LPC_SYSCTL->PDSLEEPCFG;
}
/**
* Deep sleep to wakeup setup values
*/
#define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0) /*!< IRC oscillator output wake-up configuration */
#define SYSCTL_SLPWAKE_IRC_PD (1 << 1) /*!< IRC oscillator power-down wake-up configuration */
#define SYSCTL_SLPWAKE_FLASH_PD (1 << 2) /*!< Flash wake-up configuration */
#define SYSCTL_SLPWAKE_BOD_PD (1 << 3) /*!< BOD wake-up configuration */
#define SYSCTL_SLPWAKE_ADC_PD (1 << 4) /*!< ADC wake-up configuration */
#define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5) /*!< System oscillator wake-up configuration */
#define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator wake-up configuration */
#define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7) /*!< System PLL wake-up configuration */
#define SYSCTL_SLPWAKE_USBPLL_PD (1 << 8) /*!< USB PLL wake-up configuration */
#define SYSCTL_SLPWAKE_USBPAD_PD (1 << 10) /*!< USB transceiver wake-up configuration */
/**
* @brief Setup wakeup behaviour from deep sleep
* @param wakeupmask : OR'ed values of SYSCTL_SLPWAKE_* values (high is powered down)
* @return Nothing
* @note This must be setup prior to using deep sleep. See the user manual
* *(PDWAKECFG register) for more info on setting this up. This function selects
* which peripherals are powered up on exit from deep sleep.
* This function should only be called once with all options for wakeup
* in that call.
*/
void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
/**
* @brief Return current wakeup mask
* @return OR'ed values of SYSCTL_SLPWAKE_* values
* @note A high state indicates the peripehral will powerup on wakeup.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
{
return LPC_SYSCTL->PDWAKECFG;
}
/**
* Power down configuration values
*/
#define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 0) /*!< IRC oscillator output power down */
#define SYSCTL_POWERDOWN_IRC_PD (1 << 1) /*!< IRC oscillator power-down */
#define SYSCTL_POWERDOWN_FLASH_PD (1 << 2) /*!< Flash power down */
#define SYSCTL_POWERDOWN_BOD_PD (1 << 3) /*!< BOD power down */
#define SYSCTL_POWERDOWN_ADC_PD (1 << 4) /*!< ADC power down */
#define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 5) /*!< System oscillator power down */
#define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator power down */
#define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 7) /*!< System PLL power down */
#define SYSCTL_POWERDOWN_USBPLL_PD (1 << 8) /*!< USB PLL power-down */
#define SYSCTL_POWERDOWN_USBPAD_PD (1 << 10)/*!< USB transceiver power-down */
/**
* @brief Power down one or more blocks or peripherals
* @param powerdownmask : OR'ed values of SYSCTL_POWERDOWN_* values
* @return Nothing
*/
void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
/**
* @brief Power up one or more blocks or peripherals
* @param powerupmask : OR'ed values of SYSCTL_POWERDOWN_* values
* @return Nothing
*/
void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
/**
* @brief Get power status
* @return OR'ed values of SYSCTL_POWERDOWN_* values
* @note A high state indicates the peripheral is powered down.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
{
return LPC_SYSCTL->PDRUNCFG;
}
/**
* @brief Return the device ID
* @return the device ID
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
{
return LPC_SYSCTL->DEVICEID;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSCTL_13XX_H_ */

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/*
* @brief LPC13xx 16/32-bit Timer/PWM control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __TIMER_13XX_H_
#define __TIMER_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup TIMER_13XX CHIP: LPC13xx 16/32-bit Timer driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief 32-bit Standard timer register block structure
*/
typedef struct { /*!< TIMERn Structure */
__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
__IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
__IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
__IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
} LPC_TIMER_T;
/** Macro to clear interrupt pending */
#define TIMER_IR_CLR(n) _BIT(n)
/** Macro for getting a timer match interrupt bit */
#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
/** Macro for getting a capture event interrupt bit */
#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
/** Timer/counter enable bit */
#define TIMER_ENABLE ((uint32_t) (1 << 0))
/** Timer/counter reset bit */
#define TIMER_RESET ((uint32_t) (1 << 1))
/** Bit location for interrupt on MRx match, n = 0 to 3 */
#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
/** Bit location for reset on MRx match, n = 0 to 3 */
#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
/** Bit location for stop on MRx match, n = 0 to 3 */
#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
#define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
/**
* @brief Initialize a timer
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
/**
* @brief Shutdown a timer
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
/**
* @brief Determine if a match interrupt is pending
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match interrupt number to check
* @return false if the interrupt is not pending, otherwise true
* @note Determine if the match interrupt for the passed timer and match
* counter is pending.
*/
STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
{
return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
}
/**
* @brief Determine if a capture interrupt is pending
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture interrupt number to check
* @return false if the interrupt is not pending, otherwise true
* @note Determine if the capture interrupt for the passed capture pin is
* pending.
*/
STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
{
return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
}
/**
* @brief Clears a (pending) match interrupt
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match interrupt number to clear
* @return Nothing
* @note Clears a pending timer match interrupt.
*/
STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->IR = TIMER_IR_CLR(matchnum);
}
/**
* @brief Clears a (pending) capture interrupt
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture interrupt number to clear
* @return Nothing
* @note Clears a pending timer capture interrupt.
*/
STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->IR = (0x10 << capnum);
}
/**
* @brief Enables the timer (starts count)
* @param pTMR : Pointer to timer IP register address
* @return Nothing
* @note Enables the timer to start counting.
*/
STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
{
pTMR->TCR |= TIMER_ENABLE;
}
/**
* @brief Disables the timer (stops count)
* @param pTMR : Pointer to timer IP register address
* @return Nothing
* @note Disables the timer to stop counting.
*/
STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
{
pTMR->TCR &= ~TIMER_ENABLE;
}
/**
* @brief Returns the current timer count
* @param pTMR : Pointer to timer IP register address
* @return Current timer terminal count value
* @note Returns the current timer terminal count.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
{
return pTMR->TC;
}
/**
* @brief Returns the current prescale count
* @param pTMR : Pointer to timer IP register address
* @return Current timer prescale count value
* @note Returns the current prescale count.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
{
return pTMR->PC;
}
/**
* @brief Sets the prescaler value
* @param pTMR : Pointer to timer IP register address
* @param prescale : Prescale value to set the prescale register to
* @return Nothing
* @note Sets the prescale count value.
*/
STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
{
pTMR->PR = prescale;
}
/**
* @brief Sets a timer match value
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer to set match count for
* @param matchval : Match value for the selected match count
* @return Nothing
* @note Sets one of the timer match values.
*/
STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
{
pTMR->MR[matchnum] = matchval;
}
/**
* @brief Reads a capture register
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture register to read
* @return The selected capture register value
* @note Returns the selected capture register value.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
return pTMR->CR[capnum];
}
/**
* @brief Resets the timer terminal and prescale counts to 0
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
/**
* @brief Enables a match interrupt that fires when the terminal count
* matches the match counter value.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
}
/**
* @brief Disables a match interrupt for a match counter.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
}
/**
* @brief For the specific match counter, enables reset of the terminal count register when a match occurs
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
}
/**
* @brief For the specific match counter, disables reset of the terminal count register when a match occurs
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
}
/**
* @brief Enable a match timer to stop the terminal count when a
* match count equals the terminal count.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
}
/**
* @brief Disable stop on match for a match timer. Disables a match timer
* to stop the terminal count when a match count equals the terminal count.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
}
/**
* @brief Enables capture on on rising edge of selected CAP signal for the
* selected capture register, enables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a rising edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_CAP_RISING(capnum);
}
/**
* @brief Disables capture on on rising edge of selected CAP signal. For the
* selected capture register, disables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a rising edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_CAP_RISING(capnum);
}
/**
* @brief Enables capture on on falling edge of selected CAP signal. For the
* selected capture register, enables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a falling edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_CAP_FALLING(capnum);
}
/**
* @brief Disables capture on on falling edge of selected CAP signal. For the
* selected capture register, disables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a falling edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_CAP_FALLING(capnum);
}
/**
* @brief Enables interrupt on capture of selected CAP signal. For the
* selected capture register, an interrupt will be generated when the enabled
* rising or falling edge on CAPn.capnum is detected.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_INT_ON_CAP(capnum);
}
/**
* @brief Disables interrupt on capture of selected CAP signal
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum);
}
/**
* @brief Standard timer initial match pin state and change state
*/
typedef enum IP_TIMER_PIN_MATCH_STATE {
TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */
TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */
TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */
TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */
} TIMER_PIN_MATCH_STATE_T;
/**
* @brief Sets external match control (MATn.matchnum) pin control. For the pin
* selected with matchnum, sets the function of the pin that occurs on
* a terminal count match for the match count.
* @param pTMR : Pointer to timer IP register address
* @param initial_state : Initial state of the pin, high(1) or low(0)
* @param matchState : Selects the match state for the pin
* @param matchnum : MATn.matchnum signal to use
* @return Nothing
* @note For the pin selected with matchnum, sets the function of the pin that occurs on
* a terminal count match for the match count.
*/
void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
/**
* @brief Standard timer clock and edge for count source
*/
typedef enum IP_TIMER_CAP_SRC_STATE {
TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */
TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */
TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */
TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */
} TIMER_CAP_SRC_STATE_T;
/**
* @brief Sets timer count source and edge with the selected passed from CapSrc.
* If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
* @param pTMR : Pointer to timer IP register address
* @param capSrc : timer clock source and edge
* @param capnum : CAPn.capnum pin to use (if used)
* @return Nothing
* @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
*/
STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
TIMER_CAP_SRC_STATE_T capSrc,
int8_t capnum)
{
pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __TIMER_13XX_H_ */

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/*
* @brief LPC13xx UART chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __UART_13XX_H_
#define __UART_13XX_H_
#include "ring_buffer.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup UART_13XX CHIP: LPC13xx UART driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
/**
* @brief USART register block structure
*/
typedef struct { /*!< USARTn Structure */
union {
__IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
__O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
__I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
};
union {
__IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
__IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
};
union {
__O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */
__I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */
__I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */
__IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */
__IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
__IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */
__I uint32_t RESERVED1[1];
__IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */
__IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
union {
__IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */
__I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
};
__IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
} LPC_USART_T;
/**
* @brief Macro defines for UART Receive Buffer register
*/
#define UART_RBR_MASKBIT (0xFF) /*!< UART Received Buffer mask bit (8 bits) */
/**
* @brief Macro defines for UART Divisor Latch LSB register
*/
#define UART_LOAD_DLL(div) ((div) & 0xFF) /*!< Macro for loading LSB of divisor */
#define UART_DLL_MASKBIT (0xFF) /*!< Divisor latch LSB bit mask */
/**
* @brief Macro defines for UART Divisor Latch MSB register
*/
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*!< Macro for loading MSB of divisors */
#define UART_DLM_MASKBIT (0xFF) /*!< Divisor latch MSB bit mask */
/**
* @brief Macro defines for UART Interrupt Enable Register
*/
#define UART_IER_RBRINT (1 << 0) /*!< RBR Interrupt enable */
#define UART_IER_THREINT (1 << 1) /*!< THR Interrupt enable */
#define UART_IER_RLSINT (1 << 2) /*!< RX line status interrupt enable */
#define UART_IER_MSINT (1 << 3) /*!< Modem status interrupt enable - valid for 11xx, 17xx/40xx UART1, 18xx/43xx UART1 only */
#define UART_IER_CTSINT (1 << 7) /*!< CTS signal transition interrupt enable - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
#define UART_IER_ABEOINT (1 << 8) /*!< Enables the end of auto-baud interrupt */
#define UART_IER_ABTOINT (1 << 9) /*!< Enables the auto-baud time-out interrupt */
#define UART_IER_BITMASK (0x307) /*!< UART interrupt enable register bit mask - valid for 13xx, 17xx/40xx UART0/2/3, 18xx/43xx UART0/2/3 only*/
#define UART1_IER_BITMASK (0x30F) /*!< UART1 interrupt enable register bit mask - valid for 11xx only */
#define UART2_IER_BITMASK (0x38F) /*!< UART2 interrupt enable register bit mask - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
/**
* @brief Macro defines for UART Interrupt Identification Register
*/
#define UART_IIR_INTSTAT_PEND (1 << 0) /*!< Interrupt pending status - Active low */
#define UART_IIR_FIFO_EN (3 << 6) /*!< These bits are equivalent to FCR[0] */
#define UART_IIR_ABEO_INT (1 << 8) /*!< End of auto-baud interrupt */
#define UART_IIR_ABTO_INT (1 << 9) /*!< Auto-baud time-out interrupt */
#define UART_IIR_BITMASK (0x3CF) /*!< UART interrupt identification register bit mask */
/* Interrupt ID bit definitions */
#define UART_IIR_INTID_MASK (7 << 1) /*!< Interrupt identification: Interrupt ID mask */
#define UART_IIR_INTID_RLS (3 << 1) /*!< Interrupt identification: Receive line interrupt */
#define UART_IIR_INTID_RDA (2 << 1) /*!< Interrupt identification: Receive data available interrupt */
#define UART_IIR_INTID_CTI (6 << 1) /*!< Interrupt identification: Character time-out indicator interrupt */
#define UART_IIR_INTID_THRE (1 << 1) /*!< Interrupt identification: THRE interrupt */
#define UART_IIR_INTID_MODEM (0 << 1) /*!< Interrupt identification: Modem interrupt */
/**
* @brief Macro defines for UART FIFO Control Register
*/
#define UART_FCR_FIFO_EN (1 << 0) /*!< UART FIFO enable */
#define UART_FCR_RX_RS (1 << 1) /*!< UART RX FIFO reset */
#define UART_FCR_TX_RS (1 << 2) /*!< UART TX FIFO reset */
#define UART_FCR_DMAMODE_SEL (1 << 3) /*!< UART DMA mode selection - valid for 17xx/40xx, 18xx/43xx only */
#define UART_FCR_BITMASK (0xCF) /*!< UART FIFO control bit mask */
#define UART_TX_FIFO_SIZE (16)
/* FIFO trigger level bit definitions */
#define UART_FCR_TRG_LEV0 (0) /*!< UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV1 (1 << 6) /*!< UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV2 (2 << 6) /*!< UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV3 (3 << 6) /*!< UART FIFO trigger level 3: 14 character */
/**
* @brief Macro defines for UART Line Control Register
*/
/* UART word length select bit definitions */
#define UART_LCR_WLEN_MASK (3 << 0) /*!< UART word length select bit mask */
#define UART_LCR_WLEN5 (0 << 0) /*!< UART word length select: 5 bit data mode */
#define UART_LCR_WLEN6 (1 << 0) /*!< UART word length select: 6 bit data mode */
#define UART_LCR_WLEN7 (2 << 0) /*!< UART word length select: 7 bit data mode */
#define UART_LCR_WLEN8 (3 << 0) /*!< UART word length select: 8 bit data mode */
/* UART Stop bit select bit definitions */
#define UART_LCR_SBS_MASK (1 << 2) /*!< UART stop bit select: bit mask */
#define UART_LCR_SBS_1BIT (0 << 2) /*!< UART stop bit select: 1 stop bit */
#define UART_LCR_SBS_2BIT (1 << 2) /*!< UART stop bit select: 2 stop bits (in 5 bit data mode, 1.5 stop bits) */
/* UART Parity enable bit definitions */
#define UART_LCR_PARITY_EN (1 << 3) /*!< UART Parity Enable */
#define UART_LCR_PARITY_DIS (0 << 3) /*!< UART Parity Disable */
#define UART_LCR_PARITY_ODD (0 << 4) /*!< UART Parity select: Odd parity */
#define UART_LCR_PARITY_EVEN (1 << 4) /*!< UART Parity select: Even parity */
#define UART_LCR_PARITY_F_1 (2 << 4) /*!< UART Parity select: Forced 1 stick parity */
#define UART_LCR_PARITY_F_0 (3 << 4) /*!< UART Parity select: Forced 0 stick parity */
#define UART_LCR_BREAK_EN (1 << 6) /*!< UART Break transmission enable */
#define UART_LCR_DLAB_EN (1 << 7) /*!< UART Divisor Latches Access bit enable */
#define UART_LCR_BITMASK (0xFF) /*!< UART line control bit mask */
/**
* @brief Macro defines for UART Modem Control Register
*/
#define UART_MCR_DTR_CTRL (1 << 0) /*!< Source for modem output pin DTR */
#define UART_MCR_RTS_CTRL (1 << 1) /*!< Source for modem output pin RTS */
#define UART_MCR_LOOPB_EN (1 << 4) /*!< Loop back mode select */
#define UART_MCR_AUTO_RTS_EN (1 << 6) /*!< Enable Auto RTS flow-control */
#define UART_MCR_AUTO_CTS_EN (1 << 7) /*!< Enable Auto CTS flow-control */
#define UART_MCR_BITMASK (0xD3) /*!< UART bit mask value */
/**
* @brief Macro defines for UART Line Status Register
*/
#define UART_LSR_RDR (1 << 0) /*!< Line status: Receive data ready */
#define UART_LSR_OE (1 << 1) /*!< Line status: Overrun error */
#define UART_LSR_PE (1 << 2) /*!< Line status: Parity error */
#define UART_LSR_FE (1 << 3) /*!< Line status: Framing error */
#define UART_LSR_BI (1 << 4) /*!< Line status: Break interrupt */
#define UART_LSR_THRE (1 << 5) /*!< Line status: Transmit holding register empty */
#define UART_LSR_TEMT (1 << 6) /*!< Line status: Transmitter empty */
#define UART_LSR_RXFE (1 << 7) /*!< Line status: Error in RX FIFO */
#define UART_LSR_TXFE (1 << 8) /*!< Line status: Error in RX FIFO */
#define UART_LSR_BITMASK (0xFF) /*!< UART Line status bit mask */
#define UART1_LSR_BITMASK (0x1FF) /*!< UART1 Line status bit mask - valid for 11xx, 18xx/43xx UART0/2/3 only */
/**
* @brief Macro defines for UART Modem Status Register
*/
#define UART_MSR_DELTA_CTS (1 << 0) /*!< Modem status: State change of input CTS */
#define UART_MSR_DELTA_DSR (1 << 1) /*!< Modem status: State change of input DSR */
#define UART_MSR_LO2HI_RI (1 << 2) /*!< Modem status: Low to high transition of input RI */
#define UART_MSR_DELTA_DCD (1 << 3) /*!< Modem status: State change of input DCD */
#define UART_MSR_CTS (1 << 4) /*!< Modem status: Clear To Send State */
#define UART_MSR_DSR (1 << 5) /*!< Modem status: Data Set Ready State */
#define UART_MSR_RI (1 << 6) /*!< Modem status: Ring Indicator State */
#define UART_MSR_DCD (1 << 7) /*!< Modem status: Data Carrier Detect State */
#define UART_MSR_BITMASK (0xFF) /*!< Modem status: MSR register bit-mask value */
/**
* @brief Macro defines for UART Auto baudrate control register
*/
#define UART_ACR_START (1 << 0) /*!< UART Auto-baud start */
#define UART_ACR_MODE (1 << 1) /*!< UART Auto baudrate Mode 1 */
#define UART_ACR_AUTO_RESTART (1 << 2) /*!< UART Auto baudrate restart */
#define UART_ACR_ABEOINT_CLR (1 << 8) /*!< UART End of auto-baud interrupt clear */
#define UART_ACR_ABTOINT_CLR (1 << 9) /*!< UART Auto-baud time-out interrupt clear */
#define UART_ACR_BITMASK (0x307) /*!< UART Auto Baudrate register bit mask */
/**
* @brief Macro defines for UART RS485 Control register
*/
#define UART_RS485CTRL_NMM_EN (1 << 0) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
#define UART_RS485CTRL_RX_DIS (1 << 1) /*!< The receiver is disabled */
#define UART_RS485CTRL_AADEN (1 << 2) /*!< Auto Address Detect (AAD) is enabled */
#define UART_RS485CTRL_SEL_DTR (1 << 3) /*!< If direction control is enabled (bit DCTRL = 1), pin DTR is
used for direction control */
#define UART_RS485CTRL_DCTRL_EN (1 << 4) /*!< Enable Auto Direction Control */
#define UART_RS485CTRL_OINV_1 (1 << 5) /*!< This bit reverses the polarity of the direction
control signal on the RTS (or DTR) pin. The direction control pin
will be driven to logic "1" when the transmitter has data to be sent */
#define UART_RS485CTRL_BITMASK (0x3F) /*!< RS485 control bit-mask value */
/**
* @brief Macro defines for UART IrDA Control Register - valid for 11xx, 17xx/40xx UART0/2/3, 18xx/43xx UART3 only
*/
#define UART_ICR_IRDAEN (1 << 0) /*!< IrDA mode enable */
#define UART_ICR_IRDAINV (1 << 1) /*!< IrDA serial input inverted */
#define UART_ICR_FIXPULSE_EN (1 << 2) /*!< IrDA fixed pulse width mode */
#define UART_ICR_PULSEDIV(n) ((n & 0x07) << 3) /*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_BITMASK (0x3F) /*!< UART IRDA bit mask */
/**
* @brief Macro defines for UART half duplex register - ????
*/
#define UART_HDEN_HDEN ((1 << 0)) /*!< enable half-duplex mode*/
/**
* @brief Macro defines for UART Smart card interface Control Register - valid for 11xx, 18xx/43xx UART0/2/3 only
*/
#define UART_SCICTRL_SCIEN (1 << 0) /*!< enable asynchronous half-duplex smart card interface*/
#define UART_SCICTRL_NACKDIS (1 << 1) /*!< NACK response is inhibited*/
#define UART_SCICTRL_PROTSEL_T1 (1 << 2) /*!< ISO7816-3 protocol T1 is selected*/
#define UART_SCICTRL_TXRETRY(n) ((n & 0x07) << 5) /*!< number of retransmission*/
#define UART_SCICTRL_GUARDTIME(n) ((n & 0xFF) << 8) /*!< Extra guard time*/
/**
* @brief Macro defines for UART Fractional Divider Register
*/
#define UART_FDR_DIVADDVAL(n) (n & 0x0F) /*!< Baud-rate generation pre-scaler divisor */
#define UART_FDR_MULVAL(n) ((n << 4) & 0xF0) /*!< Baud-rate pre-scaler multiplier value */
#define UART_FDR_BITMASK (0xFF) /*!< UART Fractional Divider register bit mask */
/**
* @brief Macro defines for UART Tx Enable Register
*/
#define UART_TER1_TXEN (1 << 7) /*!< Transmit enable bit - valid for 11xx, 13xx, 17xx/40xx only */
#define UART_TER2_TXEN (1 << 0) /*!< Transmit enable bit - valid for 18xx/43xx only */
/**
* @brief Macro defines for UART Synchronous Control Register - 11xx, 18xx/43xx UART0/2/3 only
*/
#define UART_SYNCCTRL_SYNC (1 << 0) /*!< enable synchronous mode*/
#define UART_SYNCCTRL_CSRC_MASTER (1 << 1) /*!< synchronous master mode*/
#define UART_SYNCCTRL_FES (1 << 2) /*!< sample on falling edge*/
#define UART_SYNCCTRL_TSBYPASS (1 << 3) /*!< to be defined*/
#define UART_SYNCCTRL_CSCEN (1 << 4) /*!< Continuous running clock enable (master mode only)*/
#define UART_SYNCCTRL_STARTSTOPDISABLE (1 << 5) /*!< Do not send start/stop bit*/
#define UART_SYNCCTRL_CCCLR (1 << 6) /*!< stop continuous clock*/
/**
* @brief Enable transmission on UART TxD pin
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_TXEnable(LPC_USART_T *pUART)
{
pUART->TER1 = UART_TER1_TXEN;
}
/**
* @brief Disable transmission on UART TxD pin
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_TXDisable(LPC_USART_T *pUART)
{
pUART->TER1 = 0;
}
/**
* @brief Transmit a single data byte through the UART peripheral
* @param pUART : Pointer to selected UART peripheral
* @param data : Byte to transmit
* @return Nothing
* @note This function attempts to place a byte into the UART transmit
* FIFO or transmit hold register regard regardless of UART state
*/
STATIC INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data)
{
pUART->THR = (uint32_t) data;
}
/**
* @brief Read a single byte data from the UART peripheral
* @param pUART : Pointer to selected UART peripheral
* @return A single byte of data read
* @note This function reads a byte from the UART receive FIFO or
* receive hold register regard regardless of UART state. The
* FIFO status should be read first prior to using this function
*/
STATIC INLINE uint8_t Chip_UART_ReadByte(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
}
/**
* @brief Enable UART interrupts
* @param pUART : Pointer to selected UART peripheral
* @param intMask : OR'ed Interrupts to enable in the Interrupt Enable Register (IER)
* @return Nothing
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to enable specific UART interrupts. The Divisor Latch Access Bit
* (DLAB) in LCR must be cleared in order to access the IER register.
* This function doesn't alter the DLAB state
*/
STATIC INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask)
{
pUART->IER |= intMask;
}
/**
* @brief Disable UART interrupts
* @param pUART : Pointer to selected UART peripheral
* @param intMask : OR'ed Interrupts to disable in the Interrupt Enable Register (IER)
* @return Nothing
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to disable specific UART interrupts. The Divisor Latch Access Bit
* (DLAB) in LCR must be cleared in order to access the IER register.
* This function doesn't alter the DLAB state
*/
STATIC INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask)
{
pUART->IER &= ~intMask;
}
/**
* @brief Returns UART interrupts that are enabled
* @param pUART : Pointer to selected UART peripheral
* @return Returns the enabled UART interrupts
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to determine which interrupts are enabled. You can check
* for multiple enabled bits if needed.
*/
STATIC INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART)
{
return pUART->IER;
}
/**
* @brief Read the Interrupt Identification Register (IIR)
* @param pUART : Pointer to selected UART peripheral
* @return Current pending interrupt status per the IIR register
*/
STATIC INLINE uint32_t Chip_UART_ReadIntIDReg(LPC_USART_T *pUART)
{
return pUART->IIR;
}
/**
* @brief Setup the UART FIFOs
* @param pUART : Pointer to selected UART peripheral
* @param fcr : FIFO control register setup OR'ed flags
* @return Nothing
* @note Use OR'ed value of UART_FCR_* definitions with this function
* to select specific options. For example, to enable the FIFOs
* with a RX trip level of 8 characters, use something like
* (UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2)
*/
STATIC INLINE void Chip_UART_SetupFIFOS(LPC_USART_T *pUART, uint32_t fcr)
{
pUART->FCR = fcr;
}
/**
* @brief Configure data width, parity and stop bits
* @param pUART : Pointer to selected pUART peripheral
* @param config : UART configuration, OR'ed values of UART_LCR_* defines
* @return Nothing
* @note Select OR'ed config options for the UART from the UART_LCR_*
* definitions. For example, a configuration of 8 data bits, 1
* stop bit, and even (enabled) parity would be
* (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_EN | UART_LCR_PARITY_EVEN)
*/
STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config)
{
pUART->LCR = config;
}
/**
* @brief Enable access to Divisor Latches
* @param pUART : Pointer to selected UART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_EnableDivisorAccess(LPC_USART_T *pUART)
{
pUART->LCR |= UART_LCR_DLAB_EN;
}
/**
* @brief Disable access to Divisor Latches
* @param pUART : Pointer to selected UART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_DisableDivisorAccess(LPC_USART_T *pUART)
{
pUART->LCR &= ~UART_LCR_DLAB_EN;
}
/**
* @brief Set LSB and MSB divisor latch registers
* @param pUART : Pointer to selected UART peripheral
* @param dll : Divisor Latch LSB value
* @param dlm : Divisor Latch MSB value
* @return Nothing
* @note The Divisor Latch Access Bit (DLAB) in LCR must be set in
* order to access the USART Divisor Latches. This function
* doesn't alter the DLAB state.
*/
STATIC INLINE void Chip_UART_SetDivisorLatches(LPC_USART_T *pUART, uint8_t dll, uint8_t dlm)
{
pUART->DLL = (uint32_t) dll;
pUART->DLM = (uint32_t) dlm;
}
/**
* @brief Return modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @return Modem control register (status)
* @note Mask bits of the returned status value with UART_MCR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadModemControl(LPC_USART_T *pUART)
{
return pUART->MCR;
}
/**
* @brief Set modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @param mcr : Modem control register flags to set
* @return Nothing
* @note Use an Or'ed value of UART_MCR_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetModemControl(LPC_USART_T *pUART, uint32_t mcr)
{
pUART->MCR |= mcr;
}
/**
* @brief Clear modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @param mcr : Modem control register flags to clear
* @return Nothing
* @note Use an Or'ed value of UART_MCR_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearModemControl(LPC_USART_T *pUART, uint32_t mcr)
{
pUART->MCR &= ~mcr;
}
/**
* @brief Return Line Status register/status (LSR)
* @param pUART : Pointer to selected UART peripheral
* @return Line Status register (status)
* @note Mask bits of the returned status value with UART_LSR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadLineStatus(LPC_USART_T *pUART)
{
return pUART->LSR;
}
/**
* @brief Return Modem Status register/status (MSR)
* @param pUART : Pointer to selected UART peripheral
* @return Modem Status register (status)
* @note Mask bits of the returned status value with UART_MSR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadModemStatus(LPC_USART_T *pUART)
{
return pUART->MSR;
}
/**
* @brief Write a byte to the scratchpad register
* @param pUART : Pointer to selected UART peripheral
* @param data : Byte value to write
* @return Nothing
*/
STATIC INLINE void Chip_UART_SetScratch(LPC_USART_T *pUART, uint8_t data)
{
pUART->SCR = (uint32_t) data;
}
/**
* @brief Returns current byte value in the scratchpad register
* @param pUART : Pointer to selected UART peripheral
* @return Byte value read from scratchpad register
*/
STATIC INLINE uint8_t Chip_UART_ReadScratch(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->SCR & 0xFF);
}
/**
* @brief Set autobaud register options
* @param pUART : Pointer to selected UART peripheral
* @param acr : Or'ed values to set for ACR register
* @return Nothing
* @note Use an Or'ed value of UART_ACR_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
{
pUART->ACR |= acr;
}
/**
* @brief Clear autobaud register options
* @param pUART : Pointer to selected UART peripheral
* @param acr : Or'ed values to clear for ACR register
* @return Nothing
* @note Use an Or'ed value of UART_ACR_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
{
pUART->ACR &= ~acr;
}
/**
* @brief Set RS485 control register options
* @param pUART : Pointer to selected UART peripheral
* @param ctrl : Or'ed values to set for RS485 control register
* @return Nothing
* @note Use an Or'ed value of UART_RS485CTRL_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
{
pUART->RS485CTRL |= ctrl;
}
/**
* @brief Clear RS485 control register options
* @param pUART : Pointer to selected UART peripheral
* @param ctrl : Or'ed values to clear for RS485 control register
* @return Nothing
* @note Use an Or'ed value of UART_RS485CTRL_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
{
pUART->RS485CTRL &= ~ctrl;
}
/**
* @brief Set RS485 address match value
* @param pUART : Pointer to selected UART peripheral
* @param addr : Address match value for RS-485/EIA-485 mode
* @return Nothing
*/
STATIC INLINE void Chip_UART_SetRS485Addr(LPC_USART_T *pUART, uint8_t addr)
{
pUART->RS485ADRMATCH = (uint32_t) addr;
}
/**
* @brief Read RS485 address match value
* @param pUART : Pointer to selected UART peripheral
* @return Address match value for RS-485/EIA-485 mode
*/
STATIC INLINE uint8_t Chip_UART_GetRS485Addr(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
}
/**
* @brief Set RS485 direction control (RTS or DTR) delay value
* @param pUART : Pointer to selected UART peripheral
* @param dly : direction control (RTS or DTR) delay value
* @return Nothing
* @note This delay time is in periods of the baud clock. Any delay
* time from 0 to 255 bit times may be programmed.
*/
STATIC INLINE void Chip_UART_SetRS485Delay(LPC_USART_T *pUART, uint8_t dly)
{
pUART->RS485DLY = (uint32_t) dly;
}
/**
* @brief Read RS485 direction control (RTS or DTR) delay value
* @param pUART : Pointer to selected UART peripheral
* @return direction control (RTS or DTR) delay value
* @note This delay time is in periods of the baud clock. Any delay
* time from 0 to 255 bit times may be programmed.
*/
STATIC INLINE uint8_t Chip_UART_GetRS485Delay(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RS485DLY & 0xFF);
}
/**
* @brief Initializes the pUART peripheral
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
void Chip_UART_Init(LPC_USART_T *pUART);
/**
* @brief De-initializes the pUART peripheral.
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
void Chip_UART_DeInit(LPC_USART_T *pUART);
/**
* @brief Transmit a byte array through the UART peripheral (non-blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to bytes to transmit
* @param numBytes : Number of bytes to transmit
* @return The actual number of bytes placed into the FIFO
* @note This function places data into the transmit FIFO until either
* all the data is in the FIFO or the FIFO is full. This function
* will not block in the FIFO is full. The actual number of bytes
* placed into the FIFO is returned. This function ignores errors.
*/
int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes);
/**
* @brief Read data through the UART peripheral (non-blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to bytes array to fill
* @param numBytes : Size of the passed data array
* @return The actual number of bytes read
* @note This function reads data from the receive FIFO until either
* all the data has been read or the passed buffer is completely full.
* This function will not block. This function ignores errors.
*/
int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes);
/**
* @brief Sets best dividers to get a target bit rate (without fractional divider)
* @param pUART : Pointer to selected UART peripheral
* @param baudrate : Target baud rate (baud rate = bit rate)
* @return The actual baud rate, or 0 if no rate can be found
*/
uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate);
/**
* @brief Sets best dividers to get a target bit rate (with fractional divider)
* @param pUART : Pointer to selected UART peripheral
* @param baudrate : Target baud rate (baud rate = bit rate)
* @return The actual baud rate, or 0 if no rate can be found
*/
uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate);
/**
* @brief Transmit a byte array through the UART peripheral (blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to data to transmit
* @param numBytes : Number of bytes to transmit
* @return The number of bytes transmitted
* @note This function will send or place all bytes into the transmit
* FIFO. This function will block until the last bytes are in the FIFO.
*/
int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes);
/**
* @brief Read data through the UART peripheral (blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to data array to fill
* @param numBytes : Size of the passed data array
* @return The size of the dat array
* @note This function reads data from the receive FIFO until the passed
* buffer is completely full. The function will block until full.
* This function ignores errors.
*/
int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes);
/**
* @brief UART receive-only interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @return Nothing
* @note If ring buffer support is desired for the receive side
* of data transfer, the UART interrupt should call this
* function for a receive based interrupt status.
*/
void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
/**
* @brief UART transmit-only interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @return Nothing
* @note If ring buffer support is desired for the transmit side
* of data transfer, the UART interrupt should call this
* function for a transmit based interrupt status.
*/
void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
/**
* @brief Populate a transmit ring buffer and start UART transmit
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @param data : Pointer to buffer to move to ring buffer
* @param bytes : Number of bytes to move
* @return The number of bytes placed into the ring buffer
* @note Will move the data into the TX ring buffer and start the
* transfer. If the number of bytes returned is less than the
* number of bytes to send, the ring buffer is considered full.
*/
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes);
/**
* @brief Copy data from a receive ring buffer
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @param data : Pointer to buffer to fill from ring buffer
* @param bytes : Size of the passed buffer in bytes
* @return The number of bytes placed into the ring buffer
* @note Will move the data from the RX ring buffer up to the
* the maximum passed buffer size. Returns 0 if there is
* no data in the ring buffer.
*/
int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes);
/**
* @brief UART receive/transmit interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRXRB : Pointer to transmit ring buffer
* @param pTXRB : Pointer to receive ring buffer
* @return Nothing
* @note This provides a basic implementation of the UART IRQ
* handler for support of a ring buffer implementation for
* transmit and receive.
*/
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __UART_13XX_H_ */

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/*
* @brief LPC13xx USB device register block
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __USBD_13XX_H_
#define __USBD_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup USBD_13XX CHIP: LPC13xx USB Device driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
#if defined(CHIP_LPC1347)
/**
* @brief USB device register block structure
*/
typedef struct { /*!< (@ 0x40080000) USB Structure */
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
__IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
__IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
__IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
__IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
__IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
__IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
__IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
__IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
__IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
__IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
__IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
__I uint32_t RESERVED0[1];
__I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
} LPC_USB_T;
#endif /* defined(CHIP_LPC1347) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_13XX_H_ */

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/*
* @brief LPC13xx WWDT chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __WWDT_13XX_H_
#define __WWDT_13XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup WWDT_13XX CHIP: LPC13xx Windowed Watchdog driver
* @ingroup CHIP_13XX_Drivers
* @{
*/
#if !defined(CHIP_LPC1343)
#define WATCHDOG_WINDOW_SUPPORT
#endif
#if defined(CHIP_LPC1347)
#define WATCHDOG_CLKSEL_SUPPORT
#endif
/** WDT oscillator frequency value */
#define WDT_OSC (SYSCTL_IRC_FREQ)
/**
* @brief Windowed Watchdog register block structure
*/
typedef struct { /*!< WWDT Structure */
__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
__IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */
__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
__I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
#ifdef WATCHDOG_CLKSEL_SUPPORT
__IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
#else
__I uint32_t RESERVED0;
#endif
#ifdef WATCHDOG_WINDOW_SUPPORT
__IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
__IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */
#endif
} LPC_WWDT_T;
/**
* @brief Watchdog Mode register definitions
*/
/** Watchdog Mode Bitmask */
#define WWDT_WDMOD_BITMASK ((uint32_t) 0x1F)
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0))
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1))
/** WWDT time out flag bit */
#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2))
/** WDT Time Out flag bit */
#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3))
/** WWDT Protect flag bit */
#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4))
/** WWDT lock bit, locks the current WDT clock */
#define WWDT_WDMOD_LOCK ((uint32_t) (1 << 5))
/**
* @brief Initialize the Watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
void Chip_WWDT_Init(LPC_WWDT_T *pWWDT);
/**
* @brief Shutdown the Watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT);
/**
* @brief Set WDT timeout constant value used for feed
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
* @return none
*/
STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->TC = timeout;
}
/**
* @brief Feed watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
* @note If this function isn't called, a watchdog timer warning will occur.
* After the warning, a timeout will occur if a feed has happened.
*/
STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT)
{
pWWDT->FEED = 0xAA;
pWWDT->FEED = 0x55;
}
#if defined(WATCHDOG_WINDOW_SUPPORT)
/**
* @brief Set WWDT warning interrupt
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT warning in ticks, between 0 and 1023
* @return None
* @note This is the number of ticks after the watchdog interrupt that the
* warning interrupt will be generated.
*/
STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->WARNINT = timeout;
}
/**
* @brief Set WWDT window time
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
* @return None
* @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
* function and this function, with this function defining the last tick before the
* watchdog window interrupt occurs.
*/
STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->WINDOW = timeout;
}
#endif
/**
* @brief Enable watchdog timer options
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param options : An or'ed set of options of values
* WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
* @return None
* @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
* WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
* are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot
* be unset.
*/
STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options)
{
pWWDT->MOD |= options;
}
/**
* @brief Disable/clear watchdog timer options
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param options : An or'ed set of options of values
* WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
* @return None
* @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
* WWDT_WDMOD_WDTOF).
*/
STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options)
{
pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK;
}
/**
* @brief Enable WWDT activity
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT)
{
Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN);
Chip_WWDT_Feed(pWWDT);
}
/**
* @brief Read WWDT status flag
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return Watchdog status, an Or'ed value of WWDT_WDMOD_*
*/
STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT)
{
return pWWDT->MOD;
}
/**
* @brief Clear WWDT interrupt status flags
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param status : Or'ed value of status flag(s) that you want to clear, should be:
* - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
* - WWDT_WDMOD_WDINT: Clear watchdog warning flag
* @return None
*/
void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status);
/**
* @brief Get the current value of WDT
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return current value of WDT
*/
STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT)
{
return pWWDT->TV;
}
#if defined(WATCHDOG_CLKSEL_SUPPORT)
/**
* @brief Watchdog Timer Clock Source Selection register definitions
*/
/** Clock source select bitmask */
#define WWDT_CLKSEL_BITMASK ((uint32_t) 0x10000003)
/** Clock source select */
#define WWDT_CLKSEL_SOURCE(n) ((uint32_t) (n & 0x03))
/** Lock the clock source selection */
#define WWDT_CLKSEL_LOCK ((uint32_t) (1 << 31))
/**
* @brief Watchdog Clock Source definitions
*/
typedef enum {
WWDT_CLKSRC_IRC = WWDT_CLKSEL_SOURCE(0), /*!< Internal RC oscillator */
WWDT_CLKSRC_WATCHDOG_WDOSC = WWDT_CLKSEL_SOURCE(1), /*!< Watchdog oscillator (WDOSC) */
} CHIP_WWDT_CLK_SRC_T;
/**
* @brief Get the current value of WDT
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param wdtClkSrc : Selected watchdog clock source
* @return Nothing
*/
STATIC INLINE void Chip_WWDT_SelClockSource(LPC_WWDT_T *pWWDT, CHIP_WWDT_CLK_SRC_T wdtClkSrc)
{
pWWDT->CLKSEL = wdtClkSrc & WWDT_CLKSEL_BITMASK;
}
#endif
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __WWDT_H_ */

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/*
* @brief LPC13xx A/D conversion driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Get the number of clock for a full conversion */
STATIC INLINE uint8_t getFullConvClk(void)
{
#if defined(CHIP_LPC1347)
return 31;
#else
return 11;
#endif
}
/* Get divider value */
STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks)
{
uint32_t adcBlockFreq;
uint32_t fullAdcRate;
uint8_t div;
/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
A/D converter, which should be less than or equal to 4.5MHz.
A fully conversion requires (bits_accuracy+1) of these clocks.
ADC Clock = PCLK_ADC0 / (CLKDIV + 1);
ADC rate = ADC clock / (the number of clocks required for each conversion);
*/
adcBlockFreq = Chip_Clock_GetSystemClockRate();
#if defined(ADC_ACC_12BITS)
fullAdcRate = adcRate * getFullConvClk();
if (clks == ADC_10BITS) {
fullAdcRate /= 2;
}
#else
if (burstMode) {
fullAdcRate = adcRate * clks;
}
else {
fullAdcRate = adcRate * getFullConvClk();
}
#endif
/* Get the round value by fomular: (2*A + B)/(2*B) */
div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
return div;
}
/* Set start mode for ADC */
void setStartMode(LPC_ADC_T *pADC, uint8_t start_mode)
{
uint32_t temp;
temp = pADC->CR & (~ADC_CR_START_MASK);
pADC->CR = temp | (ADC_CR_START_MODE_SEL((uint32_t) start_mode));
}
/* Get the ADC value */
Status readAdcVal(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
{
uint32_t temp;
temp = pADC->DR[channel];
if (!ADC_DR_DONE(temp)) {
return ERROR;
}
/* if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST)) */
/* return ERROR; */
*data = (uint16_t) ADC_DR_RESULT(temp);
return SUCCESS;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the ADC peripheral and the ADC setup structure to default value */
void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup)
{
uint8_t div;
uint32_t cr = 0;
uint32_t clk;
/* Power up ADC */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_ADC_PD);
/* Enable ADC clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC);
#if defined(ADC_TRIM_SUPPORT)
pADC->ADTRM = 0xF00;
#endif
pADC->INTEN = 0; /* Disable all interrupts */
#if defined(CHIP_LPC1347)
cr |= ADC_CR_LPWRMODE;
#else
cr |= ADC_CR_PDN;
#endif
ADCSetup->adcRate = ADC_MAX_SAMPLE_RATE;
#if defined(CHIP_LPC1347)
ADCSetup->bitsAccuracy = ADC_12BITS;
clk = ADC_12BITS;
#else
ADCSetup->bitsAccuracy = ADC_10BITS;
clk = 11;
#endif
ADCSetup->burstMode = false;
div = getClkDiv(pADC, false, ADCSetup->adcRate, clk);
cr |= ADC_CR_CLKDIV(div);
#if !defined(ADC_ACC_12BITS)
cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
#endif /*defined(ADC_ACC_12BITS)*/
pADC->CR = cr;
}
/* Shutdown ADC */
void Chip_ADC_DeInit(LPC_ADC_T *pADC)
{
pADC->INTEN = 0x00000100;
pADC->CR = 0;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC);
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_ADC_PD);
}
/* Get the ADC value */
Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
{
return readAdcVal(pADC, channel, data);
}
/* Get ADC Channel status from ADC data register */
FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)
{
switch (StatusType) {
case ADC_DR_DONE_STAT:
return (pADC->STAT & (1UL << channel)) ? SET : RESET;
case ADC_DR_OVERRUN_STAT:
channel += 8;
return (pADC->STAT & (1UL << channel)) ? SET : RESET;
case ADC_DR_ADINT_STAT:
return pADC->STAT >> 16 ? SET : RESET;
default:
break;
}
return RESET;
}
/* Enable/Disable interrupt for ADC channel */
void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
pADC->INTEN |= (1UL << channel);
}
else {
pADC->INTEN &= (~(1UL << channel));
}
}
/* Select the mode starting the AD conversion */
void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption)
{
if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
if (EdgeOption) {
pADC->CR |= ADC_CR_EDGE;
}
else {
pADC->CR &= ~ADC_CR_EDGE;
}
}
setStartMode(pADC, (uint8_t) mode);
}
/* Set the ADC Sample rate */
void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate)
{
uint8_t div;
uint32_t cr;
cr = pADC->CR & (~ADC_SAMPLE_RATE_CONFIG_MASK);
ADCSetup->adcRate = rate;
#if defined(CHIP_LPC1347)
div = getClkDiv(pADC, ADCSetup->burstMode, rate, ADCSetup->bitsAccuracy);
if (ADCSetup->bitsAccuracy == ADC_10BITS) {
cr |= ADC_CR_MODE10BIT;
}
#else
div = getClkDiv(pADC, ADCSetup->burstMode, rate, (11 - ADCSetup->bitsAccuracy));
#endif
cr |= ADC_CR_CLKDIV(div);
#if !defined(ADC_ACC_12BITS)
cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
#endif /*defined(ADC_ACC_12BITS)*/
pADC->CR = cr;
}
/* Set the ADC accuracy bits */
void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution)
{
ADCSetup->bitsAccuracy = resolution;
Chip_ADC_SetSampleRate(pADC, ADCSetup, ADCSetup->adcRate);
}
/* Enable or disable the ADC channel on ADC peripheral */
void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
pADC->CR |= ADC_CR_CH_SEL(channel);
}
else {
pADC->CR &= ~ADC_CR_START_MASK;
pADC->CR &= ~ADC_CR_CH_SEL(channel);
}
}
/* Enable burst mode */
void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState)
{
setStartMode(pADC, ADC_NO_START);
#if defined(CHIP_LPC1347)
pADC->INTEN &= ~(1 << 8);
#endif
if (NewState == DISABLE) {
pADC->CR &= ~ADC_CR_BURST;
}
else {
pADC->CR |= ADC_CR_BURST;
}
}
/* Read the ADC value and convert it to 8bits value */
Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data)
{
uint16_t temp=0;
Status rt;
rt = readAdcVal(pADC, channel, &temp);
*data = (uint8_t) temp;
return rt;
}

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/*
* @brief LPC13xx Miscellaneous chip specific functions
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/* System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock;
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Update system core clock rate, should be called if the system has
a clock rate change */
void SystemCoreClockUpdate(void)
{
/* CPU core speed */
SystemCoreClock = Chip_Clock_GetSystemClockRate();
}
void Chip_USB_Init(void)
{
/* power UP USB Phy and USB PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_SYSOSC);
Chip_Clock_SetupUSBPLL(3,1);
while (!Chip_Clock_IsUSBPLLLocked()) {}
Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
}

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/*
* @brief LPC13XX System clock control functions
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Inprecise clock rates for the watchdog oscillator */
STATIC const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
0, /* WDT_OSC_ILLEGAL */
600000, /* WDT_OSC_0_60 */
1050000, /* WDT_OSC_1_05 */
1400000, /* WDT_OSC_1_40 */
1750000, /* WDT_OSC_1_75 */
2100000, /* WDT_OSC_2_10 */
2400000, /* WDT_OSC_2_40 */
2700000, /* WDT_OSC_2_70 */
3000000, /* WDT_OSC_3_00 */
3250000, /* WDT_OSC_3_25 */
3500000, /* WDT_OSC_3_50 */
3750000, /* WDT_OSC_3_75 */
4000000, /* WDT_OSC_4_00 */
4200000, /* WDT_OSC_4_20 */
4400000, /* WDT_OSC_4_40 */
4600000 /* WDT_OSC_4_60 */
};
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Compute a WDT or LFO rate */
STATIC uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
{
uint32_t div;
CHIP_WDTLFO_OSC_T clk;
/* Get WDT oscillator settings */
clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
div = reg & 0x1F;
/* Compute clock rate and divided by divde value */
return wdtOSCRate[clk] / ((div + 1) << 1);
}
/* Compute a PLL frequency */
STATIC uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
{
uint32_t msel = ((PLLReg & 0x1F) + 1);
return inputRate * msel;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Set System PLL clock source */
void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
{
LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
#if defined(CHIP_LPC1343)
LPC_SYSCTL->SYSPLLCLKUEN = 0;
LPC_SYSCTL->SYSPLLCLKUEN = 1;
#endif
}
/* Bypass System Oscillator and set oscillator frequency range */
void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
{
uint32_t ctrl = 0;
if (bypass) {
ctrl |= (1 << 0);
}
if (highfr) {
ctrl |= (1 << 1);
}
LPC_SYSCTL->SYSOSCCTRL = ctrl;
}
/* Set USB PLL clock source */
void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
{
LPC_SYSCTL->USBPLLCLKSEL = (uint32_t) src;
#if defined(CHIP_LPC1343)
LPC_SYSCTL->USBPLLCLKUEN = 0;
LPC_SYSCTL->USBPLLCLKUEN = 1;
#endif
}
/* Set main system clock source */
void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
{
LPC_SYSCTL->MAINCLKSEL = (uint32_t) src;
#if defined(CHIP_LPC1343)
LPC_SYSCTL->MAINCLKUEN = 0;
LPC_SYSCTL->MAINCLKUEN = 1;
#endif
}
/* Set USB clock source and divider */
void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
{
LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
#if defined(CHIP_LPC1343)
LPC_SYSCTL->USBCLKUEN = 0;
LPC_SYSCTL->USBCLKUEN = 1;
#endif
LPC_SYSCTL->USBCLKDIV = div;
}
#if defined(CHIP_LPC1343)
/* Set WDT clock source and divider */
void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div)
{
LPC_SYSCTL->WDTCLKSEL = (uint32_t) src;
LPC_SYSCTL->WDTCLKUEN = 0;
LPC_SYSCTL->WDTCLKUEN = 1;
LPC_SYSCTL->WDTCLKDIV = div;
}
#endif
/* Set CLKOUT clock source and divider */
void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
{
LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
#if defined(CHIP_LPC1343)
LPC_SYSCTL->CLKOUTUEN = 0;
LPC_SYSCTL->CLKOUTUEN = 1;
#endif
LPC_SYSCTL->CLKOUTDIV = div;
}
/* Return estimated watchdog oscillator rate */
uint32_t Chip_Clock_GetWDTOSCRate(void)
{
return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL);
}
/* Return System PLL input clock rate */
uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
{
uint32_t clkRate;
switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
case SYSCTL_PLLCLKSRC_IRC:
clkRate = Chip_Clock_GetIntOscRate();
break;
case SYSCTL_PLLCLKSRC_SYSOSC:
clkRate = Chip_Clock_GetMainOscRate();
break;
default:
clkRate = 0;
}
return clkRate;
}
/* Return System PLL output clock rate */
uint32_t Chip_Clock_GetSystemPLLOutClockRate(void)
{
return Chip_Clock_GetPLLFreq(LPC_SYSCTL->SYSPLLCTRL,
Chip_Clock_GetSystemPLLInClockRate());
}
/* Return USB PLL input clock rate */
uint32_t Chip_Clock_GetUSBPLLInClockRate(void)
{
uint32_t clkRate;
switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->USBPLLCLKSEL & 0x3)) {
case SYSCTL_PLLCLKSRC_IRC:
clkRate = Chip_Clock_GetIntOscRate();
break;
case SYSCTL_PLLCLKSRC_SYSOSC:
clkRate = Chip_Clock_GetMainOscRate();
break;
default:
clkRate = 0;
}
return clkRate;
}
/* Return USB PLL output clock rate */
uint32_t Chip_Clock_GetUSBPLLOutClockRate(void)
{
return Chip_Clock_GetPLLFreq(LPC_SYSCTL->USBPLLCTRL,
Chip_Clock_GetUSBPLLInClockRate());
}
/* Return main clock rate */
uint32_t Chip_Clock_GetMainClockRate(void)
{
uint32_t clkRate = 0;
switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
case SYSCTL_MAINCLKSRC_IRC:
clkRate = Chip_Clock_GetIntOscRate();
break;
case SYSCTL_MAINCLKSRC_PLLIN:
clkRate = Chip_Clock_GetSystemPLLInClockRate();
break;
case SYSCTL_MAINCLKSRC_WDTOSC:
clkRate = Chip_Clock_GetWDTOSCRate();
break;
case SYSCTL_MAINCLKSRC_PLLOUT:
clkRate = Chip_Clock_GetSystemPLLOutClockRate();
break;
}
return clkRate;
}
/* Return system clock rate */
uint32_t Chip_Clock_GetSystemClockRate(void)
{
/* No point in checking for divide by 0 */
return Chip_Clock_GetMainClockRate() / LPC_SYSCTL->SYSAHBCLKDIV;
}

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/*
* @brief LPC13xx Flash/EEPROM programming driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/*Read Part Identification number*/
void Chip_FLASH_ReadPartID(FLASH_READ_PART_ID_OUTPUT_T *pOutput)
{
FLASH_READ_PART_ID_COMMAND_T command;
command.cmd = FLASH_READ_PART_ID;
Chip_FLASH_Execute((FLASH_COMMAND_T *) &command, (FLASH_OUTPUT_T *) pOutput);
}
/*Read Boot code version number */
void Chip_FLASH_ReadBootCodeVersion(FLASH_READ_BOOTCODE_VER_OUTPUT_T *pOutput)
{
FLASH_READ_BOOTCODE_VER_COMMAND_T command;
command.cmd = FLASH_READ_BOOT_VER;
Chip_FLASH_Execute((FLASH_COMMAND_T *) &command, (FLASH_OUTPUT_T *) pOutput);
}
/* Reinvoke ISP */
void Chip_FLASH_ReInvokeISP(void)
{
FLASH_REINVOKE_ISP_COMMAND_T command;
FLASH_REINVOKE_ISP_OUTPUT_T output;
command.cmd = FLASH_REINVOKE_ISP;
Chip_FLASH_Execute((FLASH_COMMAND_T *) &command, (FLASH_OUTPUT_T *) &output);
}
/* Read UID */
void Chip_FLASH_ReadUID(FLASH_READ_UID_OUTPUT_T *pOutput)
{
FLASH_READ_UID_COMMAND_T command;
command.cmd = FLASH_READ_UID;
Chip_FLASH_Execute((FLASH_COMMAND_T *) &command, (FLASH_OUTPUT_T *) pOutput);
}

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/*
* @brief LPC13xx GPIO chip driver for LPC13(15/16/17/45/46/47) families
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC1347)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/* Set a GPIO direction */
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
{
if (setting) {
pGPIO->DIR[port] |= 1UL << bit;
}
else {
pGPIO->DIR[port] &= ~(1UL << bit);
}
}
/* Set Direction for a GPIO port */
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
{
if (out) {
pGPIO->DIR[portNum] |= bitValue;
}
else {
pGPIO->DIR[portNum] &= ~bitValue;
}
}
/* Set GPIO direction for a single GPIO pin */
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
{
if (output) {
Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
}
else {
Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
}
}
/* Set GPIO direction for a all selected GPIO pins to an input or output */
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask, bool outSet)
{
if (outSet) {
Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
}
}
#endif /* if defined(CHIP_LPC1347) */

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/*
* @brief LPC13xx GPIO chip driver for LPC13(11/13/42/43) families
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC1343)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/* Set GPIO direction */
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
{
if (setting) {
pGPIO[port].DIR |= 1UL << bit;
}
else {
pGPIO[port].DIR &= ~(1UL << bit);
}
}
/* Set Direction for a GPIO port */
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit, uint8_t out)
{
if (out) {
pGPIO[port].DIR |= bit;
}
else {
pGPIO[port].DIR &= ~bit;
}
}
/* Set GPIO direction for a single GPIO pin */
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
{
if (output) {
Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
}
else {
Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
}
}
/* Set GPIO direction for a all selected GPIO pins to an input or output */
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet)
{
if (outSet) {
Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
}
}
/* Composite function for setting up a full interrupt configuration for a single pin */
void Chip_GPIO_SetupPinInt(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, GPIO_INT_MODE_T mode)
{
uint32_t pinMask = (1 << pin);
/* Edge mode selected? */
if ((uint32_t) mode & 0x2) {
Chip_GPIO_SetPinModeEdge(pGPIO, port, pinMask);
/* Interrupt on both edges selected? */
if ((uint32_t) mode & 0x4) {
Chip_GPIO_SetEdgeModeBoth(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetEdgeModeSingle(pGPIO, port, pinMask);
}
}
else {
/* Level mode */
Chip_GPIO_SetPinModeLevel(pGPIO, port, pinMask);
}
/* Level selections will not alter 'dual edge' mode */
if ((uint32_t) mode & 0x1) {
/* High edge or level mode selected */
Chip_GPIO_SetModeHigh(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetModeLow(pGPIO, port, pinMask);
}
}
#endif /* if defined(CHIP_LPC1343) */

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/*
* @brief LPC13xx GPIO group driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC1347)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#endif /* defined(CHIP_LPC1347) */

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/*
* @brief LPC13xx I2C driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Control flags */
#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
#define LPC_I2Cx(id) ((i2c[id].ip))
#define SLAVE_ACTIVE(iic) (((iic)->flags & 0xFF00) != 0)
/* I2C common interface structure */
struct i2c_interface {
LPC_I2C_T *ip; /* IP base address of the I2C device */
CHIP_SYSCTL_CLOCK_T clk; /* Clock used by I2C */
I2C_EVENTHANDLER_T mEvent; /* Current active Master event handler */
I2C_EVENTHANDLER_T sEvent; /* Slave transfer events */
I2C_XFER_T *mXfer; /* Current active xfer pointer */
I2C_XFER_T *sXfer; /* Pointer to store xfer when bus is busy */
uint32_t flags; /* Flags used by I2C master and slave */
};
/* Slave interface structure */
struct i2c_slave_interface {
I2C_XFER_T *xfer;
I2C_EVENTHANDLER_T event;
};
/* I2C interfaces */
static struct i2c_interface i2c[I2C_NUM_INTERFACE] = {
{LPC_I2C, SYSCTL_CLOCK_I2C, Chip_I2C_EventHandler, NULL, NULL, NULL, 0}
};
static struct i2c_slave_interface i2c_slave[I2C_NUM_INTERFACE][I2C_SLAVE_NUM_INTERFACE];
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
STATIC INLINE void enableClk(I2C_ID_T id)
{
Chip_Clock_EnablePeriphClock(i2c[id].clk);
}
STATIC INLINE void disableClk(I2C_ID_T id)
{
Chip_Clock_DisablePeriphClock(i2c[id].clk);
}
/* Get the ADC Clock Rate */
STATIC INLINE uint32_t getClkRate(I2C_ID_T id)
{
return Chip_Clock_GetSystemClockRate();
}
/* Enable I2C and start master transfer */
STATIC INLINE void startMasterXfer(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
/* Enter to Master Transmitter mode */
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
}
/* Enable I2C and enable slave transfers */
STATIC INLINE void startSlaverXfer(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
/* Enter to Master Transmitter mode */
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
}
/* Check if I2C bus is free */
STATIC INLINE int isI2CBusFree(LPC_I2C_T *pI2C)
{
return !(pI2C->CONSET & I2C_CON_STO);
}
/* Get current state of the I2C peripheral */
STATIC INLINE int getCurState(LPC_I2C_T *pI2C)
{
return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
}
/* Check if the active state belongs to master mode*/
STATIC INLINE int isMasterState(LPC_I2C_T *pI2C)
{
return getCurState(pI2C) < 0x60;
}
/* Set OWN slave address for specific slave ID */
STATIC void setSlaveAddr(LPC_I2C_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
{
uint32_t index = (uint32_t) sid - 1;
pI2C->MASK[index] = mask;
if (sid == I2C_SLAVE_0) {
pI2C->ADR0 = addr;
}
else {
volatile uint32_t *abase = &pI2C->ADR1;
abase[index - 1] = addr;
}
}
/* Match the slave address */
STATIC int isSlaveAddrMatching(uint8_t addr1, uint8_t addr2, uint8_t mask)
{
mask |= 1;
return (addr1 & ~mask) == (addr2 & ~mask);
}
/* Get the index of the active slave */
STATIC I2C_SLAVE_ID lookupSlaveIndex(LPC_I2C_T *pI2C, uint8_t slaveAddr)
{
if (!(slaveAddr >> 1)) {
return I2C_SLAVE_GENERAL; /* General call address */
}
if (isSlaveAddrMatching(pI2C->ADR0, slaveAddr, pI2C->MASK[0])) {
return I2C_SLAVE_0;
}
if (isSlaveAddrMatching(pI2C->ADR1, slaveAddr, pI2C->MASK[1])) {
return I2C_SLAVE_1;
}
if (isSlaveAddrMatching(pI2C->ADR2, slaveAddr, pI2C->MASK[2])) {
return I2C_SLAVE_2;
}
if (isSlaveAddrMatching(pI2C->ADR3, slaveAddr, pI2C->MASK[3])) {
return I2C_SLAVE_3;
}
/* If everything is fine the code should never come here */
return I2C_SLAVE_GENERAL;
}
/* Master transfer state change handler handler */
int handleMasterXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
{
uint32_t cclr = I2C_CON_FLAGS;
switch (getCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0);
break;
/* Tx handling */
case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */
if (!xfer->txSz) {
cclr &= ~(xfer->rxSz ? I2C_CON_STA : I2C_CON_STO);
}
else {
pI2C->DAT = *xfer->txBuff++;
xfer->txSz--;
}
break;
/* Rx handling */
case 0x58: /* Data Received and NACK sent */
cclr &= ~I2C_CON_STO;
case 0x50: /* Data Received and ACK sent */
*xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--;
case 0x40: /* SLA+R sent and ACK received */
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
/* NAK Handling */
case 0x20: /* SLA+W sent NAK received */
case 0x30: /* DATA sent NAK received */
case 0x48: /* SLA+R sent NAK received */
xfer->status = I2C_STATUS_NAK;
cclr &= ~I2C_CON_STO;
break;
case 0x38: /* Arbitration lost */
xfer->status = I2C_STATUS_ARBLOST;
break;
/* Bus Error */
case 0x00:
xfer->status = I2C_STATUS_BUSERR;
cclr &= ~I2C_CON_STO;
}
/* Set clear control flags */
pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
pI2C->CONCLR = cclr;
/* If stopped return 0 */
if (!(cclr & I2C_CON_STO) || (xfer->status == I2C_STATUS_ARBLOST)) {
if (xfer->status == I2C_STATUS_BUSY) {
xfer->status = I2C_STATUS_DONE;
}
return 0;
}
return 1;
}
/* Find the slave address of SLA+W or SLA+R */
I2C_SLAVE_ID getSlaveIndex(LPC_I2C_T *pI2C)
{
switch (getCurState(pI2C)) {
case 0x60:
case 0x68:
case 0x70:
case 0x78:
case 0xA8:
case 0xB0:
return lookupSlaveIndex(pI2C, pI2C->DAT);
}
/* If everything is fine code should never come here */
return I2C_SLAVE_GENERAL;
}
/* Slave state machine handler */
int handleSlaveXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
{
uint32_t cclr = I2C_CON_FLAGS;
int ret = RET_SLAVE_BUSY;
xfer->status = I2C_STATUS_BUSY;
switch (getCurState(pI2C)) {
case 0x80: /* SLA: Data received + ACK sent */
case 0x90: /* GC: Data received + ACK sent */
*xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--;
ret = RET_SLAVE_RX;
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
case 0x60: /* Own SLA+W received */
case 0x68: /* Own SLA+W received after losing arbitration */
case 0x70: /* GC+W received */
case 0x78: /* GC+W received after losing arbitration */
xfer->slaveAddr = pI2C->DAT & ~1;
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
case 0xA8: /* SLA+R received */
case 0xB0: /* SLA+R received after losing arbitration */
xfer->slaveAddr = pI2C->DAT & ~1;
case 0xB8: /* DATA sent and ACK received */
pI2C->DAT = *xfer->txBuff++;
xfer->txSz--;
if (xfer->txSz > 0) {
cclr &= ~I2C_CON_AA;
}
ret = RET_SLAVE_TX;
break;
case 0xC0: /* Data transmitted and NAK received */
case 0xC8: /* Last data transmitted and ACK received */
case 0x88: /* SLA: Data received + NAK sent */
case 0x98: /* GC: Data received + NAK sent */
case 0xA0: /* STOP/Repeated START condition received */
ret = RET_SLAVE_IDLE;
cclr &= ~I2C_CON_AA;
xfer->status = I2C_STATUS_DONE;
if (xfer->slaveAddr & 1) {
cclr &= ~I2C_CON_STA;
}
break;
}
/* Set clear control flags */
pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
pI2C->CONCLR = cclr;
return ret;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Chip event handler interrupt based */
void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event)
{
struct i2c_interface *iic = &i2c[id];
volatile I2C_STATUS_T *stat;
/* Only WAIT event needs to be handled */
if (event != I2C_EVENT_WAIT) {
return;
}
stat = &iic->mXfer->status;
/* Wait for the status to change */
while (*stat == I2C_STATUS_BUSY) {}
}
/* Chip polling event handler */
void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event)
{
struct i2c_interface *iic = &i2c[id];
volatile I2C_STATUS_T *stat;
/* Only WAIT event needs to be handled */
if (event != I2C_EVENT_WAIT) {
return;
}
stat = &iic->mXfer->status;
/* Call the state change handler till xfer is done */
while (*stat == I2C_STATUS_BUSY) {
if (Chip_I2C_IsStateChanged(id)) {
Chip_I2C_MasterStateHandler(id);
}
}
}
/* Initializes the LPC_I2C peripheral with specified parameter */
void Chip_I2C_Init(I2C_ID_T id)
{
enableClk(id);
/* Set I2C operation to default */
LPC_I2Cx(id)->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
}
/* De-initializes the I2C peripheral registers to their default reset values */
void Chip_I2C_DeInit(I2C_ID_T id)
{
/* Disable I2C control */
LPC_I2Cx(id)->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
disableClk(id);
}
/* Set up clock rate for LPC_I2C peripheral */
void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate)
{
uint32_t SCLValue;
SCLValue = (getClkRate(id) / clockrate);
LPC_I2Cx(id)->SCLH = (uint32_t) (SCLValue >> 1);
LPC_I2Cx(id)->SCLL = (uint32_t) (SCLValue - LPC_I2Cx(id)->SCLH);
}
/* Get current clock rate for LPC_I2C peripheral */
uint32_t Chip_I2C_GetClockRate(I2C_ID_T id)
{
return getClkRate(id) / (LPC_I2Cx(id)->SCLH + LPC_I2Cx(id)->SCLL);
}
/* Set the master event handler */
int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event)
{
struct i2c_interface *iic = &i2c[id];
if (!iic->mXfer) {
iic->mEvent = event;
}
return iic->mEvent == event;
}
/* Get the master event handler */
I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id)
{
return i2c[id].mEvent;
}
/* Transmit and Receive data in master mode */
int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer)
{
struct i2c_interface *iic = &i2c[id];
iic->mEvent(id, I2C_EVENT_LOCK);
xfer->status = I2C_STATUS_BUSY;
iic->mXfer = xfer;
/* If slave xfer not in progress */
if (!iic->sXfer) {
startMasterXfer(iic->ip);
}
iic->mEvent(id, I2C_EVENT_WAIT);
iic->mXfer = 0;
/* Wait for stop condition to appear on bus */
while (!isI2CBusFree(iic->ip)) {}
/* Start slave if one is active */
if (SLAVE_ACTIVE(iic)) {
startSlaverXfer(iic->ip);
}
iic->mEvent(id, I2C_EVENT_UNLOCK);
return (int) xfer->status;
}
/* Master tx only */
int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.txBuff = buff;
xfer.txSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.txSz;
}
/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
* This function is useful for communicating with the I2C slave registers
*/
int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.txBuff = &cmd;
xfer.txSz = 1;
xfer.rxBuff = buff;
xfer.rxSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.rxSz;
}
/* Sequential master read */
int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.rxBuff = buff;
xfer.rxSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.rxSz;
}
/* Check if master state is active */
int Chip_I2C_IsMasterActive(I2C_ID_T id)
{
return isMasterState(i2c[id].ip);
}
/* State change handler for master transfer */
void Chip_I2C_MasterStateHandler(I2C_ID_T id)
{
if (!handleMasterXferState(i2c[id].ip, i2c[id].mXfer)) {
i2c[id].mEvent(id, I2C_EVENT_DONE);
}
}
/* Setup slave function */
void Chip_I2C_SlaveSetup(I2C_ID_T id,
I2C_SLAVE_ID sid,
I2C_XFER_T *xfer,
I2C_EVENTHANDLER_T event,
uint8_t addrMask)
{
struct i2c_interface *iic = &i2c[id];
struct i2c_slave_interface *si2c = &i2c_slave[id][sid];
si2c->xfer = xfer;
si2c->event = event;
/* Set up the slave address */
if (sid != I2C_SLAVE_GENERAL) {
setSlaveAddr(iic->ip, sid, xfer->slaveAddr, addrMask);
}
if (!SLAVE_ACTIVE(iic) && !iic->mXfer) {
startSlaverXfer(iic->ip);
}
iic->flags |= 1 << (sid + 8);
}
/* I2C Slave event handler */
void Chip_I2C_SlaveStateHandler(I2C_ID_T id)
{
int ret;
struct i2c_interface *iic = &i2c[id];
/* Get the currently addressed slave */
if (!iic->sXfer) {
struct i2c_slave_interface *si2c;
I2C_SLAVE_ID sid = getSlaveIndex(iic->ip);
si2c = &i2c_slave[id][sid];
iic->sXfer = si2c->xfer;
iic->sEvent = si2c->event;
}
iic->sXfer->slaveAddr |= iic->mXfer != 0;
ret = handleSlaveXferState(iic->ip, iic->sXfer);
if (ret) {
if (iic->sXfer->status == I2C_STATUS_DONE) {
iic->sXfer = 0;
}
iic->sEvent(id, (I2C_EVENT_T) ret);
}
}
/* Disable I2C device */
void Chip_I2C_Disable(I2C_ID_T id)
{
LPC_I2Cx(id)->CONCLR = I2C_I2CONCLR_I2ENC;
}
/* State change checking */
int Chip_I2C_IsStateChanged(I2C_ID_T id)
{
return (LPC_I2Cx(id)->CONSET & I2C_CON_SI) != 0;
}

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/*
* @brief LPC13xx I2C master driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Control flags */
#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initializes the LPC_I2C peripheral with specified parameter */
void Chip_I2CM_Init(LPC_I2C_T *pI2C)
{
/* Enable I2C clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_I2C);
/* Peripheral reset control to I2C */
Chip_SYSCTL_PeriphReset(RESET_I2C0);
}
/* De-initializes the I2C peripheral registers to their default reset values */
void Chip_I2CM_DeInit(LPC_I2C_T *pI2C)
{
/* Disable I2C clock */
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_I2C);
}
/* Set up bus speed for LPC_I2C interface */
void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed)
{
uint32_t clockDiv = (Chip_Clock_GetMainClockRate() / busSpeed);
Chip_I2CM_SetDutyCycle(pI2C, (clockDiv >> 1), (clockDiv - (clockDiv >> 1)));
}
/* Master transfer state change handler handler */
uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
uint32_t cclr = I2C_CON_FLAGS;
switch (Chip_I2CM_GetCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0);
break;
/* Tx handling */
case 0x20: /* SLA+W sent NAK received */
case 0x30: /* DATA sent NAK received */
if ((xfer->options & I2CM_XFER_OPTION_IGNORE_NACK) == 0) {
xfer->status = I2CM_STATUS_NAK;
cclr &= ~I2C_CON_STO;
break;
}
case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */
if (!xfer->txSz) {
if (xfer->rxSz) {
cclr &= ~I2C_CON_STA;
}
else {
xfer->status = I2CM_STATUS_OK;
cclr &= ~I2C_CON_STO;
}
}
else {
pI2C->DAT = *xfer->txBuff++;
xfer->txSz--;
}
break;
/* Rx handling */
case 0x58: /* Data Received and NACK sent */
case 0x50: /* Data Received and ACK sent */
*xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--;
case 0x40: /* SLA+R sent and ACK received */
if ((xfer->rxSz > 1) || (xfer->options & I2CM_XFER_OPTION_LAST_RX_ACK)) {
cclr &= ~I2C_CON_AA;
}
if (xfer->rxSz == 0) {
xfer->status = I2CM_STATUS_OK;
cclr &= ~I2C_CON_STO;
}
break;
/* NAK Handling */
case 0x48: /* SLA+R sent NAK received */
xfer->status = I2CM_STATUS_SLAVE_NAK;
cclr &= ~I2C_CON_STO;
break;
case 0x38: /* Arbitration lost */
xfer->status = I2CM_STATUS_ARBLOST;
break;
case 0x00: /* Bus Error */
xfer->status = I2CM_STATUS_BUS_ERROR;
cclr &= ~I2C_CON_STO;
break;
default:
xfer->status = I2CM_STATUS_ERROR;
cclr &= ~I2C_CON_STO;
break;
}
/* Set clear control flags */
pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
pI2C->CONCLR = cclr;
return xfer->status != I2CM_STATUS_BUSY;
}
/* Transmit and Receive data in master mode */
void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
/* set the transfer status as busy */
xfer->status = I2CM_STATUS_BUSY;
/* Clear controller state. */
Chip_I2CM_ResetControl(pI2C);
/* Enter to Master Transmitter mode */
Chip_I2CM_SendStart(pI2C);
}
/* Transmit and Receive data in master mode */
uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
uint32_t ret = 0;
/* start transfer */
Chip_I2CM_Xfer(pI2C, xfer);
while (ret == 0) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* call state change handler */
ret = Chip_I2CM_XferHandler(pI2C, xfer);
}
return ret;
}
/* Master tx only */
uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len)
{
uint32_t txLen = 0, err = 0;
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
/* generate START condition */
Chip_I2CM_SendStart(pI2C);
while ((txLen < len) && (err == 0)) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* check status and send data */
switch (Chip_I2CM_GetCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */
Chip_I2CM_WriteByte(pI2C, buff[txLen++]);
break;
case 0x38: /* Arbitration lost */
break;
default: /* we shouldn't be in any other state */
err = 1;
break;
}
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
}
return txLen;
}
/* Sequential master read */
uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len)
{
uint32_t rxLen = 0, err = 0;
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
/* generate START condition and auto-ack data received */
pI2C->CONSET = I2C_CON_AA | I2C_CON_STA;
while ((rxLen < len) && (err == 0)) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* check status and send data */
switch (Chip_I2CM_GetCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
case 0x40: /* SLA+R sent and ACK received */
case 0x50: /* Data Received and ACK sent */
buff[rxLen++] = Chip_I2CM_ReadByte(pI2C);
break;
case 0x38: /* Arbitration lost */
break;
default: /* we shouldn't be in any other state */
err = 1;
break;
}
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
}
return rxLen;
}

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/*
* @brief LPC13xx IOCON driver
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#if defined(CHIP_LPC1347)
/* I/O Control pin mux */
void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
{
if (port == 0) {
pIOCON->PIO0[pin] = modefunc;
}
else {
pIOCON->PIO1[pin] = modefunc;
}
}
#endif

53
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/*
* @brief LPC11xx Pin Interrupt and Pattern Match driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licenser disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC1347)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#endif /* defined(CHIP_LPC1347) */

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/*
* @brief LPC13xx PMU chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Enter MCU Sleep mode */
void Chip_PMU_SleepState(LPC_PMU_T *pPMU)
{
pPMU->PCON = PMU_PCON_PM_SLEEP;
SCB->SCR &= ~(1UL << SCB_SCR_SLEEPDEEP_Pos);
/* Enter sleep mode */
__WFI();
}
/* Enter MCU Deep Sleep mode */
void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU)
{
#if defined(CHIP_LPC1347)
pPMU->PCON = PMU_PCON_PM_DEEPSLEEP;
#elif defined(CHIP_LPC1343)
pPMU->PCON = PMU_PCON_PM_SLEEP;
#endif
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
/* Enter sleep mode */
__WFI();
}
/* Enter MCU Power down mode */
#if defined(CHIP_LPC1347)
void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
pPMU->PCON = PMU_PCON_PM_POWERDOWN;
/* Enter sleep mode */
__WFI();
}
#endif
/* Enter MCU Deep Power down mode */
void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
pPMU->PCON = PMU_PCON_PM_DEEPPOWERDOWN;
/* Enter sleep mode */
__WFI();
}
/* Put some of the peripheral in sleep mode */
void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode)
{
if (SleepMode == PMU_MCU_DEEP_SLEEP) {
Chip_PMU_DeepSleepState(pPMU);
}
#if defined(CHIP_LPC1347)
else if (SleepMode == PMU_MCU_POWER_DOWN) {
Chip_PMU_PowerDownState(pPMU);
}
#endif
else if (SleepMode == PMU_MCU_DEEP_PWRDOWN) {
Chip_PMU_DeepPowerDownState(pPMU);
}
else {
/* PMU_MCU_SLEEP */
Chip_PMU_SleepState(pPMU);
}
}

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/*
* @brief Common ring buffer support functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include <string.h>
#include "ring_buffer.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
#define RB_INDH(rb) ((rb)->head & ((rb)->count - 1))
#define RB_INDT(rb) ((rb)->tail & ((rb)->count - 1))
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize ring buffer */
int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
{
RingBuff->data = buffer;
RingBuff->count = count;
RingBuff->itemSz = itemSize;
RingBuff->head = RingBuff->tail = 0;
return 1;
}
/* Insert a single item into Ring Buffer */
int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data)
{
uint8_t *ptr = RingBuff->data;
/* We cannot insert when queue is full */
if (RingBuffer_IsFull(RingBuff))
return 0;
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
memcpy(ptr, data, RingBuff->itemSz);
RingBuff->head++;
return 1;
}
/* Insert multiple items into Ring Buffer */
int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num)
{
uint8_t *ptr = RingBuff->data;
int cnt1, cnt2;
/* We cannot insert when queue is full */
if (RingBuffer_IsFull(RingBuff))
return 0;
/* Calculate the segment lengths */
cnt1 = cnt2 = RingBuffer_GetFree(RingBuff);
if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count)
cnt1 = RingBuff->count - RB_INDH(RingBuff);
cnt2 -= cnt1;
cnt1 = MIN(cnt1, num);
num -= cnt1;
cnt2 = MIN(cnt2, num);
num -= cnt2;
/* Write segment 1 */
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
memcpy(ptr, data, cnt1 * RingBuff->itemSz);
RingBuff->head += cnt1;
/* Write segment 2 */
ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz;
data = (const uint8_t *) data + cnt1 * RingBuff->itemSz;
memcpy(ptr, data, cnt2 * RingBuff->itemSz);
RingBuff->head += cnt2;
return cnt1 + cnt2;
}
/* Pop single item from Ring Buffer */
int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data)
{
uint8_t *ptr = RingBuff->data;
/* We cannot pop when queue is empty */
if (RingBuffer_IsEmpty(RingBuff))
return 0;
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
memcpy(data, ptr, RingBuff->itemSz);
RingBuff->tail++;
return 1;
}
/* Pop multiple items from Ring buffer */
int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num)
{
uint8_t *ptr = RingBuff->data;
int cnt1, cnt2;
/* We cannot insert when queue is empty */
if (RingBuffer_IsEmpty(RingBuff))
return 0;
/* Calculate the segment lengths */
cnt1 = cnt2 = RingBuffer_GetCount(RingBuff);
if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count)
cnt1 = RingBuff->count - RB_INDT(RingBuff);
cnt2 -= cnt1;
cnt1 = MIN(cnt1, num);
num -= cnt1;
cnt2 = MIN(cnt2, num);
num -= cnt2;
/* Write segment 1 */
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
memcpy(data, ptr, cnt1 * RingBuff->itemSz);
RingBuff->tail += cnt1;
/* Write segment 2 */
ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz;
data = (uint8_t *) data + cnt1 * RingBuff->itemSz;
memcpy(data, ptr, cnt2 * RingBuff->itemSz);
RingBuff->tail += cnt2;
return cnt1 + cnt2;
}

99
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/*
* @brief LPC13xx RITimer chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC1347)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the RIT */
void Chip_RIT_Init(LPC_RITIMER_T *pRITimer)
{
pRITimer->COMPVAL = 0xFFFFFFFF;
pRITimer->MASK = 0x00000000;
pRITimer->CTRL = 0x0C;
pRITimer->COUNTER = 0x00000000;
pRITimer->COMPVAL_H = 0x0;
}
/* DeInitialize the RIT */
void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer)
{
Chip_RIT_Init(pRITimer);
}
/* Set timer interval value */
void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval)
{
uint32_t cmp_value;
/* Determine aapproximate compare value based on clock rate and passed interval */
cmp_value = (Chip_Clock_GetSystemClockRate() / 1000) * time_interval;
/* Set timer compare value */
Chip_RIT_SetCOMPVAL(pRITimer, cmp_value);
/* Set timer enable clear bit to clear timer to 0 whenever
counter value equals the contents of RICOMPVAL */
Chip_RIT_EnableCTRL(pRITimer, RIT_CTRL_ENCLR);
}
/* Check whether interrupt is pending */
IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer)
{
uint8_t result;
if ((pRITimer->CTRL & RIT_CTRL_INT) == 1) {
result = SET;
}
else {
return RESET;
}
return (IntStatus) result;
}
#endif /* defined(CHIP_LPC1347) */

496
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/*
* @brief LPC13xx SSP Registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
STATIC void SSP_Write2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
if (xf_setup->tx_data) {
Chip_SSP_SendFrame(pSSP, (*(uint16_t *) ((uint32_t) xf_setup->tx_data +
xf_setup->tx_cnt)));
}
else {
Chip_SSP_SendFrame(pSSP, 0xFFFF);
}
xf_setup->tx_cnt += 2;
}
/** SSP macro: write 1 bytes to FIFO buffer */
STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
if (xf_setup->tx_data) {
Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
}
else {
Chip_SSP_SendFrame(pSSP, 0xFF);
}
xf_setup->tx_cnt++;
}
/** SSP macro: read 1 bytes from FIFO buffer */
STATIC void SSP_Read2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
uint16_t rDat;
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
(xf_setup->rx_cnt < xf_setup->length)) {
rDat = Chip_SSP_ReceiveFrame(pSSP);
if (xf_setup->rx_data) {
*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
}
xf_setup->rx_cnt += 2;
}
}
/** SSP macro: read 2 bytes from FIFO buffer */
STATIC void SSP_Read1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
uint16_t rDat;
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
(xf_setup->rx_cnt < xf_setup->length)) {
rDat = Chip_SSP_ReceiveFrame(pSSP);
if (xf_setup->rx_data) {
*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
}
xf_setup->rx_cnt++;
}
}
/* Returns clock for the peripheral block */
STATIC CHIP_SYSCTL_CLOCK_T Chip_SSP_GetClockIndex(LPC_SSP_T *pSSP)
{
CHIP_SYSCTL_CLOCK_T clkSSP;
if (pSSP == LPC_SSP0) {
clkSSP = SYSCTL_CLOCK_SSP0;
}
else {
clkSSP = SYSCTL_CLOCK_SSP1;
}
return clkSSP;
}
/* Returns reset ID for the peripheral block */
STATIC CHIP_SYSCTL_PERIPH_RESET_T Chip_SSP_GetResetIndex(LPC_SSP_T *pSSP)
{
CHIP_SYSCTL_PERIPH_RESET_T resetSSP;
if (pSSP == LPC_SSP0) {
resetSSP = RESET_SSP0;
}
else {
resetSSP = RESET_SSP1;
}
return resetSSP;
}
/* Returns reset ID for the peripheral block */
STATIC void Chip_SSP_SetSSPClkDivider(LPC_SSP_T *pSSP, uint32_t div)
{
if (pSSP == LPC_SSP0) {
Chip_Clock_SetSSP0ClockDiv(div);
}
else {
Chip_Clock_SetSSP1ClockDiv(div);
}
}
/* Returns SSP peripheral clock for the peripheral block */
STATIC uint32_t Chip_SSP_GetPCLKkRate(LPC_SSP_T *pSSP)
{
uint32_t sspCLK = Chip_Clock_GetMainClockRate();
if (pSSP == LPC_SSP0) {
sspCLK /= Chip_Clock_GetSSP0ClockDiv();
}
else {
sspCLK /= Chip_Clock_GetSSP1ClockDiv();
}
return sspCLK;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/*Set up output clocks per bit for SSP bus*/
void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
{
uint32_t temp;
temp = pSSP->CR0 & (~(SSP_CR0_SCR(0xFF)));
pSSP->CR0 = temp | (SSP_CR0_SCR(clk_rate));
pSSP->CPSR = prescale;
}
/* SSP Polling Read/Write in blocking mode */
uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
/* write data to buffer */
if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
SSP_Write2BFifo(pSSP, xf_setup);
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read2BFifo(pSSP, xf_setup);
}
}
else {
while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
/* write data to buffer */
if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
SSP_Write1BFifo(pSSP, xf_setup);
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read1BFifo(pSSP, xf_setup);
}
}
if (xf_setup->tx_data) {
return xf_setup->tx_cnt;
}
else if (xf_setup->rx_data) {
return xf_setup->rx_cnt;
}
return 0;
}
/* SSP Polling Write in blocking mode */
uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
{
uint32_t tx_cnt = 0, rx_cnt = 0;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
uint16_t *wdata16;
wdata16 = (uint16_t *) buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, *wdata16);
wdata16++;
tx_cnt += 2;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) {
Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */
rx_cnt += 2;
}
}
}
else {
uint8_t *wdata8;
wdata8 = buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, *wdata8);
wdata8++;
tx_cnt++;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */
rx_cnt++;
}
}
}
return tx_cnt;
}
/* SSP Polling Read in blocking mode */
uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
{
uint32_t rx_cnt = 0, tx_cnt = 0;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
uint16_t *rdata16;
rdata16 = (uint16_t *) buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, 0xFFFF); /* just send dummy data */
tx_cnt += 2;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
*rdata16 = Chip_SSP_ReceiveFrame(pSSP);
rdata16++;
rx_cnt += 2;
}
}
}
else {
uint8_t *rdata8;
rdata8 = buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, 0xFF); /* just send dummy data */
tx_cnt++;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
*rdata8 = Chip_SSP_ReceiveFrame(pSSP);
rdata8++;
rx_cnt++;
}
}
}
return rx_cnt;
}
/* Clean all data in RX FIFO of SSP */
void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP)
{
if (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {}
}
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
}
/* SSP Interrupt Read/Write with 8-bit frame width */
Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
/* check if RX FIFO contains data */
SSP_Read1BFifo(pSSP, xf_setup);
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
/* Write data to buffer */
SSP_Write1BFifo(pSSP, xf_setup);
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read1BFifo(pSSP, xf_setup);
}
return SUCCESS;
}
return ERROR;
}
/* SSP Interrupt Read/Write with 16-bit frame width */
Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
/* check if RX FIFO contains data */
SSP_Read2BFifo(pSSP, xf_setup);
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
/* Write data to buffer */
SSP_Write2BFifo(pSSP, xf_setup);
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read2BFifo(pSSP, xf_setup);
}
return SUCCESS;
}
return ERROR;
}
/* Set the SSP operating modes, master or slave */
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master)
{
if (master) {
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
}
else {
Chip_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
}
}
/* Set the clock frequency for SSP interface */
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate)
{
uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
ssp_clk = Chip_SSP_GetPCLKkRate(pSSP);
cr0_div = 0;
cmp_clk = 0xFFFFFFFF;
prescale = 2;
while (cmp_clk > bitRate) {
cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
if (cmp_clk > bitRate) {
cr0_div++;
if (cr0_div > 0xFF) {
cr0_div = 0;
prescale += 2;
}
}
}
Chip_SSP_SetClockRate(pSSP, cr0_div, prescale);
}
/* Initialize the SSP */
void Chip_SSP_Init(LPC_SSP_T *pSSP)
{
Chip_Clock_EnablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
Chip_SSP_SetSSPClkDivider(pSSP, 1);
Chip_SYSCTL_PeriphReset(Chip_SSP_GetResetIndex(pSSP));
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
Chip_SSP_SetBitRate(pSSP, 100000);
}
/* De-initializes the SSP peripheral */
void Chip_SSP_DeInit(LPC_SSP_T *pSSP)
{
Chip_SSP_Disable(pSSP);
Chip_Clock_DisablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
Chip_SSP_SetSSPClkDivider(pSSP, 0);
}

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/*
* @brief LPC13xx specific stopwatch implementation
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#include "stopwatch.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Precompute these to optimize runtime */
static uint32_t ticksPerSecond;
static uint32_t ticksPerMs;
static uint32_t ticksPerUs;
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize stopwatch */
void StopWatch_Init(void)
{
/* Use timer 1. Set prescaler to divide by 8, should give ticks at 9 MHz.
That gives a useable stopwatch measurement range of about 8 minutes
(if system clock is running at 72 MHz). */
const uint32_t prescaleDivisor = 8;
Chip_TIMER_Init(LPC_TIMER32_1);
Chip_TIMER_PrescaleSet(LPC_TIMER32_1, prescaleDivisor - 1);
Chip_TIMER_Enable(LPC_TIMER32_1);
/* Pre-compute tick rate. */
ticksPerSecond = Chip_Clock_GetSystemClockRate() / prescaleDivisor;
ticksPerMs = ticksPerSecond / 1000;
ticksPerUs = ticksPerSecond / 1000000;
}
/* Start a stopwatch */
uint32_t StopWatch_Start(void)
{
/* Return the current timer count. */
return Chip_TIMER_ReadCount(LPC_TIMER32_1);
}
/* Returns number of ticks per second of the stopwatch timer */
uint32_t StopWatch_TicksPerSecond(void)
{
return ticksPerSecond;
}
/* Converts from stopwatch ticks to mS. */
uint32_t StopWatch_TicksToMs(uint32_t ticks)
{
return ticks / ticksPerMs;
}
/* Converts from stopwatch ticks to uS. */
uint32_t StopWatch_TicksToUs(uint32_t ticks)
{
return ticks / ticksPerUs;
}
/* Converts from mS to stopwatch ticks. */
uint32_t StopWatch_MsToTicks(uint32_t mS)
{
return mS * ticksPerMs;
}
/* Converts from uS to stopwatch ticks. */
uint32_t StopWatch_UsToTicks(uint32_t uS)
{
return uS * ticksPerUs;
}

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/*
* @brief LPC13xx System Control functions
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* PDSLEEPCFG register mask */
#if defined(CHIP_LPC1343)
#if defined(CHIP_LPC1300L)
#define PDSLEEPUSEMASK 0x000018B7 /* For CHIP_LPC1300L only */
#else
#define PDSLEEPUSEMASK 0x00000FB7
#endif /* defined (CHIP_LPC1300L) */
#else
#define PDSLEEPUSEMASK 0x00000007
#endif /* defined(CHIP_LPC1343) */
#define PDSLEEPMASKTMP (SYSCTL_DEEPSLP_BOD_PD | SYSCTL_DEEPSLP_WDTOSC_PD)
#define PDSLEEPMASK ((PDSLEEPUSEMASK) &~(PDSLEEPMASKTMP))
/* PDWAKECFG register mask */
#if defined(CHIP_LPC1347)
#define PDWAKEUPUSEMASK 0x00000800
#else
#define PDWAKEUPUSEMASK 0x0000F800
#endif
#define PDWAKEUPMASKTMP 0x000005FF
/* PDRUNCFG register mask */
#if defined(CHIP_LPC1347)
#define PDRUNCFGUSEMASK 0x0000E800
#else
#define PDRUNCFGUSEMASK 0x0000F800
#endif
#define PDRUNCFGMASKTMP 0x000005FF
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Setup deep sleep behaviour for power down */
void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask)
{
/* Update new value */
LPC_SYSCTL->PDSLEEPCFG = PDSLEEPMASK | (sleepmask & PDSLEEPMASKTMP);
}
/* Setup wakeup behaviour from deep sleep */
void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask)
{
/* Update new value */
LPC_SYSCTL->PDWAKECFG = PDWAKEUPUSEMASK | (wakeupmask & PDWAKEUPMASKTMP);
}
/* Power down one or more blocks or peripherals */
void Chip_SYSCTL_PowerDown(uint32_t powerdownmask)
{
uint32_t pdrun;
pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
pdrun |= (powerdownmask & PDRUNCFGMASKTMP);
LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
}
/* Power up one or more blocks or peripherals */
void Chip_SYSCTL_PowerUp(uint32_t powerupmask)
{
uint32_t pdrun;
pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
pdrun &= ~(powerupmask & PDRUNCFGMASKTMP);
LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
}

132
hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysinit_13xx.c Normal file
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@ -0,0 +1,132 @@
/*
* @brief LPC13xx Chip specific SystemInit
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Setup system clocking */
void Chip_SetupXtalClocking(void)
{
volatile int i;
/* Powerup main oscillator */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
/* Wait an estimated 200us for OSC to be stablized, no status
indication, dummy wait */
for (i = 0; i < 0x200; i++) {}
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_SYSOSC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 6 = 72MHz
MSEL = 5 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 6 = 72MHz
FCCO = FCLKOUT * 2 * P = 72MHz * 2 * 2 = 288MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(5, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks (72MHz clock) */
Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 72MHz
for the main clock and 72MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
}
/* Set up and initialize hardware prior to call to main */
void Chip_SetupIrcClocking(void)
{
/* IRC should be powered up */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 6 = 72MHz
MSEL = 5 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 6 = 72MHz
FCCO = FCLKOUT * 2 * P = 72MHz * 2 * 2 = 288MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(5, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
}
/* Set up and initialize hardware prior to call to main */
void Chip_SystemInit(void)
{
/* Initial internal clocking */
Chip_SetupIrcClocking();
}

115
hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/timer_13xx.c Normal file
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@ -0,0 +1,115 @@
/*
* @brief LPC13xx 16/32-bit Timer/PWM control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Returns clock index for a specific timer referenced by IP block address */
STATIC CHIP_SYSCTL_CLOCK_T Chip_TIMER_GetClock(LPC_TIMER_T *pTMR)
{
CHIP_SYSCTL_CLOCK_T tmrClk;
if (pTMR == LPC_TIMER32_1) {
tmrClk = SYSCTL_CLOCK_CT32B1;
}
else if (pTMR == LPC_TIMER16_0) {
tmrClk = SYSCTL_CLOCK_CT16B0;
}
else if (pTMR == LPC_TIMER16_1) {
tmrClk = SYSCTL_CLOCK_CT16B1;
}
else {
tmrClk = SYSCTL_CLOCK_CT32B0;
}
return tmrClk;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize a timer */
void Chip_TIMER_Init(LPC_TIMER_T *pTMR)
{
Chip_Clock_EnablePeriphClock(Chip_TIMER_GetClock(pTMR));
}
/* Shutdown a timer */
void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR)
{
Chip_Clock_DisablePeriphClock(Chip_TIMER_GetClock(pTMR));
}
/* Resets the timer terminal and prescale counts to 0 */
void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)
{
uint32_t reg;
/* Disable timer, set terminal count to non-0 */
reg = pTMR->TCR;
pTMR->TCR = 0;
pTMR->TC = 1;
/* Reset timer counter */
pTMR->TCR = TIMER_RESET;
/* Wait for terminal count to clear */
while (pTMR->TC != 0) {}
/* Restore timer state */
pTMR->TCR = reg;
}
/* Sets external match control (MATn.matchnum) pin control */
void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)
{
uint32_t mask, reg;
/* Clear bits corresponding to selected match register */
mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2)));
reg = pTMR->EMR &= ~mask;
/* Set new configuration for selected match register */
pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) |
(((uint32_t) matchState) << (4 + (matchnum * 2)));
}

280
hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/uart_13xx.c Normal file
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@ -0,0 +1,280 @@
/*
* @brief LPC13xx UART chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initializes the pUART peripheral */
void Chip_UART_Init(LPC_USART_T *pUART)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_UART0);
Chip_Clock_SetUARTClockDiv(1);
/* Enable FIFOs by default, reset them */
Chip_UART_SetupFIFOS(pUART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS));
/* Default 8N1, with DLAB disabled */
Chip_UART_ConfigData(pUART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS));
/* Disable fractional divider */
pUART->FDR = 0x10;
}
/* De-initializes the pUART peripheral */
void Chip_UART_DeInit(LPC_USART_T *pUART)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_UART0);
}
/* Transmit a byte array through the UART peripheral (non-blocking) */
int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes)
{
int sent = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((sent < numBytes) &&
((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0)) {
Chip_UART_SendByte(pUART, *p8);
p8++;
sent++;
}
return sent;
}
/* Transmit a byte array through the UART peripheral (blocking) */
int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes)
{
int pass, sent = 0;
uint8_t *p8 = (uint8_t *) data;
while (numBytes > 0) {
pass = Chip_UART_Send(pUART, p8, numBytes);
numBytes -= pass;
sent += pass;
p8 += pass;
}
return sent;
}
/* Read data through the UART peripheral (non-blocking) */
int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes)
{
int readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((readBytes < numBytes) &&
((Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) != 0)) {
*p8 = Chip_UART_ReadByte(pUART);
p8++;
readBytes++;
}
return readBytes;
}
/* Read data through the UART peripheral (blocking) */
int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes)
{
int pass, readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
while (readBytes < numBytes) {
pass = Chip_UART_Read(pUART, p8, numBytes);
numBytes -= pass;
readBytes += pass;
p8 += pass;
}
return readBytes;
}
/* Determines and sets best dividers to get a target bit rate */
uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate)
{
uint32_t div, divh, divl, clkin;
/* Determine UART clock in rate without FDR */
clkin = Chip_Clock_GetMainClockRate();
div = clkin / (baudrate * 16);
/* High and low halves of the divider */
divh = div / 256;
divl = div - (divh * 256);
Chip_UART_EnableDivisorAccess(pUART);
Chip_UART_SetDivisorLatches(pUART, divl, divh);
Chip_UART_DisableDivisorAccess(pUART);
/* Fractional FDR alreadt setup for 1 in UART init */
return clkin / div;
}
/* UART receive-only interrupt handler for ring buffers */
void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
/* New data will be ignored if data not popped in time */
while (Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) {
uint8_t ch = Chip_UART_ReadByte(pUART);
RingBuffer_Insert(pRB, &ch);
}
}
/* UART transmit-only interrupt handler for ring buffers */
void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
uint8_t ch;
/* Fill FIFO until full or until TX ring buffer is empty */
while ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0 &&
RingBuffer_Pop(pRB, &ch)) {
Chip_UART_SendByte(pUART, ch);
}
}
/* Populate a transmit ring buffer and start UART transmit */
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes)
{
uint32_t ret;
uint8_t *p8 = (uint8_t *) data;
/* Don't let UART transmit ring buffer change in the UART IRQ handler */
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
/* Move as much data as possible into transmit ring buffer */
ret = RingBuffer_InsertMult(pRB, p8, bytes);
Chip_UART_TXIntHandlerRB(pUART, pRB);
/* Add additional data to transmit ring buffer if possible */
ret += RingBuffer_InsertMult(pRB, (p8 + ret), (bytes - ret));
/* Enable UART transmit interrupt */
Chip_UART_IntEnable(pUART, UART_IER_THREINT);
return ret;
}
/* Copy data from a receive ring buffer */
int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes)
{
(void) pUART;
return RingBuffer_PopMult(pRB, (uint8_t *) data, bytes);
}
/* UART receive/transmit interrupt handler for ring buffers */
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
{
/* Handle transmit interrupt if enabled */
if (pUART->IER & UART_IER_THREINT) {
Chip_UART_TXIntHandlerRB(pUART, pTXRB);
/* Disable transmit interrupt if the ring buffer is empty */
if (RingBuffer_IsEmpty(pTXRB)) {
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
}
}
/* Handle receive interrupt */
Chip_UART_RXIntHandlerRB(pUART, pRXRB);
}
/* Determines and sets best dividers to get a target baud rate */
uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate)
{
uint32_t uClk;
uint32_t dval, mval;
uint32_t dl;
uint32_t rate16 = 16 * baudrate;
uint32_t actualRate = 0;
/* Get Clock rate */
uClk = Chip_Clock_GetMainClockRate();
/* The fractional is calculated as (PCLK % (16 * Baudrate)) / (16 * Baudrate)
* Let's make it to be the ratio DivVal / MulVal
*/
dval = uClk % rate16;
/* The PCLK / (16 * Baudrate) is fractional
* => dval = pclk % rate16
* mval = rate16;
* now mormalize the ratio
* dval / mval = 1 / new_mval
* new_mval = mval / dval
* new_dval = 1
*/
if (dval > 0) {
mval = rate16 / dval;
dval = 1;
/* In case mval still bigger then 4 bits
* no adjustment require
*/
if (mval > 12) {
dval = 0;
}
}
dval &= 0xf;
mval &= 0xf;
dl = uClk / (rate16 + rate16 *dval / mval);
/* Update UART registers */
Chip_UART_EnableDivisorAccess(pUART);
Chip_UART_SetDivisorLatches(pUART, UART_LOAD_DLL(dl), UART_LOAD_DLM(dl));
Chip_UART_DisableDivisorAccess(pUART);
/* Set best fractional divider */
pUART->FDR = (UART_FDR_MULVAL(mval) | UART_FDR_DIVADDVAL(dval));
/* Return actual baud rate */
actualRate = uClk / (16 * dl + 16 * dl * dval / mval);
return actualRate;
}

80
hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/wwdt_13xx.c Normal file
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@ -0,0 +1,80 @@
/*
* @brief LPC13xx WWDT chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the Watchdog timer */
void Chip_WWDT_Init(LPC_WWDT_T *pWWDT)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_WDT);
/* Disable watchdog */
pWWDT->MOD = 0;
pWWDT->TC = 0xFF;
#if defined(WATCHDOG_WINDOW_SUPPORT)
pWWDT->WARNINT = 0xFFFF;
pWWDT->WINDOW = 0xFFFFFF;
#endif
}
/* Shutdown the Watchdog timer */
void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_WDT);
}
/* Clear WWDT interrupt status flags */
void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status)
{
if (status & WWDT_WDMOD_WDTOF) {
pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK;
}
if (status & WWDT_WDMOD_WDINT) {
pWWDT->MOD |= WWDT_WDMOD_WDINT;
}
}

296
src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
View File

@ -40,21 +40,12 @@
#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
#define _TINY_USB_SOURCE_FILE_
// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
// endpoint's max packet size and need some soft DMA helper
//--------------------------------------------------------------------+
// INCLUDE
//--------------------------------------------------------------------+
#include "common/tusb_common.h"
#include "hal/hal.h"
#include "osal/osal.h"
#include "chip.h"
#include "device/dcd.h"
#include "usbd_dcd.h"
#include "dcd_lpc_11uxx_13uxx.h"
#include "dcd_lpc11_13_15.h"
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
@ -134,8 +125,6 @@ typedef struct {
uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
}current_td[DCD_11U_13U_QHD_COUNT];
uint8_t class_code[DCD_11U_13U_QHD_COUNT]; ///< class where the endpoints belongs to TODO no need for control endpoints
}dcd_11u_13u_data_t;
//--------------------------------------------------------------------+
@ -194,7 +183,7 @@ bool dcd_init(uint8_t rhport)
LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
NVIC_EnableIRQ(USB_IRQn);
NVIC_EnableIRQ(USB0_IRQn);
return true;
}
@ -247,17 +236,12 @@ static void endpoint_non_control_isr(uint32_t int_status)
if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
{
edpt_hdl_t edpt_hdl =
{
.rhport = 0,
.index = ep_id,
.class_code = dcd_data.class_code[ep_id]
};
dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
// TODO no way determine if the transfer is failed or not
dcd_xfer_complete(edpt_hdl, dcd_data.current_td[ep_id].xferred_total, true);
dcd_event_xfer_complete(0, ep_addr, dcd_data.current_td[ep_id].xferred_total, XFER_RESULT_SUCCESS, true);
}
//------------- Next TD is available -------------//
@ -287,100 +271,14 @@ static void endpoint_control_isr(uint32_t int_status)
if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
{
edpt_hdl_t edpt_hdl = { .rhport = 0 };
dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
// FIXME xferred_byte for control xfer is not needed now !!!
dcd_xfer_complete(edpt_hdl, 0, true);
// FIXME control xferred bytes
dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, 0, XFER_RESULT_SUCCESS, true);
}
}
}
void hal_dcd_isr(uint8_t rhport)
{
(void) rhport;
uint32_t const int_enable = LPC_USB->INTEN;
uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
if (int_status == 0) return;
uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
dcd_event_t event = { .rhport = rhport };
//------------- Device Status -------------//
if ( int_status & INT_MASK_DEVICE_STATUS )
{
LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
{
bus_reset();
event.event_id = DCD_EVENT_BUS_RESET;
dcd_event_handler(&event, true);
}
if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
{ // device disconnect
if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
{ // debouncing as this can be set when device is powering
event.event_id = DCD_EVENT_UNPLUGGED;
dcd_event_handler(&event, true);
}
}
// TODO support suspend & resume
if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
{
if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
{ // suspend signal, bus idle for more than 3ms
// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
{
event.event_id = DCD_EVENT_SUSPENDED;
dcd_event_handler(&event, true);
}
}
}
// else
// { // resume signal
// event.event_id = DCD_EVENT_RESUME;
// dcd_event_handler(&event, true);
// }
// }
}
//------------- Setup Received -------------//
if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
{ // received control request from host
// copy setup request & acknowledge so that the next setup can be received by hw
event.event_id = DCD_EVENT_SETUP_RECEIVED;
event.setup_received = dcd_data.setup_request;
dcd_event_handler(&event, true);
// NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
}
//------------- Control Endpoint -------------//
else if ( int_status & 0x03 )
{
endpoint_control_isr(int_status);
}
//------------- Non-Control Endpoints -------------//
if( int_status & ~(0x03UL) )
{
endpoint_non_control_isr(int_status);
}
}
//--------------------------------------------------------------------+
// CONTROL PIPE API
//--------------------------------------------------------------------+
@ -439,19 +337,21 @@ static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
//--------------------------------------------------------------------+
// BULK/INTERRUPT/ISOCHRONOUS PIPE API
//--------------------------------------------------------------------+
void dcd_edpt_stall(edpt_hdl_t edpt_hdl)
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
{
dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;
uint8_t const ep_id = edpt_addr2phy(edpt_addr);
dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 1;
}
bool dcd_pipe_is_stalled(edpt_hdl_t edpt_hdl)
bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
{
return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
uint8_t const ep_id = edpt_addr2phy(edpt_addr);
return dcd_data.qhd[ep_id][0].stall || dcd_data.qhd[ep_id][1].stall;
}
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
{
uint8_t ep_id = edpt_addr2phy(edpt_addr);
uint8_t const ep_id = edpt_addr2phy(edpt_addr);
// uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 0;
@ -467,42 +367,33 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
}
}
edpt_hdl_t dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
{
(void) rhport;
edpt_hdl_t const null_handle = { 0 };
if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return null_handle; // TODO not support ISO yet
TU_ASSERT (p_endpoint_desc->wMaxPacketSize.size <= 64, null_handle); // TODO ISO can be 1023, but ISO not supported now
// TODO prevent to open if endpoint size is not 64
// TODO not support ISO yet
if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return false;
//------------- Prepare Queue Head -------------//
uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable, null_handle ); // endpoint must not previously opened, normally this means running out of endpoints
// endpoint must not previously opened, normally this means running out of endpoints
TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable );
tu_memclr(dcd_data.qhd[ep_id], 2*sizeof(dcd_11u_13u_qhd_t));
dcd_data.qhd[ep_id][0].is_isochronous = dcd_data.qhd[ep_id][1].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
dcd_data.class_code[ep_id] = class_code;
dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 0;
LPC_USB->EPBUFCFG |= BIT_(ep_id);
LPC_USB->INTEN |= BIT_(ep_id);
return (edpt_hdl_t)
{
.rhport = 0,
.index = ep_id,
.class_code = class_code
};
return true;
}
bool dcd_edpt_busy(edpt_hdl_t edpt_hdl)
bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
{
return dcd_data.qhd[edpt_hdl.index][0].active || dcd_data.qhd[edpt_hdl.index][1].active;
uint8_t const ep_id = edpt_addr2phy(ep_addr);
return dcd_data.qhd[ep_id][0].active || dcd_data.qhd[ep_id][1].active;
}
static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
@ -546,33 +437,138 @@ static void queue_xfer_in_next_td(uint8_t ep_id)
dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
}
tusb_error_t dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
tusb_error_t dcd_edpt_queue_xfer(uint8_t ep_id , uint8_t * buffer, uint16_t total_bytes)
{
TU_ASSERT( !dcd_edpt_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
return TUSB_ERROR_NONE;
}
tusb_error_t dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
{
if( dcd_edpt_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
{ // save this transfer data to next td if pipe is busy or already been stalled
dcd_data.next_td[edpt_hdl.index].buff_addr_offset = addr_offset(buffer);
dcd_data.next_td[edpt_hdl.index].total_bytes = total_bytes;
uint8_t const ep_id = edpt_addr2phy(ep_addr);
dcd_data.next_ioc = int_on_complete ? BIT_SET_(dcd_data.next_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.next_ioc, edpt_hdl.index);
}else
// if( dcd_edpt_busy(ep_addr) || dcd_edpt_stalled(ep_addr) )
// { // save this transfer data to next td if pipe is busy or already been stalled
// dcd_data.next_td[ep_id].buff_addr_offset = addr_offset(buffer);
// dcd_data.next_td[ep_id].total_bytes = total_bytes;
//
// dcd_data.next_ioc = BIT_SET_(dcd_data.next_ioc, ep_id);
// }else
{
dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
dcd_data.current_ioc = BIT_SET_(dcd_data.current_ioc, ep_id);
pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
}
return TUSB_ERROR_NONE;
return true;
}
void tusb_hal_int_enable(uint8_t rhport)
{
(void) rhport; // discard compiler's warning
NVIC_EnableIRQ(USB0_IRQn);
}
void tusb_hal_int_disable(uint8_t rhport)
{
(void) rhport; // discard compiler's warning
NVIC_DisableIRQ(USB0_IRQn);
}
bool tusb_hal_init(void)
{
#if 0 // FIXME
// TODO remove magic number
LPC_SYSCON->SYSAHBCLKCTRL |= ((0x1<<14) | (0x1<<27)); /* Enable AHB clock to the USB block and USB RAM. */
LPC_SYSCON->PDRUNCFG &= ~( BIT_(8) | BIT_(10) ); // enable USB PLL & USB transceiver
/* Pull-down is needed, or internally, VBUS will be floating. This is to
address the wrong status in VBUSDebouncing bit in CmdStatus register. */
// set PIO0_3 as USB_VBUS
LPC_IOCON->PIO0_3 &= ~0x1F;
LPC_IOCON->PIO0_3 |= (0x01<<0) | (1 << 3); /* Secondary function VBUS */
// set PIO0_6 as usb connect
LPC_IOCON->PIO0_6 &= ~0x07;
LPC_IOCON->PIO0_6 |= (0x01<<0); /* Secondary function SoftConn */
#endif
return true;
}
void USB_IRQHandler(void)
{
uint32_t const int_enable = LPC_USB->INTEN;
uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
if (int_status == 0) return;
uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
//------------- Device Status -------------//
if ( int_status & INT_MASK_DEVICE_STATUS )
{
LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
{
bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
}
if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
{
// device disconnect
if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
{
// debouncing as this can be set when device is powering
dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
}
}
// TODO support suspend & resume
if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
{
if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
{ // suspend signal, bus idle for more than 3ms
// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
{
dcd_event_bus_signal(0, DCD_EVENT_SUSPENDED, true);
}
}
}
// else
// { // resume signal
// dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
// }
// }
}
//------------- Setup Received -------------//
if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
{
// received control request from host
// copy setup request & acknowledge so that the next setup can be received by hw
dcd_event_setup_received(0, (uint8_t*) &dcd_data.setup_request, true);
// NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
}
//------------- Control Endpoint -------------//
else if ( int_status & 0x03 )
{
endpoint_control_isr(int_status);
}
//------------- Non-Control Endpoints -------------//
if( int_status & ~(0x03UL) )
{
endpoint_non_control_isr(int_status);
}
}
#endif