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https://github.com/hathach/tinyusb.git
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commit
d26b574f80
@ -67,6 +67,7 @@
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#define configENABLE_FPU 1
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#define configENABLE_TRUSTZONE 0
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#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
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#define configRUN_FREERTOS_SECURE_ONLY 1
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#define configUSE_PREEMPTION 1
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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@ -67,6 +67,7 @@
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#define configENABLE_FPU 1
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#define configENABLE_TRUSTZONE 0
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#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
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#define configRUN_FREERTOS_SECURE_ONLY 1
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#define configUSE_PREEMPTION 1
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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@ -67,6 +67,7 @@
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#define configENABLE_FPU 1
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#define configENABLE_TRUSTZONE 0
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#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
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#define configRUN_FREERTOS_SECURE_ONLY 1
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#define configUSE_PREEMPTION 1
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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@ -67,6 +67,7 @@
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#define configENABLE_FPU 1
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#define configENABLE_TRUSTZONE 0
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#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
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#define configRUN_FREERTOS_SECURE_ONLY 1
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#define configUSE_PREEMPTION 1
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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@ -52,6 +52,7 @@
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#define configENABLE_FPU 1
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#define configENABLE_TRUSTZONE 0
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#define configMINIMAL_SECURE_STACK_SIZE (1024)
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#define configRUN_FREERTOS_SECURE_ONLY 1
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#define configUSE_PREEMPTION 1
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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@ -120,12 +120,17 @@ void board_init(void) {
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// Init 96 MHz clock
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BootClockFROHF96M();
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#if CFG_TUSB_OS == OPT_OS_NONE
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// 1ms tick timer
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SysTick_Config(SystemCoreClock / 1000);
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#if CFG_TUSB_OS == OPT_OS_FREERTOS
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#elif CFG_TUSB_OS == OPT_OS_FREERTOS
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// Explicitly disable systick to prevent its ISR runs before scheduler start
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SysTick->CTRL &= ~1U;
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// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
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NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
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NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
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#endif
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// Init all GPIO ports
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@ -239,6 +244,10 @@ void board_init(void) {
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// phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
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// phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
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// USBPHY->TX = phytx;
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ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
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ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
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#endif
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}
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