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Flush the dcd data on reset
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@ -48,6 +48,8 @@
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#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
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// Clean means to push any cached changes to RAM and invalidate "removes" the
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// entry from the cache.
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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#define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
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#else
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@ -199,6 +201,8 @@ static void bus_reset(uint8_t rhport)
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_dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
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_dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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}
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void dcd_init(uint8_t rhport)
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