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fixed dcd lpc17xx queue transfer & IOC handling

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able to run MSC demo
This commit is contained in:
hathach 2013-11-20 15:34:49 +07:00
parent 850fcf03f0
commit d94efa60d6
6 changed files with 71 additions and 35 deletions
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6
demos/device/device_os_none/mscd_app.h
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@ -61,10 +61,10 @@ enum
DISK_BLOCK_SIZE = 512
};
#if MCU==MCU_LPC43XX
#define MSCD_APP_RAMDISK
#else // defaults is rom disk
#if MCU==MCU_LPC11UXX || MCU==MCU_LPC13UXX
#define MSCD_APP_ROMDISK
#else // defaults is ram disk
#define MSCD_APP_RAMDISK
#endif
void msc_dev_app_init(void);

4
demos/device/device_os_none/tusb_config.h
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@ -84,8 +84,8 @@
#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
#define TUSB_CFG_DEVICE_HID_MOUSE 0
#define TUSB_CFG_DEVICE_HID_GENERIC 0
#define TUSB_CFG_DEVICE_MSC 0
#define TUSB_CFG_DEVICE_CDC 1
#define TUSB_CFG_DEVICE_MSC 1
#define TUSB_CFG_DEVICE_CDC 0
//--------------------------------------------------------------------+

30
demos/device/device_os_none/tusb_descriptors.h
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@ -74,6 +74,34 @@
#define EDPT_IN(x) (0x80 | (x))
#define EDPT_OUT(x) (x)
#if MCU == MCU_LPC175X_6X
//------------- These MCUs's endpoint number has a fixed type -------------//
//------------- CDC -------------//
#define CDC_EDPT_NOTIFICATION_ADDR EDPT_IN (1)
#define CDC_EDPT_NOTIFICATION_PACKETSIZE 64
#define CDC_EDPT_DATA_OUT_ADDR EDPT_OUT(2)
#define CDC_EDPT_DATA_IN_ADDR EDPT_IN (2)
#define CDC_EDPT_DATA_PACKETSIZE 64
//------------- HID Keyboard -------------//
#define HID_KEYBOARD_EDPT_ADDR EDPT_IN (4)
#define HID_KEYBOARD_EDPT_PACKETSIZE 8
//------------- HID Mouse -------------//
#define HID_MOUSE_EDPT_ADDR EDPT_IN (7)
#define HID_MOUSE_EDPT_PACKETSIZE 8
//------------- HID Generic -------------//
//------------- Mass Storage -------------//
#define MSC_EDPT_OUT_ADDR EDPT_OUT(5)
#define MSC_EDPT_IN_ADDR EDPT_IN (5)
#define MSC_EDPT_PACKETSIZE (TUSB_CFG_DEVICE_FULLSPEED ? 64 : 512)
#else
//------------- CDC -------------//
#define CDC_EDPT_NOTIFICATION_ADDR EDPT_IN (INTERFACE_NUM_CDC+1)
#define CDC_EDPT_NOTIFICATION_PACKETSIZE 64
@ -97,6 +125,8 @@
#define MSC_EDPT_IN_ADDR EDPT_IN (INTERFACE_NUM_MSC+1)
#define MSC_EDPT_PACKETSIZE (TUSB_CFG_DEVICE_FULLSPEED ? 64 : 512)
#endif
//--------------------------------------------------------------------+
// CONFIGURATION DESCRIPTOR
//--------------------------------------------------------------------+

3
readme.md
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@ -52,7 +52,8 @@ coming soon ...
- NXP
- LPC43xx
- LPC13uxx (12 bit ADC)
- LPC11uxx
- LPC11uxx
- LPC175x_6x
## Supported Toolchains ##

60
tinyusb/device/dcd_lpc175x_6x.c
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@ -275,34 +275,36 @@ void dcd_isr(uint8_t coreid)
{
if ( BIT_TEST_(eot_int, ep_id) )
{
dcd_dma_descriptor_t* p_dd;
dcd_dma_descriptor_t* const p_fixed_dd = qhd_get_fixed_dd(ep_id);
p_fixed_dd->buffer_length = 0; // buffer length is used to determined if fixed dd is queued in pipe xfer function
// Maximum is 2 QTD are queued in an endpoint
if (p_fixed_dd->is_next_valid)
{
p_dd = (dcd_dma_descriptor_t*) p_fixed_dd->next;
p_dd->used = 0; // free non-fixed dd
}else
{
p_dd = p_fixed_dd;
}
dcd_dma_descriptor_t* const p_last_dd = (p_fixed_dd->is_next_valid) ? ((dcd_dma_descriptor_t*) p_fixed_dd->next) : p_fixed_dd;
if ( BIT_TEST_(dcd_data.ioc_dd, dd_get_index(p_dd) ) )
{
dcd_data.ioc_dd = BIT_CLR_(dcd_data.ioc_dd, dd_get_index(p_dd) );
endpoint_handle_t edpt_hdl =
// only handle when Controller already finished the last DD
if ( dcd_data.udca[ep_id] == p_last_dd )
{
dcd_data.udca[ep_id] = p_fixed_dd; // UDCA currently points to the last DD, change to the fixed DD
p_fixed_dd->buffer_length = 0; // buffer length is used to determined if fixed dd is queued in pipe xfer function
if (p_fixed_dd->is_next_valid)
{ // last_dd is not fixed_dd --> need to free
p_last_dd->used = 0;
}
if ( BIT_TEST_(dcd_data.ioc_dd, dd_get_index(p_last_dd) ) )
{
.coreid = 0,
.index = ep_id,
.class_code = dcd_data.class_code[ep_id]
};
tusb_event_t event = (p_dd->status == DD_STATUS_NORMAL || p_dd->status == DD_STATUS_DATA_UNDERUN) ? TUSB_EVENT_XFER_COMPLETE : TUSB_EVENT_XFER_ERROR;
dcd_data.ioc_dd = BIT_CLR_(dcd_data.ioc_dd, dd_get_index(p_last_dd) );
usbd_xfer_isr(edpt_hdl, event, p_dd->present_count); // only number of bytes in the IOC qtd
endpoint_handle_t edpt_hdl =
{
.coreid = 0,
.index = ep_id,
.class_code = dcd_data.class_code[ep_id]
};
tusb_event_t event = (p_last_dd->status == DD_STATUS_NORMAL || p_last_dd->status == DD_STATUS_DATA_UNDERUN) ? TUSB_EVENT_XFER_COMPLETE : TUSB_EVENT_XFER_ERROR;
usbd_xfer_isr(edpt_hdl, event, p_last_dd->present_count); // only number of bytes in the IOC qtd
}
}
}
}
@ -477,11 +479,13 @@ tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
void dd_xfer_init(dcd_dma_descriptor_t* p_dd, void* buffer, uint16_t total_bytes)
{
p_dd->next = 0;
p_dd->is_next_valid = 0;
p_dd->buffer_addr = (uint32_t) buffer;
p_dd->buffer_length = total_bytes;
p_dd->status = DD_STATUS_NOT_SERVICED;
p_dd->next = 0;
p_dd->is_next_valid = 0;
p_dd->buffer_addr = (uint32_t) buffer;
p_dd->buffer_length = total_bytes;
p_dd->status = DD_STATUS_NOT_SERVICED;
p_dd->iso_last_packet_valid = 0;
p_dd->present_count = 0;
}
tusb_error_t dcd_pipe_queue_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t total_bytes)
@ -514,7 +518,7 @@ tusb_error_t dcd_pipe_xfer(endpoint_handle_t edpt_hdl, void * buffer, uint16_t t
p_dd->used = 1;
p_dd->max_packet_size = p_fixed_dd->max_packet_size;
p_dd->is_isochronous = p_fixed_dd->is_isochronous;
dcd_data.ioc_dd = int_on_complete ? BIT_SET_(dcd_data.ioc_dd, dd_idx) : BIT_CLR_(dcd_data.ioc_dd, dd_idx);
dcd_data.ioc_dd = int_on_complete ? BIT_SET_(dcd_data.ioc_dd, dd_idx) : BIT_CLR_(dcd_data.ioc_dd, dd_idx);
//------------- hook to fixed dd -------------//
p_fixed_dd->next = (uint32_t) p_dd;

3
tinyusb/device/usbd.c
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@ -178,8 +178,9 @@ tusb_error_t usbd_body_subtask(void)
length -= USBD_COTNROL_MAX_LENGTH_EACH_XFER;
p_buffer += USBD_COTNROL_MAX_LENGTH_EACH_XFER;
usbd_devices[coreid].is_waiting_control_xfer = false;
}
usbd_devices[coreid].is_waiting_control_xfer = false;
#endif
if ( TUSB_ERROR_NONE == error )