mirror of
https://github.com/hathach/tinyusb.git
synced 2025-01-17 05:32:55 +08:00
fix rt1010 rt1020 only has 1 usb controller, rt1050 rt1060 has 2
This commit is contained in:
hathach
parent
4ecb07afc5
commit
d991466a8e
34
hw/bsp/mimxrt1020_evk/board.h
Normal file
34
hw/bsp/mimxrt1020_evk/board.h
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
/*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2019, Ha Thach (tinyusb.org)
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* This file is part of the TinyUSB stack.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef BOARD_H_
|
||||||
|
#define BOARD_H_
|
||||||
|
|
||||||
|
// required since iMX RT10xx SDK include this file for board size
|
||||||
|
#define BOARD_FLASH_SIZE (0x800000U)
|
||||||
|
|
||||||
|
#endif /* BOARD_H_ */
|
||||||
55
hw/bsp/mimxrt1020_evk/board.mk
Normal file
55
hw/bsp/mimxrt1020_evk/board.mk
Normal file
@ -0,0 +1,55 @@
|
|||||||
|
CFLAGS += \
|
||||||
|
-mthumb \
|
||||||
|
-mabi=aapcs \
|
||||||
|
-mcpu=cortex-m7 \
|
||||||
|
-mfloat-abi=hard \
|
||||||
|
-mfpu=fpv5-d16 \
|
||||||
|
-D__ARMVFP__=0 -D__ARMFPV5__=0\
|
||||||
|
-DCPU_MIMXRT1021DAG5A \
|
||||||
|
-DXIP_EXTERNAL_FLASH=1 \
|
||||||
|
-DXIP_BOOT_HEADER_ENABLE=1 \
|
||||||
|
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX \
|
||||||
|
-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))' \
|
||||||
|
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
|
||||||
|
|
||||||
|
# mcu driver cause following warnings
|
||||||
|
#CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs
|
||||||
|
CFLAGS += -Wno-error=unused-parameter
|
||||||
|
|
||||||
|
MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1021
|
||||||
|
|
||||||
|
# All source paths should be relative to the top level.
|
||||||
|
LD_FILE = $(MCU_DIR)/gcc/MIMXRT1021xxxxx_flexspi_nor.ld
|
||||||
|
|
||||||
|
SRC_C += \
|
||||||
|
$(MCU_DIR)/system_MIMXRT1021.c \
|
||||||
|
$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
|
||||||
|
$(MCU_DIR)/project_template/clock_config.c \
|
||||||
|
$(MCU_DIR)/drivers/fsl_clock.c \
|
||||||
|
$(MCU_DIR)/drivers/fsl_gpio.c \
|
||||||
|
$(MCU_DIR)/drivers/fsl_common.c \
|
||||||
|
$(MCU_DIR)/drivers/fsl_lpuart.c
|
||||||
|
|
||||||
|
INC += \
|
||||||
|
$(TOP)/hw/bsp/$(BOARD) \
|
||||||
|
$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
|
||||||
|
$(TOP)/$(MCU_DIR) \
|
||||||
|
$(TOP)/$(MCU_DIR)/drivers \
|
||||||
|
$(TOP)/$(MCU_DIR)/project_template \
|
||||||
|
|
||||||
|
SRC_S += $(MCU_DIR)/gcc/startup_MIMXRT1021.S
|
||||||
|
|
||||||
|
# For TinyUSB port source
|
||||||
|
VENDOR = nxp
|
||||||
|
CHIP_FAMILY = transdimension
|
||||||
|
|
||||||
|
# For freeRTOS port source
|
||||||
|
FREERTOS_PORT = ARM_CM7
|
||||||
|
|
||||||
|
# For flash-jlink target
|
||||||
|
JLINK_DEVICE = CPU_MIMXRT1021DAG5A
|
||||||
|
JLINK_IF = swd
|
||||||
|
|
||||||
|
# flash by copying bin file to DAP Mass Storage
|
||||||
|
flash: $(BUILD)/$(BOARD)-firmware.bin
|
||||||
|
cp $< /media/$(USER)/RT1020-EVK/
|
||||||
49
hw/bsp/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.c
Normal file
49
hw/bsp/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.c
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "evkmimxrt1020_flexspi_nor_config.h"
|
||||||
|
|
||||||
|
/* Component ID definition, used by tools. */
|
||||||
|
#ifndef FSL_COMPONENT_ID
|
||||||
|
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||||
|
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||||
|
__attribute__((section(".boot_hdr.conf")))
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#pragma location = ".boot_hdr.conf"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
const flexspi_nor_config_t qspiflash_config = {
|
||||||
|
.memConfig =
|
||||||
|
{
|
||||||
|
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||||
|
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||||
|
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||||
|
.csHoldTime = 3u,
|
||||||
|
.csSetupTime = 3u,
|
||||||
|
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||||
|
.sflashPadType = kSerialFlash_4Pads,
|
||||||
|
.serialClkFreq = kFlexSpiSerialClk_100MHz,
|
||||||
|
.sflashA1Size = 8u * 1024u * 1024u,
|
||||||
|
.lookupTable =
|
||||||
|
{
|
||||||
|
// Read LUTs
|
||||||
|
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||||
|
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||||
|
},
|
||||||
|
},
|
||||||
|
.pageSize = 256u,
|
||||||
|
.sectorSize = 4u * 1024u,
|
||||||
|
.blockSize = 256u * 1024u,
|
||||||
|
.isUniformBlockSize = false,
|
||||||
|
};
|
||||||
|
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||||
268
hw/bsp/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
Normal file
268
hw/bsp/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
Normal file
@ -0,0 +1,268 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
|
||||||
|
#define __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include "fsl_common.h"
|
||||||
|
|
||||||
|
/*! @name Driver version */
|
||||||
|
/*@{*/
|
||||||
|
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||||
|
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/* FLEXSPI memory config block related defintions */
|
||||||
|
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||||
|
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||||
|
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||||
|
|
||||||
|
/* FLEXSPI Feature related definitions */
|
||||||
|
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||||
|
|
||||||
|
/* Lookup table related defintions */
|
||||||
|
#define CMD_INDEX_READ 0
|
||||||
|
#define CMD_INDEX_READSTATUS 1
|
||||||
|
#define CMD_INDEX_WRITEENABLE 2
|
||||||
|
#define CMD_INDEX_WRITE 4
|
||||||
|
|
||||||
|
#define CMD_LUT_SEQ_IDX_READ 0
|
||||||
|
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||||
|
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||||
|
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||||
|
|
||||||
|
#define CMD_SDR 0x01
|
||||||
|
#define CMD_DDR 0x21
|
||||||
|
#define RADDR_SDR 0x02
|
||||||
|
#define RADDR_DDR 0x22
|
||||||
|
#define CADDR_SDR 0x03
|
||||||
|
#define CADDR_DDR 0x23
|
||||||
|
#define MODE1_SDR 0x04
|
||||||
|
#define MODE1_DDR 0x24
|
||||||
|
#define MODE2_SDR 0x05
|
||||||
|
#define MODE2_DDR 0x25
|
||||||
|
#define MODE4_SDR 0x06
|
||||||
|
#define MODE4_DDR 0x26
|
||||||
|
#define MODE8_SDR 0x07
|
||||||
|
#define MODE8_DDR 0x27
|
||||||
|
#define WRITE_SDR 0x08
|
||||||
|
#define WRITE_DDR 0x28
|
||||||
|
#define READ_SDR 0x09
|
||||||
|
#define READ_DDR 0x29
|
||||||
|
#define LEARN_SDR 0x0A
|
||||||
|
#define LEARN_DDR 0x2A
|
||||||
|
#define DATSZ_SDR 0x0B
|
||||||
|
#define DATSZ_DDR 0x2B
|
||||||
|
#define DUMMY_SDR 0x0C
|
||||||
|
#define DUMMY_DDR 0x2C
|
||||||
|
#define DUMMY_RWDS_SDR 0x0D
|
||||||
|
#define DUMMY_RWDS_DDR 0x2D
|
||||||
|
#define JMP_ON_CS 0x1F
|
||||||
|
#define STOP 0
|
||||||
|
|
||||||
|
#define FLEXSPI_1PAD 0
|
||||||
|
#define FLEXSPI_2PAD 1
|
||||||
|
#define FLEXSPI_4PAD 2
|
||||||
|
#define FLEXSPI_8PAD 3
|
||||||
|
|
||||||
|
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||||
|
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||||
|
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||||
|
|
||||||
|
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||||
|
typedef enum _FlexSpiSerialClockFreq
|
||||||
|
{
|
||||||
|
kFlexSpiSerialClk_30MHz = 1,
|
||||||
|
kFlexSpiSerialClk_50MHz = 2,
|
||||||
|
kFlexSpiSerialClk_60MHz = 3,
|
||||||
|
kFlexSpiSerialClk_75MHz = 4,
|
||||||
|
kFlexSpiSerialClk_80MHz = 5,
|
||||||
|
kFlexSpiSerialClk_100MHz = 6,
|
||||||
|
kFlexSpiSerialClk_133MHz = 7,
|
||||||
|
kFlexSpiSerialClk_166MHz = 8,
|
||||||
|
kFlexSpiSerialClk_200MHz = 9,
|
||||||
|
} flexspi_serial_clk_freq_t;
|
||||||
|
|
||||||
|
//!@brief FlexSPI clock configuration type
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||||
|
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI Read Sample Clock Source definition
|
||||||
|
typedef enum _FlashReadSampleClkSource
|
||||||
|
{
|
||||||
|
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||||
|
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||||
|
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||||
|
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||||
|
} flexspi_read_sample_clk_t;
|
||||||
|
|
||||||
|
//!@brief Misc feature bit definitions
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||||
|
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||||
|
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||||
|
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||||
|
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||||
|
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||||
|
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief Flash Type Definition
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||||
|
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||||
|
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||||
|
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||||
|
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief Flash Pad Definitions
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kSerialFlash_1Pad = 1,
|
||||||
|
kSerialFlash_2Pads = 2,
|
||||||
|
kSerialFlash_4Pads = 4,
|
||||||
|
kSerialFlash_8Pads = 8,
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI LUT Sequence structure
|
||||||
|
typedef struct _lut_sequence
|
||||||
|
{
|
||||||
|
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||||
|
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||||
|
uint16_t reserved;
|
||||||
|
} flexspi_lut_seq_t;
|
||||||
|
|
||||||
|
//!@brief Flash Configuration Command Type
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||||
|
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||||
|
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||||
|
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||||
|
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||||
|
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||||
|
};
|
||||||
|
|
||||||
|
//!@brief FlexSPI Memory Configuration Block
|
||||||
|
typedef struct _FlexSPIConfig
|
||||||
|
{
|
||||||
|
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||||
|
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||||
|
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||||
|
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||||
|
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||||
|
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||||
|
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||||
|
//! Serial NAND, need to refer to datasheet
|
||||||
|
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||||
|
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||||
|
//! Generic configuration, etc.
|
||||||
|
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||||
|
//! DPI/QPI/OPI switch or reset command
|
||||||
|
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||||
|
//! sequence number, [31:16] Reserved
|
||||||
|
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||||
|
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||||
|
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||||
|
flexspi_lut_seq_t
|
||||||
|
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||||
|
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||||
|
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||||
|
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||||
|
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||||
|
//! details
|
||||||
|
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||||
|
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||||
|
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||||
|
//! Chapter for more details
|
||||||
|
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||||
|
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||||
|
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||||
|
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||||
|
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||||
|
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||||
|
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||||
|
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||||
|
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||||
|
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||||
|
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||||
|
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||||
|
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||||
|
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||||
|
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||||
|
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||||
|
//! busy flag is 0 when flash device is busy
|
||||||
|
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||||
|
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||||
|
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||||
|
} flexspi_mem_config_t;
|
||||||
|
|
||||||
|
/* */
|
||||||
|
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||||
|
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||||
|
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||||
|
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||||
|
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||||
|
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||||
|
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||||
|
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||||
|
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||||
|
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||||
|
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||||
|
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||||
|
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||||
|
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||||
|
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||||
|
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||||
|
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial NOR configuration block
|
||||||
|
*/
|
||||||
|
typedef struct _flexspi_nor_config
|
||||||
|
{
|
||||||
|
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||||
|
uint32_t pageSize; //!< Page size of Serial NOR
|
||||||
|
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||||
|
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||||
|
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||||
|
uint8_t reserved0[2]; //!< Reserved for future use
|
||||||
|
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||||
|
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||||
|
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||||
|
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||||
|
uint32_t blockSize; //!< Block size
|
||||||
|
uint32_t reserve2[11]; //!< Reserved for future use
|
||||||
|
} flexspi_nor_config_t;
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif /* __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ */
|
||||||
169
hw/bsp/mimxrt1020_evk/mimxrt1020_evk.c
Normal file
169
hw/bsp/mimxrt1020_evk/mimxrt1020_evk.c
Normal file
@ -0,0 +1,169 @@
|
|||||||
|
/*
|
||||||
|
* The MIT License (MIT)
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018, hathach (tinyusb.org)
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* This file is part of the TinyUSB stack.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../board.h"
|
||||||
|
#include "fsl_device_registers.h"
|
||||||
|
#include "fsl_gpio.h"
|
||||||
|
#include "fsl_iomuxc.h"
|
||||||
|
#include "fsl_clock.h"
|
||||||
|
#include "fsl_lpuart.h"
|
||||||
|
|
||||||
|
#include "clock_config.h"
|
||||||
|
|
||||||
|
#define LED_PINMUX IOMUXC_GPIO_AD_B0_05_GPIO1_IO05
|
||||||
|
#define LED_PORT GPIO1
|
||||||
|
#define LED_PIN 5
|
||||||
|
#define LED_STATE_ON 0
|
||||||
|
|
||||||
|
// SW8 button
|
||||||
|
#define BUTTON_PINMUX IOMUXC_SNVS_WAKEUP_GPIO5_IO00
|
||||||
|
#define BUTTON_PORT GPIO5
|
||||||
|
#define BUTTON_PIN 0
|
||||||
|
#define BUTTON_STATE_ACTIVE 0
|
||||||
|
|
||||||
|
// UART
|
||||||
|
#define UART_PORT LPUART1
|
||||||
|
#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_07_LPUART1_RX
|
||||||
|
#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_06_LPUART1_TX
|
||||||
|
|
||||||
|
const uint8_t dcd_data[] = { 0x00 };
|
||||||
|
|
||||||
|
void board_init(void)
|
||||||
|
{
|
||||||
|
// Init clock
|
||||||
|
BOARD_BootClockRUN();
|
||||||
|
SystemCoreClockUpdate();
|
||||||
|
|
||||||
|
// Enable IOCON clock
|
||||||
|
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||||
|
|
||||||
|
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||||
|
// 1ms tick timer
|
||||||
|
SysTick_Config(SystemCoreClock / 1000);
|
||||||
|
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||||
|
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||||
|
// NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// LED
|
||||||
|
IOMUXC_SetPinMux( LED_PINMUX, 0U);
|
||||||
|
IOMUXC_SetPinConfig( LED_PINMUX, 0x10B0U);
|
||||||
|
|
||||||
|
gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
|
||||||
|
GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
|
||||||
|
board_led_write(true);
|
||||||
|
|
||||||
|
// Button
|
||||||
|
IOMUXC_SetPinMux( BUTTON_PINMUX, 0U);
|
||||||
|
gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0, kGPIO_IntRisingEdge, };
|
||||||
|
GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
|
||||||
|
|
||||||
|
// UART
|
||||||
|
IOMUXC_SetPinMux( UART_TX_PINMUX, 0U);
|
||||||
|
IOMUXC_SetPinMux( UART_RX_PINMUX, 0U);
|
||||||
|
IOMUXC_SetPinConfig( UART_TX_PINMUX, 0x10B0u);
|
||||||
|
IOMUXC_SetPinConfig( UART_RX_PINMUX, 0x10B0u);
|
||||||
|
|
||||||
|
lpuart_config_t uart_config;
|
||||||
|
LPUART_GetDefaultConfig(&uart_config);
|
||||||
|
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
|
||||||
|
uart_config.enableTx = true;
|
||||||
|
uart_config.enableRx = true;
|
||||||
|
LPUART_Init(UART_PORT, &uart_config, (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U));
|
||||||
|
|
||||||
|
//------------- USB0 -------------//
|
||||||
|
// Clock
|
||||||
|
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
|
||||||
|
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
|
||||||
|
|
||||||
|
USBPHY_Type* usb_phy = USBPHY;
|
||||||
|
|
||||||
|
// Enable PHY support for Low speed device + LS via FS Hub
|
||||||
|
usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
|
||||||
|
|
||||||
|
// Enable all power for normal operation
|
||||||
|
usb_phy->PWD = 0;
|
||||||
|
|
||||||
|
// TX Timing
|
||||||
|
uint32_t phytx = usb_phy->TX;
|
||||||
|
phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
|
||||||
|
phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
|
||||||
|
usb_phy->TX = phytx;
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// USB Interrupt Handler
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
void USB_OTG1_IRQHandler(void)
|
||||||
|
{
|
||||||
|
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
|
||||||
|
tuh_isr(0);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
|
||||||
|
tud_isr(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
// Board porting API
|
||||||
|
//--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
void board_led_write(bool state)
|
||||||
|
{
|
||||||
|
GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t board_button_read(void)
|
||||||
|
{
|
||||||
|
// active low
|
||||||
|
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_uart_read(uint8_t* buf, int len)
|
||||||
|
{
|
||||||
|
LPUART_ReadBlocking(UART_PORT, buf, len);
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_uart_write(void const * buf, int len)
|
||||||
|
{
|
||||||
|
LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||||
|
volatile uint32_t system_ticks = 0;
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
system_ticks++;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t board_millis(void)
|
||||||
|
{
|
||||||
|
return system_ticks;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
@ -38,8 +38,17 @@
|
|||||||
|
|
||||||
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
|
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
|
||||||
#include "fsl_device_registers.h"
|
#include "fsl_device_registers.h"
|
||||||
|
|
||||||
|
// RT1010 and RT1020 only has 1 USB controller
|
||||||
|
#if FSL_FEATURE_SOC_USBHS_COUNT == 1
|
||||||
|
#define DCD_REGS_BASE { (dcd_registers_t*) USB_BASE }
|
||||||
|
IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn };
|
||||||
|
|
||||||
|
// RT1050, RT1060 has 2 USB controllers
|
||||||
|
#else
|
||||||
#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
|
#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
|
||||||
IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn };
|
IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn };
|
||||||
|
#endif
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user