mirror of
https://github.com/hathach/tinyusb.git
synced 2025-01-17 05:32:55 +08:00
able to get 8 byte descriptor, but read(RCVBC) always return 0
- rename max3421e to max3421 - fix incorrect bitmask for HCTL, fix initial device connect - fix bus reset cause connect IRQ
This commit is contained in:
hathach
parent
274578ff46
commit
e3f3179924
@ -93,7 +93,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
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}
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//------------- Host using MAX2341E -------------//
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
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static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
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void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
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@ -102,19 +102,17 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
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tuh_int_handler(1);
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}
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static inline void max3421e_cs_assert(bool active) {
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nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
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}
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//--------------------------------------------------------------------+
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// API: SPI transfer with MAX3421E, must be implemented by application
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//--------------------------------------------------------------------+
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bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
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uint8_t * rx_buf, size_t rx_len, bool keep_cs) {
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void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
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(void) rhport;
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nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
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}
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max3421e_cs_assert(true);
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bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
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(void) rhport;
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nrfx_spim_xfer_desc_t xfer = {
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.p_tx_buffer = tx_buf,
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@ -123,11 +121,7 @@ bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx
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.rx_length = rx_len,
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};
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bool ret = (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
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if ( !keep_cs ) max3421e_cs_assert(false);
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return ret;
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return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
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}
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#endif
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@ -218,10 +212,10 @@ void board_init(void) {
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if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY);
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#endif
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
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// manually manage CS
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nrf_gpio_cfg_output(MAX3421E_CS_PIN);
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max3421e_cs_assert(false);
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tuh_max3421_spi_cs_api(0, false);
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// USB host using max3421e usb controller via SPI
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nrfx_spim_config_t cfg = {
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@ -124,7 +124,7 @@ function(family_configure_example TARGET RTOS)
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family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
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target_sources(${TARGET}-tinyusb PUBLIC
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${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
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${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
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${TOP}/src/portable/analog/max3421/hcd_max3421.c
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)
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target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
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@ -170,7 +170,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
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// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
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// Abort a queued transfer. Note: it can only abort transfer that has not been started
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// Return true if a queued transfer is aborted, false if there is no transfer to abort
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@ -26,7 +26,7 @@
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#include "tusb_option.h"
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
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#include "host/hcd.h"
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@ -110,14 +110,14 @@ enum {
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};
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enum {
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HCTL_BUSRST = 1u << 1,
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HCTL_FRMRST = 1u << 2,
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HCTL_SAMPLEBUS = 1u << 3,
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HCTL_SIGRSM = 1u << 4,
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HCTL_RCVTOG0 = 1u << 5,
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HCTL_RCVTOG1 = 1u << 6,
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HCTL_SNDTOG0 = 1u << 7,
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HCTL_SNDTOG1 = 1u << 8,
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HCTL_BUSRST = 1u << 0,
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HCTL_FRMRST = 1u << 1,
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HCTL_SAMPLEBUS = 1u << 2,
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HCTL_SIGRSM = 1u << 3,
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HCTL_RCVTOG0 = 1u << 4,
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HCTL_RCVTOG1 = 1u << 5,
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HCTL_SNDTOG0 = 1u << 6,
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HCTL_SNDTOG1 = 1u << 7,
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};
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enum {
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@ -155,45 +155,73 @@ enum {
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HRSL_BABBLE,
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};
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enum {
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DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ
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};
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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typedef struct {
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uint8_t xfer_type;
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uint8_t data_toggle;
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uint16_t packet_size;
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uint16_t total_len;
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uint16_t xferred_len;
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uint8_t* buf;
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} hcd_ep_t;
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typedef struct {
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bool inited;
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// cached register
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uint8_t sndbc;
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uint8_t mode;
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uint8_t peraddr;
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uint8_t hxfr;
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volatile uint16_t frame_count;
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struct {
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uint16_t packet_size;
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uint16_t total_len;
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uint8_t xfer_type;
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}ep[8][2];
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} max2341e_data_t;
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hcd_ep_t ep[8][2];
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} max2341_data_t;
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static max2341e_data_t _hcd_data;
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static max2341_data_t _hcd_data;
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//--------------------------------------------------------------------+
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// API: SPI transfer with MAX3421E, must be implemented by application
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//--------------------------------------------------------------------+
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bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
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uint8_t * rx_buf, size_t rx_len, bool keep_cs);
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void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
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bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
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//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled);
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
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reg |= CMDBYTE_WRITE;
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tuh_max3421_spi_cs_api(0, true);
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tuh_max3421_spi_xfer_api(0, ®, 1, NULL, 0);
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tuh_max3421_spi_xfer_api(0, buffer, len, NULL, 0);
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tuh_max3421_spi_cs_api(0, false);
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}
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// return HIRQ register since we are in full-duplex mode
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static uint8_t reg_write(uint8_t reg, uint8_t data) {
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uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
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uint8_t rx_buf[2] = {0, 0};
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tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false);
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tuh_max3421_spi_cs_api(0, true);
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tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
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tuh_max3421_spi_cs_api(0, false);
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TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
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return rx_buf[0];
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}
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@ -201,7 +229,12 @@ static uint8_t reg_write(uint8_t reg, uint8_t data) {
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static uint8_t reg_read(uint8_t reg) {
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uint8_t tx_buf[2] = {reg, 0};
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uint8_t rx_buf[2] = {0, 0};
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return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false) ? rx_buf[1] : 0;
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tuh_max3421_spi_cs_api(0, true);
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bool ret = tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
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tuh_max3421_spi_cs_api(0, false);
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return ret ? rx_buf[1] : 0;
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}
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static inline uint8_t mode_write(uint8_t data) {
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@ -221,10 +254,9 @@ static inline uint8_t hxfr_write(uint8_t data) {
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return reg_write(HXFR_ADDR, data);
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}
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static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
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uint8_t tx_buf[1] = {reg | CMDBYTE_WRITE};
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tuh_max3421e_spi_xfer_api(0, tx_buf, 1, NULL, 0, true);
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tuh_max3421e_spi_xfer_api(0, buffer, len, NULL, 0, false);
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static inline uint8_t sndbc_write(uint8_t data) {
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_hcd_data.sndbc = data;
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return reg_write(SNDBC_ADDR, data);
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}
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@ -290,8 +322,8 @@ bool hcd_init(uint8_t rhport) {
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tu_memclr(&_hcd_data, sizeof(_hcd_data));
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// full duplex, interrupt level (should be configurable)
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reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
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// full duplex, interrupt negative edge
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reg_write(PINCTL_ADDR, PINCTL_FDUPSPI);
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// reset
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reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
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@ -303,19 +335,16 @@ bool hcd_init(uint8_t rhport) {
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// Mode: Host and DP/DM pull down
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mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
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// bus reset, this will trigger CONDET IRQ if device is already connected
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reg_write(HCTL_ADDR, HCTL_BUSRST);
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// clear all previously pending IRQ
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reg_write(HIRQ_ADDR, 0xff);
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_hcd_data.inited = true;
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// Enable Connection IRQ
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reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ);
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#if 0
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// Note: if device is already connected, CONDET IRQ may not be triggered.
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// We need to detect it by sampling bus signal. FIXME not working
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reg_write(HCTL_ADDR, HCTL_SAMPLEBUS);
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while ( reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS ) {}
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if ( TUSB_SPEED_INVALID != handle_connect_irq(rhport) ) {
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reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); // clear connect irq
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}
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#endif
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reg_write(HIEN_ADDR, DEFAULT_HIEN);
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// Enable Interrupt pin
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reg_write(CPUCTL_ADDR, CPUCTL_IE);
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@ -353,6 +382,10 @@ bool hcd_port_connect_status(uint8_t rhport) {
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// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
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void hcd_port_reset(uint8_t rhport) {
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(void) rhport;
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// Bus reset will also trigger CONDET IRQ, disable it
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uint8_t hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
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reg_write(HIEN_ADDR, hien);
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reg_write(HCTL_ADDR, HCTL_BUSRST);
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}
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@ -360,6 +393,10 @@ void hcd_port_reset(uint8_t rhport) {
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void hcd_port_reset_end(uint8_t rhport) {
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(void) rhport;
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reg_write(HCTL_ADDR, 0);
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// Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
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reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
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reg_write(HIEN_ADDR, DEFAULT_HIEN);
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}
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// Get port link speed
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@ -393,14 +430,51 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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}
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// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
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(void) rhport;
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(void) dev_addr;
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(void) ep_addr;
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(void) buffer;
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(void) buflen;
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return false;
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uint8_t const ep_num = tu_edpt_number(ep_addr);
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uint8_t const ep_dir = tu_edpt_dir(ep_addr);
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hcd_ep_t* ep = &_hcd_data.ep[ep_num][ep_dir];
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ep->buf = buffer;
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ep->total_len = buflen;
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ep->xferred_len = 0;
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uint8_t hirq = peraddr_write(daddr);
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uint8_t hctl = 0;
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uint8_t hxfr = ep_num;
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if ( ep_num == 0 ) {
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ep->data_toggle = 1;
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if ( buffer == NULL || buflen == 0 ) {
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// ZLP for ACK stage
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hxfr |= HXFR_HS;
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}
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} else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) {
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hxfr |= HXFR_ISO;
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}
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if ( 0 == ep_dir ) {
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// Page 12: Programming BULK-OUT Transfers
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TU_ASSERT(hirq & HIRQ_RCVDAV_IRQ);
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uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
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fifo_write(SNDFIFO_ADDR, buffer, xact_len);
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reg_write(SNDBC_ADDR, xact_len);
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hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
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hxfr |= HXFR_OUT_NIN;
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} else {
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// Page 13: Programming BULK-IN Transfers
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hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
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}
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reg_write(HCTL_ADDR, hctl);
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hxfr_write(hxfr);
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return true;
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}
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// Abort a queued transfer. Note: it can only abort transfer that has not been started
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@ -416,10 +490,10 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
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// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
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bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
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(void) rhport;
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(void) daddr;
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(void) setup_packet;
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_hcd_data.ep[0][0].total_len = 8;
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hcd_ep_t* ep = &_hcd_data.ep[0][0];
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ep->total_len = 8;
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ep->xferred_len = 0;
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peraddr_write(daddr);
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fifo_write(SUDFIFO_ADDR, setup_packet, 8);
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@ -437,11 +511,79 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
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return false;
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}
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static void handle_xfer_done(uint8_t rhport) {
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(void) rhport;
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uint8_t const hrsl = reg_read(HRSL_ADDR);
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uint8_t const result = hrsl & HRSL_RESULT_MASK;
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uint8_t xfer_result;
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TU_LOG3("HRSL: %02X\r\n", hrsl);
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switch(result) {
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case HRSL_SUCCESS:
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xfer_result = XFER_RESULT_SUCCESS;
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break;
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case HRSL_STALL:
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xfer_result = XFER_RESULT_STALLED;
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break;
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case HRSL_BAD_REQ:
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// occurred when initialized without any pending transfer. Skip for now
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return;
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default:
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xfer_result = XFER_RESULT_FAILED;
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break;
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}
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uint8_t ep_dir = 0;
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uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
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uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
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hcd_ep_t * ep;
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if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) {
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// SETUP or OUT transfer
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ep_dir = 0;
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ep = &_hcd_data.ep[ep_num][ep_dir];
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|
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uint8_t const xact_len = (xfer_type & HXFR_SETUP) ? 8 : _hcd_data.sndbc;
|
||||
ep->xferred_len += xact_len;
|
||||
|
||||
if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
|
||||
hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
|
||||
}else {
|
||||
// more to transfer
|
||||
}
|
||||
} else {
|
||||
// IN transfer
|
||||
ep_dir = 1;
|
||||
ep = &_hcd_data.ep[ep_num][ep_dir];
|
||||
uint8_t const xact_len = reg_read(RCVBC_ADDR);
|
||||
ep->xferred_len += xact_len;
|
||||
|
||||
// short packet or all bytes transferred
|
||||
if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
|
||||
hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
|
||||
}else {
|
||||
// more to transfer
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Interrupt Handler
|
||||
void hcd_int_handler(uint8_t rhport) {
|
||||
// not initialized, do nothing
|
||||
if ( !_hcd_data.inited ) return;
|
||||
|
||||
uint8_t hirq = reg_read(HIRQ_ADDR);
|
||||
TU_LOG3_HEX(hirq);
|
||||
|
||||
if (hirq & HIRQ_FRAME_IRQ) {
|
||||
_hcd_data.frame_count++;
|
||||
}
|
||||
|
||||
if (hirq & HIRQ_CONDET_IRQ) {
|
||||
tusb_speed_t speed = handle_connect_irq(rhport);
|
||||
|
||||
@ -452,49 +594,17 @@ void hcd_int_handler(uint8_t rhport) {
|
||||
}
|
||||
}
|
||||
|
||||
if (hirq & HIRQ_FRAME_IRQ) {
|
||||
_hcd_data.frame_count++;
|
||||
}
|
||||
|
||||
if (hirq & HIRQ_HXFRDN_IRQ) {
|
||||
uint8_t const hrsl = reg_read(HRSL_ADDR);
|
||||
uint8_t const result = hrsl & HRSL_RESULT_MASK;
|
||||
uint8_t xfer_result;
|
||||
|
||||
TU_LOG3("HRSL: %02X\r\n", hrsl);
|
||||
switch(result) {
|
||||
case HRSL_SUCCESS:
|
||||
xfer_result = XFER_RESULT_SUCCESS;
|
||||
break;
|
||||
|
||||
case HRSL_STALL:
|
||||
xfer_result = XFER_RESULT_STALLED;
|
||||
break;
|
||||
|
||||
default:
|
||||
xfer_result = XFER_RESULT_FAILED;
|
||||
break;
|
||||
}
|
||||
|
||||
uint8_t ep_dir = 0;
|
||||
uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
|
||||
uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
|
||||
|
||||
if ( xfer_type & HXFR_SETUP ) {
|
||||
// SETUP transfer
|
||||
ep_dir = 0;
|
||||
}else if ( !(xfer_type & HXFR_OUT_NIN) ) {
|
||||
// IN transfer
|
||||
ep_dir = 1;
|
||||
}
|
||||
|
||||
uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir);
|
||||
uint16_t xferred_len = _hcd_data.ep[ep_num][ep_dir].total_len;
|
||||
|
||||
hcd_event_xfer_complete(_hcd_data.peraddr, ep_addr, xferred_len, xfer_result, true);
|
||||
handle_xfer_done(rhport);
|
||||
}
|
||||
|
||||
// clear all interrupt
|
||||
if ( hirq & HIRQ_RCVDAV_IRQ ) {
|
||||
TU_LOG3("RCVDAV\r\n");
|
||||
TU_LOG3_INT(reg_read(RCVBC_ADDR));
|
||||
}
|
||||
|
||||
// clear all interrupt execept SNDBAV_IRQ
|
||||
hirq &= ~HIRQ_SNDBAV_IRQ;
|
||||
if ( hirq ) {
|
||||
reg_write(HIRQ_ADDR, hirq);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user