diff --git a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/history.txt b/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/history.txt deleted file mode 100644 index 577ef686a..000000000 --- a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/history.txt +++ /dev/null @@ -1,35 +0,0 @@ -History of updates to CMSIS_CORE_LPC11Uxx -=========================================== - -18 July 2013 ------------- -CMSIS library project using ARM Cortex-M0 CMSIS files as -supplied in ARM's CMSIS 3.20 March 2013 release, together -with NXP's device specific files taken from old -CMSISv2p00_LPC11Uxx project. - -Note files are built -Os for both Debug and Release - - -History of updates to CMSISv2p00_LPC11Uxx -========================================= - -2 June 2011 ------------ -Updated version of core_cm0.h from ARM (V2.03, dated -23. May 2011) - with main change being removal of -core debug registers (which are not accessible from -application code on Cortex-M0). - -8 April 2011 ------------- -Minor fix to LPC11Uxx.h to change LPC_CT32B1_BASE from -0x40014000 to 0x40018000 - -23 March 2011 -------------- -LPC11Uxx CMSIS 2.0 library project using ARM -Cortex-M0 CMSIS files as supplied in ARM's CMSIS 2.0 -December 2010 release, together with device/board -specific files from NXP. - diff --git a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/LPC11Uxx.h b/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/LPC11Uxx.h deleted file mode 100644 index bc3f737aa..000000000 --- a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/LPC11Uxx.h +++ /dev/null @@ -1,670 +0,0 @@ - -/****************************************************************************************************//** - * @file LPC11Uxx.h - * - * - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for - * default LPC11Uxx Device Series - * - * @version V0.1 - * @date 21. March 2011 - * - * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45 - * - * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, - * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40 - * - *******************************************************************************************************/ - -// ################################################################################ -// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000 -// ################################################################################ - -/** @addtogroup NXP - * @{ - */ - -/** @addtogroup LPC11Uxx - * @{ - */ - -#ifndef __LPC11UXX_H__ -#define __LPC11UXX_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#if defined ( __CC_ARM ) - #pragma anon_unions -#endif - - /* Interrupt Number Definition */ - -typedef enum { -// ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------ -FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */ - FLEX_INT1_IRQn = 1, - FLEX_INT2_IRQn = 2, - FLEX_INT3_IRQn = 3, - FLEX_INT4_IRQn = 4, - FLEX_INT5_IRQn = 5, - FLEX_INT6_IRQn = 6, - FLEX_INT7_IRQn = 7, - GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */ - GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */ - Reserved0_IRQn = 10, /*!< Reserved Interrupt */ - Reserved1_IRQn = 11, - Reserved2_IRQn = 12, - Reserved3_IRQn = 13, - SSP1_IRQn = 14, /*!< SSP1 Interrupt */ - I2C_IRQn = 15, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ - SSP0_IRQn = 20, /*!< SSP0 Interrupt */ - UART_IRQn = 21, /*!< UART Interrupt */ - USB_IRQn = 22, /*!< USB IRQ Interrupt */ - USB_FIQn = 23, /*!< USB FIQ Interrupt */ - ADC_IRQn = 24, /*!< A/D Converter Interrupt */ - WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ - FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ - Reserved4_IRQn = 28, /*!< Reserved Interrupt */ - Reserved5_IRQn = 29, /*!< Reserved Interrupt */ - USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */ - Reserved6_IRQn = 31, /*!< Reserved Interrupt */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ - -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */ - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) - */ - -typedef struct { /*!< (@ 0x40000000) I2C Structure */ - __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */ - __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */ - __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */ - __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */ - __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */ - __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */ - __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/ - __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/ - __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/ - __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/ - __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/ - __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */ -union{ - __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */ - struct{ - __IO uint32_t MASK0; - __IO uint32_t MASK1; - __IO uint32_t MASK2; - __IO uint32_t MASK3; - }; - }; -} LPC_I2C_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- WWDT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) - */ - -typedef struct { /*!< (@ 0x40004000) WWDT Structure */ - __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/ - __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */ - __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */ - __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */ - __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */ - __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ - __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */ -} LPC_WWDT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- USART ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) - */ - -typedef struct { /*!< (@ 0x40008000) USART Structure */ - - union { - __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ - __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ - }; - - union { - __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */ - __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - }; - - union { - __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */ - __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ - }; - __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ - __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */ - __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ - __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */ - __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ - __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ - __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */ - __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ - __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */ - __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ - __I uint32_t RESERVED0[3]; - __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */ - __I uint32_t RESERVED1; - __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */ - __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ - __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ - __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ - __IO uint32_t SYNCCTRL; -} LPC_USART_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- Timer ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 - */ - -typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */ - __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */ - __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */ - __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */ - __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */ - __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */ - __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */ - union { - __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */ - struct{ - __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */ - __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */ - __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */ - __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */ - }; - }; - __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */ - union{ - __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */ - struct{ - __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */ - __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */ - __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */ - __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */ - }; - }; -__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */ - __I uint32_t RESERVED0[12]; - __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */ - __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */ -} LPC_CTxxBx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- ADC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) - */ - -typedef struct { /*!< (@ 0x4001C000) ADC Structure */ - __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */ - __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */ - __I uint32_t RESERVED0[1]; - __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */ - union{ - __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/ - struct{ - __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ - __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/ - __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/ - __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/ - __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/ - __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/ - __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/ - __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/ - }; - }; - __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */ -} LPC_ADC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- PMU ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) - */ - -typedef struct { /*!< (@ 0x40038000) PMU Structure */ - __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */ - union{ - __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */ - struct{ - __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */ - __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */ - __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */ - __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */ - }; - }; -} LPC_PMU_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- FLASHCTRL ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) - */ - -typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */ - __I uint32_t RESERVED2[1]; - __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */ - __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */ - __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */ - __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */ - __I uint32_t RESERVED3[1001]; - __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */ - __I uint32_t RESERVED4[1]; - __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */ -} LPC_FLASHCTRL_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SSP0/1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) - */ - -typedef struct { /*!< (@ 0x40040000) SSP0 Structure */ - __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ - __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ - __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ - __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */ - __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */ - __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ - __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ - __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ -} LPC_SSPx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- IOCONFIG ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) - */ - -typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ - __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */ - __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */ - __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ - __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */ - __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */ - __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */ - __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */ - __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */ - __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ - __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ - __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */ - __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ - __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */ - __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */ - __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */ - __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */ - __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */ - __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */ - __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */ - __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */ - __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */ - __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */ - __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */ - __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */ - __IO uint32_t PIO1_0; /*!< Offset: 0x060 */ - __IO uint32_t PIO1_1; - __IO uint32_t PIO1_2; - __IO uint32_t PIO1_3; - __IO uint32_t PIO1_4; /*!< Offset: 0x070 */ - __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */ - __IO uint32_t PIO1_6; - __IO uint32_t PIO1_7; - __IO uint32_t PIO1_8; /*!< Offset: 0x080 */ - __IO uint32_t PIO1_9; - __IO uint32_t PIO1_10; - __IO uint32_t PIO1_11; - __IO uint32_t PIO1_12; /*!< Offset: 0x090 */ - __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */ - __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */ - __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */ - __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */ - __IO uint32_t PIO1_17; - __IO uint32_t PIO1_18; - __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */ - __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */ - __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */ - __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */ - __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */ - __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */ - __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */ - __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */ - __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */ - __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */ - __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */ - __IO uint32_t PIO1_30; - __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */ -} LPC_IOCON_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SYSCON ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) - */ - -typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ - __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ - __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ - __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ - __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ - __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */ - __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */ - __I uint32_t RESERVED0[2]; - __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ - __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ - __I uint32_t RESERVED1[2]; - __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ - __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ - __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */ - __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */ - __I uint32_t RESERVED3[8]; - __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ - __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ - __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ - __I uint32_t RESERVED4[1]; - __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ - __I uint32_t RESERVED5[4]; - __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */ - __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */ - __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */ - __I uint32_t RESERVED6[8]; - __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */ - __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */ - __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */ - __I uint32_t RESERVED7[5]; - __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ - __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ - __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ - __I uint32_t RESERVED8[5]; - __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ - __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */ - __I uint32_t RESERVED9[18]; - __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ - __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ - __I uint32_t RESERVED10[6]; - __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */ - __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ - __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */ - __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */ - __I uint32_t RESERVED11[25]; - __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */ - __I uint32_t RESERVED12[3]; - __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */ - __I uint32_t RESERVED13[6]; - __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ - __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ - __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ - __I uint32_t RESERVED14[110]; - __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */ -} LPC_SYSCON_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PIN_INT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) - */ - -typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */ -} LPC_GPIO_PIN_INT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INT0/1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) - */ - -typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */ - __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */ - __I uint32_t RESERVED0[7]; - __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */ - __I uint32_t RESERVED1[6]; - __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */ -} LPC_GPIO_GROUP_INTx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- USB ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) - */ - -typedef struct { /*!< (@ 0x40080000) USB Structure */ - __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */ - __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */ - __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */ - __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */ - __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */ - __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */ - __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */ - __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */ - __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */ - __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */ - __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */ - __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */ - __I uint32_t RESERVED0[1]; - __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */ -} LPC_USB_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) - */ - -typedef struct { - union { - struct { - __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */ - __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */ - }; - __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */ - }; - __I uint32_t RESERVED0[1008]; - union { - struct { - __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */ - __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */ - }; - __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */ - }; - uint32_t RESERVED1[960]; - __IO uint32_t DIR[2]; /* 0x2000 */ - uint32_t RESERVED2[30]; - __IO uint32_t MASK[2]; /* 0x2080 */ - uint32_t RESERVED3[30]; - __IO uint32_t PIN[2]; /* 0x2100 */ - uint32_t RESERVED4[30]; - __IO uint32_t MPIN[2]; /* 0x2180 */ - uint32_t RESERVED5[30]; - __IO uint32_t SET[2]; /* 0x2200 */ - uint32_t RESERVED6[30]; - __O uint32_t CLR[2]; /* 0x2280 */ - uint32_t RESERVED7[30]; - __O uint32_t NOT[2]; /* 0x2300 */ -} LPC_GPIO_Type; - - -#if defined ( __CC_ARM ) - #pragma no_anon_unions -#endif - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral memory map ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_I2C_BASE (0x40000000) -#define LPC_WWDT_BASE (0x40004000) -#define LPC_USART_BASE (0x40008000) -#define LPC_CT16B0_BASE (0x4000C000) -#define LPC_CT16B1_BASE (0x40010000) -#define LPC_CT32B0_BASE (0x40014000) -#define LPC_CT32B1_BASE (0x40018000) -#define LPC_ADC_BASE (0x4001C000) -#define LPC_PMU_BASE (0x40038000) -#define LPC_FLASHCTRL_BASE (0x4003C000) -#define LPC_SSP0_BASE (0x40040000) -#define LPC_SSP1_BASE (0x40058000) -#define LPC_IOCON_BASE (0x40044000) -#define LPC_SYSCON_BASE (0x40048000) -#define LPC_GPIO_PIN_INT_BASE (0x4004C000) -#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000) -#define LPC_GPIO_GROUP_INT1_BASE (0x40060000) -#define LPC_USB_BASE (0x40080000) -#define LPC_GPIO_BASE (0x50000000) - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral declaration ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) -#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) -#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE) -#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) -#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) -#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) -#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) -#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) -#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE) -#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE) -#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) -#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) -#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) -#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE) -#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE) -#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) -#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group (null) */ -/** @} */ /* End of group LPC11Uxx */ - -#ifdef __cplusplus -} -#endif - - -#endif // __LPC11UXX_H__ diff --git a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/power_api.h b/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/power_api.h deleted file mode 100644 index 23296c5ff..000000000 --- a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/power_api.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $ - * Project: NXP LPC11Uxx software example - * - * Description: - * Power API Header File for NXP LPC11Uxx Device Series - * - **************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. -****************************************************************************/ -#ifndef __LPC11UXX_POWER_API_H__ -#define __LPC11UXX_POWER_API_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#define PWRROMD_PRESENT - -typedef struct _PWRD { - void (*set_pll)(unsigned int cmd[], unsigned int resp[]); - void (*set_power)(unsigned int cmd[], unsigned int resp[]); -} PWRD; - -typedef struct _ROM { -#ifdef USBROMD_PRESENT - const USB * pUSBD; -#else - const unsigned p_usbd; -#endif /* USBROMD_PRESENT */ - const unsigned p_clib; - const unsigned p_cand; -#ifdef PWRROMD_PRESENT - const PWRD * pPWRD; -#else - const unsigned p_pwrd; -#endif /* PWRROMD_PRESENT */ - const unsigned p_dev1; - const unsigned p_dev2; - const unsigned p_dev3; - const unsigned p_dev4; -} ROM; - -//PLL setup related definitions -#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified -#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified -#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified -#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified - -#define PLL_CMD_SUCCESS 0 //PLL setup successfully found -#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output) -#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified -#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions -#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup - -//power setup elated definitions -#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface) -#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation) -#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance) -#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance - -#define PARAM_CMD_SUCCESS 0 //power setting successfully found -#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz) -#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid) - -#define MAX_CLOCK_KHZ_PARAM 50000 - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC11UXX_POWER_API_H__ */ - diff --git a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/system_LPC11Uxx.h b/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/system_LPC11Uxx.h deleted file mode 100644 index aaf73f705..000000000 --- a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/inc/system_LPC11Uxx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_LPC11Uxx.h - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File - * for the NXP LPC11Uxx Device Series - * @version V1.10 - * @date 24. November 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC11Uxx_H -#define __SYSTEM_LPC11Uxx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC11Uxx_H */ diff --git a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/liblinks.xml b/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/liblinks.xml deleted file mode 100644 index 7ed75897a..000000000 --- a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/liblinks.xml +++ /dev/null @@ -1,32 +0,0 @@ - - - - - ${workspace_loc:/CMSIS_CORE_LPC11Uxx/inc} - - - __USE_CMSIS=CMSIS_CORE_LPC11Uxx - - - CMSIS_CORE_LPC11Uxx - - - ${workspace_loc:/CMSIS_CORE_LPC11Uxx/Debug} - - - ${workspace_loc:/CMSIS_CORE_LPC11Uxx/Release} - - - CMSIS_CORE_LPC11Uxx - - - diff --git a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/src/system_LPC11Uxx.c b/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/src/system_LPC11Uxx.c deleted file mode 100644 index 387601587..000000000 --- a/hw/mcu/nxp/lpc11uxx/CMSIS_CORE_LPC11Uxx/src/system_LPC11Uxx.c +++ /dev/null @@ -1,451 +0,0 @@ -/****************************************************************************** - * @file system_LPC11Uxx.c - * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC13xx Device Series - * @version V1.10 - * @date 24. November 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#include -#include "LPC11Uxx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable -// If enabled then PLL input (sys_osc_clk) is fed -// directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range -// Determines frequency range for Low-power oscillator. -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -// -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.5 MHz -// <2=> 0.8 MHz -// <3=> 1.1 MHz -// <4=> 1.4 MHz -// <5=> 1.6 MHz -// <6=> 1.8 MHz -// <7=> 2.0 MHz -// <8=> 2.2 MHz -// <9=> 2.4 MHz -// <10=> 2.6 MHz -// <11=> 2.7 MHz -// <12=> 2.9 MHz -// <13=> 3.1 MHz -// <14=> 3.2 MHz -// <15=> 3.4 MHz -// -// -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -// -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> Reserved -// <3=> Reserved -// -// -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> Input Clock to System PLL -// <2=> WDT Oscillator -// <3=> System PLL Clock Out -// -// -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// -// -// USB PLL Control Register (USBPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -// -// USB PLL Clock Source Select Register (USBPLLCLKSEL) -// SEL: USB PLL Clock Source -// USB PLL clock source must be switched to System Oscillator for correct USB operation -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> Reserved -// <3=> Reserved -// -// -// USB Clock Source Select Register (USBCLKSEL) -// SEL: System PLL Clock Source -// <0=> USB PLL out -// <1=> Main clock -// <2=> Reserved -// <3=> Reserved -// -// -// USB Clock Divider Register (USBCLKDIV) -// DIV: USB Clock Divider -// Divides USB clock to 48 MHz. -// 0 = is disabled -// <0-255> -// -// -*/ -#define CLOCK_SETUP 1 -#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000 -#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 -#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 -#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000 -#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000 -#define USBCLKSEL_Val 0x00000000 // Reset: 0x000 -#define USBCLKDIV_Val 0x00000001 // Reset: 0x001 - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - -#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) - #error "USBPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF)) - #error "USBPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1)) - #error "USBCLKSEL: Value out of range!" -#endif - -#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255)) - #error "USBCLKDIV: Value out of range!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" - #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - -#else - #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint32_t wdt_osc = 0; - - /* Determine clock frequency according to clock register values */ - switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 0; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; - } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - - switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* Input Clock to System PLL */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; - break; - case 2: /* Reserved */ - case 3: /* Reserved */ - SystemCoreClock = 0; - break; - } - break; - case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; - break; - case 3: /* System PLL Clock Out */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = __IRC_OSC_CLK; - } else { - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 1: /* System oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = __SYS_OSC_CLK; - } else { - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 2: /* Reserved */ - case 3: /* Reserved */ - SystemCoreClock = 0; - break; - } - break; - } - - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) { - volatile uint32_t i; - -#if (CLOCK_SETUP) /* Clock Setup */ - -#if ((SYSPLLCLKSEL_Val & 0x03) == 1) - LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */ - LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ - LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ -#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif - -#if (((MAINCLKSEL_Val & 0x03) == 2) ) - LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ - LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->MAINCLKUEN = 0x01; - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ - - LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; - -#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */ - LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ - -#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */ - LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ - LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ - LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ - LPC_SYSCON->USBPLLCLKUEN = 0x01; - while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ - LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; - while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ - LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ -#endif - - LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */ - LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */ - -#else /* USB clock is not used */ - LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ - LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ -#endif - -#endif - - /* System clock to the IOCON needs to be enabled or - most of the I/O related peripherals won't work. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); - -} diff --git a/hw/mcu/nxp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.c b/hw/mcu/nxp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.c deleted file mode 100644 index e867fcd4b..000000000 --- a/hw/mcu/nxp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.c +++ /dev/null @@ -1,819 +0,0 @@ -/**************************************************************************** - * $Id:: gpio.c 6172 2011-01-13 18:22:51Z usb00423 $ - * Project: NXP LPC11Uxx GPIO example - * - * Description: - * This file contains GPIO code example which include GPIO - * initialization, GPIO interrupt handler, and related APIs for - * GPIO access. - * - **************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. -****************************************************************************/ -#include "LPC11Uxx.h" /* LPC11Uxx Peripheral Registers */ -#include "lpc11uxx_gpio.h" - -volatile uint32_t flex_int0_counter = 0; -volatile uint32_t flex_int1_counter = 0; -volatile uint32_t flex_int2_counter = 0; -volatile uint32_t flex_int3_counter = 0; -volatile uint32_t flex_int4_counter = 0; -volatile uint32_t flex_int5_counter = 0; -volatile uint32_t flex_int6_counter = 0; -volatile uint32_t flex_int7_counter = 0; -volatile uint32_t gint0_counter = 0; -volatile uint32_t gint1_counter = 0; -volatile uint32_t flex_int0_level_counter = 0; -volatile uint32_t flex_int0_rising_edge_counter = 0; -volatile uint32_t flex_int0_falling_edge_counter = 0; -volatile uint32_t flex_int1_level_counter = 0; -volatile uint32_t flex_int1_rising_edge_counter = 0; -volatile uint32_t flex_int1_falling_edge_counter = 0; -volatile uint32_t flex_int2_level_counter = 0; -volatile uint32_t flex_int2_rising_edge_counter = 0; -volatile uint32_t flex_int2_falling_edge_counter = 0; -volatile uint32_t flex_int3_level_counter = 0; -volatile uint32_t flex_int3_rising_edge_counter = 0; -volatile uint32_t flex_int3_falling_edge_counter = 0; -volatile uint32_t flex_int4_level_counter = 0; -volatile uint32_t flex_int4_rising_edge_counter = 0; -volatile uint32_t flex_int4_falling_edge_counter = 0; -volatile uint32_t flex_int5_level_counter = 0; -volatile uint32_t flex_int5_rising_edge_counter = 0; -volatile uint32_t flex_int5_falling_edge_counter = 0; -volatile uint32_t flex_int6_level_counter = 0; -volatile uint32_t flex_int6_rising_edge_counter = 0; -volatile uint32_t flex_int6_falling_edge_counter = 0; -volatile uint32_t flex_int7_level_counter = 0; -volatile uint32_t flex_int7_rising_edge_counter = 0; -volatile uint32_t flex_int7_falling_edge_counter = 0; -volatile uint32_t gint0_level_counter = 0; -volatile uint32_t gint0_edge_counter = 0; -volatile uint32_t gint1_level_counter = 0; -volatile uint32_t gint1_edge_counter = 0; - -/***************************************************************************** -** Function name: FLEX_INT0_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT0_IRQHandler(void) -{ - flex_int0_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<0) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<0) ) - { - flex_int0_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<0) ) - { - flex_int0_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<0; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<0) ) - { - flex_int0_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<0; - } - LPC_GPIO_PIN_INT->IST = 0x1<<0; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT1_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT1_IRQHandler(void) -{ - flex_int1_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<1) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<1) ) - { - flex_int1_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<1) ) - { - flex_int1_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<1; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<1) ) - { - flex_int1_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<1; - } - LPC_GPIO_PIN_INT->IST = 0x1<<1; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT2_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT2_IRQHandler(void) -{ - flex_int2_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<2) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<2) ) - { - flex_int2_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<2) ) - { - flex_int2_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<2; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<2) ) - { - flex_int2_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<2; - } - LPC_GPIO_PIN_INT->IST = 0x1<<2; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT3_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT3_IRQHandler(void) -{ - flex_int3_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<3) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<3) ) - { - flex_int3_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<3) ) - { - flex_int3_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<3; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<3) ) - { - flex_int3_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<3; - } - LPC_GPIO_PIN_INT->IST = 0x1<<3; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT4_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT4_IRQHandler(void) -{ - flex_int4_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<4) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<4) ) - { - flex_int4_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<4) ) - { - flex_int4_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<4; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<4) ) - { - flex_int4_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<4; - } - LPC_GPIO_PIN_INT->IST = 0x1<<4; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT5_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT5_IRQHandler(void) -{ - flex_int5_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<5) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<5) ) - { - flex_int5_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<5) ) - { - flex_int5_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<5; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<5) ) - { - flex_int5_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<5; - } - LPC_GPIO_PIN_INT->IST = 0x1<<5; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT6_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT6_IRQHandler(void) -{ - flex_int6_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<6) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<6) ) - { - flex_int6_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<6) ) - { - flex_int6_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<6; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<6) ) - { - flex_int6_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<6; - } - LPC_GPIO_PIN_INT->IST = 0x1<<6; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT7_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT7_IRQHandler(void) -{ - flex_int7_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<7) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<7) ) - { - flex_int7_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<7) ) - { - flex_int7_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<7; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<7) ) - { - flex_int7_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<7; - } - LPC_GPIO_PIN_INT->IST = 0x1<<7; - } - } - return; -} - -/***************************************************************************** -** Function name: GINT0_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void GINT0_IRQHandler(void) -{ - gint0_counter++; - if ( LPC_GPIO_GROUP_INT0->CTRL & 0x1 ) - { - if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<4) ) - { - gint0_level_counter++; - } - else - { - gint0_edge_counter++; - } - LPC_GPIO_GROUP_INT0->CTRL |= 0x1; - } - return; -} - -/***************************************************************************** -** Function name: GINT1_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void GINT1_IRQHandler(void) -{ - gint1_counter++; - if ( LPC_GPIO_GROUP_INT1->CTRL & 0x1 ) - { - if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<4) ) - { - gint1_level_counter++; - } - else - { - gint1_edge_counter++; - } - LPC_GPIO_GROUP_INT1->CTRL |= 0x1; - } - return; -} - -/***************************************************************************** -** Function name: GPIOInit -** -** Descriptions: Initialize GPIO, install the -** GPIO interrupt handler -** -** parameters: None -** -** Returned value: true or false, return false if the VIC table -** is full and GPIO interrupt handler can be -** installed. -** -*****************************************************************************/ -void GPIOInit( void ) -{ - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - /* Enable AHB clock to the FlexInt, GroupedInt domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24)); - - return; -} - -/***************************************************************************** -** Function name: GPIOSetFlexInterrupt -** -** Descriptions: Set interrupt sense, event, etc. -** sense: edge or level, 0 is edge, 1 is level -** event/polarity: 0 is active low/falling, 1 is high/rising. -** -** parameters: channel #, port #, bit position, sense, event(polarity) -** -** Returned value: None -** -*****************************************************************************/ -void GPIOSetFlexInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi, - uint32_t sense, uint32_t event ) -{ - switch ( channelNum ) - { - case CHANNEL0: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[0] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[0] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT0_IRQn); - break; - case CHANNEL1: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[1] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[1] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT1_IRQn); - break; - case CHANNEL2: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[2] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[2] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT2_IRQn); - break; - case CHANNEL3: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[3] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[3] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT3_IRQn); - break; - case CHANNEL4: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[4] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[4] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT4_IRQn); - break; - case CHANNEL5: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[5] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[5] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT5_IRQn); - break; - case CHANNEL6: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[6] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[6] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT6_IRQn); - break; - case CHANNEL7: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[7] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[7] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT7_IRQn); - break; - default: - break; - } - if ( sense == 0 ) - { - LPC_GPIO_PIN_INT->ISEL &= ~(0x1<IENF |= (0x1<IENR |= (0x1<ISEL |= (0x1<IENR |= (0x1<IENF &= ~(0x1<IENF |= (0x1<ISEL & (0x1<SIENF |= (0x1<SIENR |= (0x1<SIENR |= (0x1<ISEL & (0x1<CIENF |= (0x1<CIENR |= (0x1<CIENR |= (0x1<IST & (0x1<ISEL & (0x1<IST = (1<CTRL &= ~(0x1<<2); /* Edge trigger */ - } - else - { - LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<2); /* Level trigger. */ - } - LPC_GPIO_GROUP_INT0->CTRL |= (logic<<1); - LPC_GPIO_GROUP_INT0->PORT_POL[0] = *((uint32_t *)(eventPattern + 0)); - LPC_GPIO_GROUP_INT0->PORT_POL[1] = *((uint32_t *)(eventPattern + 1)); - LPC_GPIO_GROUP_INT0->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0)); - LPC_GPIO_GROUP_INT0->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1)); - /* as soon as enabled, an edge may be generated */ - /* clear interrupt flag and NVIC pending interrupt to */ - /* workaround the potential edge generated as enabled */ - LPC_GPIO_GROUP_INT0->CTRL |= (1<<0); - NVIC_ClearPendingIRQ(GINT0_IRQn); - NVIC_EnableIRQ(GINT0_IRQn); - break; - case GROUP1: - if ( sense == 0 ) - { - LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<2); /* Edge trigger */ - } - else - { - LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<2); /* Level trigger. */ - } - LPC_GPIO_GROUP_INT1->CTRL |= (logic<<1); - LPC_GPIO_GROUP_INT1->PORT_POL[0] = *((uint32_t *)(eventPattern + 0)); - LPC_GPIO_GROUP_INT1->PORT_POL[1] = *((uint32_t *)(eventPattern + 1)); - LPC_GPIO_GROUP_INT1->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0)); - LPC_GPIO_GROUP_INT1->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1)); - /* as soon as enabled, an edge may be generated */ - /* clear interrupt flag and NVIC pending interrupt to */ - /* workaround the potential edge generated as enabled */ - LPC_GPIO_GROUP_INT1->CTRL |= (1<<0); - NVIC_ClearPendingIRQ(GINT1_IRQn); - NVIC_EnableIRQ(GINT1_IRQn); - break; - default: - break; - } - - return; -} - -/***************************************************************************** -** Function name: GPIOGetPinValue -** -** Descriptions: Read Current state of port pin, PIN register value -** -** parameters: port num, bit position -** Returned value: None -** -*****************************************************************************/ -uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi ) -{ - uint32_t regVal = 0; - - if( bitPosi < 0x20 ) - { - if ( LPC_GPIO->PIN[portNum] & (0x1<PIN[portNum]; - } - return ( regVal ); -} - -/***************************************************************************** -** Function name: GPIOSetBitValue -** -** Descriptions: Set/clear a bit in a specific position -** -** parameters: port num, bit position, bit value -** -** Returned value: None -** -*****************************************************************************/ -void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal ) -{ - if ( bitVal ) - { - LPC_GPIO->SET[portNum] = 1<CLR[portNum] = 1<DIR[portNum] |= (1<DIR[portNum] &= ~(1< -#include "LPC11Uxx.h" -#include "lpc11uxx_uart.h" - -volatile uint32_t UARTStatus; -volatile uint8_t UARTTxEmpty = 1; -volatile uint8_t UARTBuffer[BUFSIZE]; -volatile uint32_t UARTCount = 0; - -/***************************************************************************** -** Function name: UART_IRQHandler -** -** Descriptions: UART interrupt handler -** -** parameters: None -** Returned value: None -** -*****************************************************************************/ -void UART_IRQHandler(void) -{ - uint8_t IIRValue, LSRValue; - uint8_t Dummy = Dummy; - - IIRValue = LPC_USART->IIR; - - IIRValue >>= 1; /* skip pending bit in IIR */ - IIRValue &= 0x07; /* check bit 1~3, interrupt identification */ - if (IIRValue == IIR_RLS) /* Receive Line Status */ - { - LSRValue = LPC_USART->LSR; - /* Receive Line Status */ - if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI)) - { - /* There are errors or break interrupt */ - /* Read LSR will clear the interrupt */ - UARTStatus = LSRValue; - Dummy = LPC_USART->RBR; /* Dummy read on RX to clear - interrupt, then bail out */ - return; - } - if (LSRValue & LSR_RDR) /* Receive Data Ready */ - { - /* If no error on RLS, normal ready, save into the data buffer. */ - /* Note: read RBR will clear the interrupt */ - UARTBuffer[UARTCount++] = LPC_USART->RBR; - if (UARTCount == BUFSIZE) - { - UARTCount = 0; /* buffer overflow */ - } - } - } - else if (IIRValue == IIR_RDA) /* Receive Data Available */ - { - /* Receive Data Available */ - UARTBuffer[UARTCount++] = LPC_USART->RBR; - if (UARTCount == BUFSIZE) - { - UARTCount = 0; /* buffer overflow */ - } - } - else if (IIRValue == IIR_CTI) /* Character timeout indicator */ - { - /* Character Time-out indicator */ - UARTStatus |= 0x100; /* Bit 9 as the CTI error */ - } - else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */ - { - /* THRE interrupt */ - LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if - valid data in U0THR or not */ - if (LSRValue & LSR_THRE) - { - UARTTxEmpty = 1; - } - else - { - UARTTxEmpty = 0; - } - } - return; -} - -#if MODEM_TEST -/***************************************************************************** -** Function name: ModemInit -** -** Descriptions: Initialize UART0 port as modem, setup pin select. -** -** parameters: None -** Returned value: None -** -*****************************************************************************/ -void ModemInit( void ) -{ - LPC_IOCON->PIO2_0 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO2_0 |= 0x01; /* UART DTR */ - LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */ - LPC_IOCON->PIO1_5 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO1_5 |= 0x01; /* UART RTS */ -#if 1 - LPC_IOCON->DSR_LOC = 0; - LPC_IOCON->PIO2_1 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO2_1 |= 0x01; /* UART DSR */ - - LPC_IOCON->DCD_LOC = 0; - LPC_IOCON->PIO2_2 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO2_2 |= 0x01; /* UART DCD */ - - LPC_IOCON->RI_LOC = 0; - LPC_IOCON->PIO2_3 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO2_3 |= 0x01; /* UART RI */ - -#else - LPC_IOCON->DSR_LOC = 1; - LPC_IOCON->PIO3_1 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO3_1 |= 0x01; /* UART DSR */ - - LPC_IOCON->DCD_LOC = 1; - LPC_IOCON->PIO3_2 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO3_2 |= 0x01; /* UART DCD */ - - LPC_IOCON->RI_LOC = 1; - LPC_IOCON->PIO3_3 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO3_3 |= 0x01; /* UART RI */ -#endif - LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */ - return; -} -#endif - -/***************************************************************************** -** Function name: UARTInit -** -** Descriptions: Initialize UART0 port, setup pin select, -** clock, parity, stop bits, FIFO, etc. -** -** parameters: UART baudrate -** Returned value: None -** -*****************************************************************************/ -void UARTInit(uint32_t baudrate) -{ - uint32_t Fdiv; - uint32_t regVal; - - UARTTxEmpty = 1; - UARTCount = 0; - - NVIC_DisableIRQ(UART_IRQn); - - LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */ - LPC_IOCON->PIO0_19 &= ~0x07; - LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */ - /* Enable UART clock */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); - LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */ - - LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ - regVal = LPC_SYSCON->UARTCLKDIV; - - Fdiv = (((SystemCoreClock*LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ; /*baud rate */ - - LPC_USART->DLM = Fdiv / 256; - LPC_USART->DLL = Fdiv % 256; - LPC_USART->LCR = 0x03; /* DLAB = 0 */ - LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ - - /* Read to clear the line status. */ - regVal = LPC_USART->LSR; - - /* Ensure a clean start, no data in either TX or RX FIFO. */ -// CodeRed - added parentheses around comparison in operand of & - while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) ); - while ( LPC_USART->LSR & LSR_RDR ) - { - regVal = LPC_USART->RBR; /* Dump data from RX FIFO */ - } - - /* Enable the UART Interrupt */ - NVIC_EnableIRQ(UART_IRQn); - -#if CONFIG_UART_ENABLE_INTERRUPT==1 -#if CONFIG_UART_ENABLE_TX_INTERRUPT==1 - LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */ -#else - LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */ -#endif -#endif - return; -} - -/***************************************************************************** -** Function name: UARTSend -** -** Descriptions: Send a block of data to the UART 0 port based -** on the data length -** -** parameters: buffer pointer, and data length -** Returned value: None -** -*****************************************************************************/ -void UARTSend(uint8_t *BufferPtr, uint32_t Length) -{ - - while ( Length != 0 ) - { - /* THRE status, contain valid data */ -#if CONFIG_UART_ENABLE_TX_INTERRUPT==1 - /* Below flag is set inside the interrupt handler when THRE occurs. */ - while ( !(UARTTxEmpty & 0x01) ); - LPC_USART->THR = *BufferPtr; - UARTTxEmpty = 0; /* not empty in the THR until it shifts out */ -#else - while ( !(LPC_USART->LSR & LSR_THRE) ); - LPC_USART->THR = *BufferPtr; -#endif - BufferPtr++; - Length--; - } - return; -} - -/****************************************************************************** -** End Of File -******************************************************************************/ diff --git a/hw/mcu/nxp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h b/hw/mcu/nxp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h deleted file mode 100644 index 8b8d2eb86..000000000 --- a/hw/mcu/nxp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h +++ /dev/null @@ -1,55 +0,0 @@ -/***************************************************************************** - * uart.h: Header file for NXP LPC1xxx Family Microprocessors - * - * Copyright(C) 2008, NXP Semiconductor - * All rights reserved. - * - * History - * 2009.12.07 ver 1.00 Preliminary version, first Release - * -******************************************************************************/ -#ifndef __UART_H -#define __UART_H - -#define RS485_ENABLED 0 -#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */ -#define MODEM_TEST 0 - -#define IER_RBR 0x01 -#define IER_THRE 0x02 -#define IER_RLS 0x04 - -#define IIR_PEND 0x01 -#define IIR_RLS 0x03 -#define IIR_RDA 0x02 -#define IIR_CTI 0x06 -#define IIR_THRE 0x01 - -#define LSR_RDR 0x01 -#define LSR_OE 0x02 -#define LSR_PE 0x04 -#define LSR_FE 0x08 -#define LSR_BI 0x10 -#define LSR_THRE 0x20 -#define LSR_TEMT 0x40 -#define LSR_RXFE 0x80 - -#define BUFSIZE 0x40 - -/* RS485 mode definition. */ -#define RS485_NMMEN (0x1<<0) -#define RS485_RXDIS (0x1<<1) -#define RS485_AADEN (0x1<<2) -#define RS485_SEL (0x1<<3) -#define RS485_DCTRL (0x1<<4) -#define RS485_OINV (0x1<<5) - -void ModemInit( void ); -void UARTInit(uint32_t Baudrate); -void UART_IRQHandler(void); -void UARTSend(uint8_t *BufferPtr, uint32_t Length); - -#endif /* end __UART_H */ -/***************************************************************************** -** End Of File -******************************************************************************/ diff --git a/hw/mcu/nxp/lpc11uxx/hal_mcu/hal_lpc11uxx.c b/hw/mcu/nxp/lpc11uxx/hal_mcu/hal_lpc11uxx.c deleted file mode 100644 index 5797d7c5b..000000000 --- a/hw/mcu/nxp/lpc11uxx/hal_mcu/hal_lpc11uxx.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************/ -/*! - @file hal_lpc11uxx.c - @author hathach (tinyusb.org) - - @section LICENSE - - Software License Agreement (BSD License) - - Copyright (c) 2013, hathach (tinyusb.org) - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holders nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - This file is part of the tinyusb stack. -*/ -/**************************************************************************/ - -#include "common/tusb_common.h" -#include "hal.h" - -#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX - -void tusb_hal_int_enable(uint8_t rhport) -{ - (void) rhport; // discard compiler's warning - NVIC_EnableIRQ(USB_IRQn); -} - -void tusb_hal_int_disable(uint8_t rhport) -{ - (void) rhport; // discard compiler's warning - NVIC_DisableIRQ(USB_IRQn); -} - -bool tusb_hal_init(void) -{ - // TODO remove magic number - /* Enable AHB clock to the USB block and USB RAM. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ((0x1<<14) | (0x1<<27)); - LPC_SYSCON->PDRUNCFG &= ~( BIT_(8) | BIT_(10) ); // enable USB PLL & USB transceiver - - /* Pull-down is needed, or internally, VBUS will be floating. This is to - address the wrong status in VBUSDebouncing bit in CmdStatus register. */ - // set PIO0_3 as USB_VBUS - LPC_IOCON->PIO0_3 &= ~0x1F; - LPC_IOCON->PIO0_3 |= (0x01<<0) | (1 << 3); /* Secondary function VBUS */ - - // set PIO0_6 as usb connect - LPC_IOCON->PIO0_6 &= ~0x07; - LPC_IOCON->PIO0_6 |= (0x01<<0); /* Secondary function SoftConn */ - - return true; -} - -void USB_IRQHandler(void) -{ - hal_dcd_isr(0); -} - -#endif diff --git a/hw/mcu/nxp/lpc11uxx/hal_mcu/hal_mcu.h b/hw/mcu/nxp/lpc11uxx/hal_mcu/hal_mcu.h deleted file mode 100644 index 7e17fe53a..000000000 --- a/hw/mcu/nxp/lpc11uxx/hal_mcu/hal_mcu.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************/ -/*! - @file hal_lpc11uxx.h - @author hathach (tinyusb.org) - - @section LICENSE - - Software License Agreement (BSD License) - - Copyright (c) 2013, hathach (tinyusb.org) - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holders nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY - EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY - DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND - ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - This file is part of the tinyusb stack. -*/ -/**************************************************************************/ - -#ifndef _TUSB_HAL_MCU_H_ -#define _TUSB_HAL_MCU_H_ - -#include "LPC11Uxx.h" - -#ifdef __cplusplus - extern "C" { -#endif - - -#ifdef __cplusplus - } -#endif - -#endif /* _TUSB_HAL_MCU_H_ */