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https://github.com/hathach/tinyusb.git
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rasc for portenta_c33
This commit is contained in:
hathach
parent
4d1f945096
commit
ec2f2f3523
@ -31,36 +31,9 @@
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extern "C" {
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#endif
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#define LED1 BSP_IO_PORT_01_PIN_07 // Red LED
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#define LED_STATE_ON 1
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#define SW1 BSP_IO_PORT_04_PIN_08 // D12
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#define BUTTON_STATE_ACTIVE 0
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static const ioport_pin_cfg_t board_pin_cfg[] = {
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{ .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
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{ .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
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// USB FS
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{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
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{ .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
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{ .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
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// USB HS
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{ .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
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{ .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
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{ .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
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// ETM Trace
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#ifdef TRACE_ETM
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{ .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
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{ .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
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{ .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
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{ .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
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{ .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
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#endif
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};
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#ifdef __cplusplus
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}
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#endif
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@ -1,25 +0,0 @@
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RAM_START = 0x20000000;
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RAM_LENGTH = 0x80000;
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FLASH_START = 0x00000000;
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FLASH_LENGTH = 0x200000;
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DATA_FLASH_START = 0x08000000;
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DATA_FLASH_LENGTH = 0x2000;
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OPTION_SETTING_START = 0x0100A100;
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OPTION_SETTING_LENGTH = 0x100;
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OPTION_SETTING_S_START = 0x0100A200;
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OPTION_SETTING_S_LENGTH = 0x100;
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ID_CODE_START = 0x00000000;
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ID_CODE_LENGTH = 0x0;
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SDRAM_START = 0x80010000;
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SDRAM_LENGTH = 0x0;
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QSPI_FLASH_START = 0x60000000;
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QSPI_FLASH_LENGTH = 0x4000000;
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OSPI_DEVICE_0_START = 0x68000000;
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OSPI_DEVICE_0_LENGTH = 0x8000000;
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OSPI_DEVICE_1_START = 0x70000000;
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OSPI_DEVICE_1_LENGTH = 0x10000000;
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/* Board has bootloader */
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FLASH_IMAGE_START = 0x10000;
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INCLUDE fsp.ld
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@ -2,62 +2,61 @@
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern "C" {
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#endif
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "board_cfg.h"
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "board_cfg.h"
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
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#define BSP_CFG_HEAP_BYTES (0x1000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (2)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
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#define BSP_CFG_HEAP_BYTES (0x1000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#ifdef __cplusplus
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_CFG_H_ */
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@ -2,10 +2,10 @@
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_R7FA6M5BH3CFC
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#define BSP_MCU_FEATURE_SET ('B')
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#define BSP_ROM_SIZE_BYTES (2097152)
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#define BSP_RAM_SIZE_BYTES (524288)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (176)
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#define BSP_MCU_FEATURE_SET ('B')
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#define BSP_ROM_SIZE_BYTES (2097152)
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#define BSP_RAM_SIZE_BYTES (524288)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (176)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
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@ -5,80 +5,80 @@
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extern "C" {
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#endif
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA6M5 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (16000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 1
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#define BSP_HOCO_HZ (18000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (20000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_MCU_GROUP_RA6M5 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (16000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 1
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#define BSP_HOCO_HZ (18000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (20000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CFG_FLL_ENABLE (0)
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#define BSP_CFG_FLL_ENABLE (0)
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
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#define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
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#if defined(_RA_TZ_SECURE)
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#if defined(_RA_TZ_SECURE)
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#define BSP_TZ_SECURE_BUILD (1)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#elif defined(_RA_TZ_NONSECURE)
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (1)
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#else
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#endif
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#endif
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/* TrustZone Settings */
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#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
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#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
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#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
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/* TrustZone Settings */
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#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
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#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
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#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
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/* CMSIS TrustZone Settings */
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#define SCB_CSR_AIRCR_INIT (1)
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#define SCB_AIRCR_BFHFNMINS_VAL (0)
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#define SCB_AIRCR_SYSRESETREQS_VAL (1)
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#define SCB_AIRCR_PRIS_VAL (0)
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#define TZ_FPU_NS_USAGE (1)
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/* CMSIS TrustZone Settings */
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#define SCB_CSR_AIRCR_INIT (1)
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#define SCB_AIRCR_BFHFNMINS_VAL (0)
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#define SCB_AIRCR_SYSRESETREQS_VAL (1)
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#define SCB_AIRCR_PRIS_VAL (0)
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#define TZ_FPU_NS_USAGE (1)
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#ifndef SCB_NSACR_CP10_11_VAL
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#define SCB_NSACR_CP10_11_VAL (3U)
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#define SCB_NSACR_CP10_11_VAL (3U)
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#endif
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#ifndef FPU_FPCCR_TS_VAL
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#define FPU_FPCCR_TS_VAL (1U)
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#define FPU_FPCCR_TS_VAL (1U)
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#endif
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#define FPU_FPCCR_CLRONRETS_VAL (1)
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#define FPU_FPCCR_CLRONRETS_VAL (1)
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#ifndef FPU_FPCCR_CLRONRET_VAL
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#define FPU_FPCCR_CLRONRET_VAL (1)
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#define FPU_FPCCR_CLRONRET_VAL (1)
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#endif
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/* The C-Cache line size that is configured during startup. */
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/* The C-Cache line size that is configured during startup. */
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#ifndef BSP_CFG_C_CACHE_LINE_SIZE
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#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
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#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
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#endif
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/* Type 1 Peripheral Security Attribution */
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/* Type 1 Peripheral Security Attribution */
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/* Peripheral Security Attribution Register (PSAR) Settings */
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/* Peripheral Security Attribution Register (PSAR) Settings */
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#ifndef BSP_TZ_CFG_PSARB
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#define BSP_TZ_CFG_PSARB (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
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(((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
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@ -146,19 +146,19 @@ extern "C" {
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0xfffffffc) /* Unused */
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#endif
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/* Type 2 Peripheral Security Attribution */
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/* Type 2 Peripheral Security Attribution */
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/* Security attribution for Cache registers. */
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/* Security attribution for Cache registers. */
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#ifndef BSP_TZ_CFG_CSAR
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#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
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#endif
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/* Security attribution for RSTSRn registers. */
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/* Security attribution for RSTSRn registers. */
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#ifndef BSP_TZ_CFG_RSTSAR
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#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
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#endif
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/* Security attribution for registers of LVD channels. */
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/* Security attribution for registers of LVD channels. */
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#ifndef BSP_TZ_CFG_LVDSAR
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#define BSP_TZ_CFG_LVDSAR (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
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@ -166,16 +166,16 @@ extern "C" {
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0xFFFFFFFCU)
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#endif
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/* Security attribution for LPM registers. */
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/* Security attribution for LPM registers. */
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#ifndef BSP_TZ_CFG_LPMSAR
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#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
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#endif
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/* Deep Standby Interrupt Factor Security Attribution Register. */
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/* Deep Standby Interrupt Factor Security Attribution Register. */
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#ifndef BSP_TZ_CFG_DPFSAR
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#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
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#endif
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/* Security attribution for CGC registers. */
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/* Security attribution for CGC registers. */
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#ifndef BSP_TZ_CFG_CGFSAR
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#if BSP_CFG_CLOCKS_SECURE
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/* Protect all CGC registers from Non-secure write access. */
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@ -186,12 +186,12 @@ extern "C" {
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#endif
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#endif
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/* Security attribution for Battery Backup registers. */
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/* Security attribution for Battery Backup registers. */
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#ifndef BSP_TZ_CFG_BBFSAR
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#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
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||||
#endif
|
||||
|
||||
/* Security attribution for registers for IRQ channels. */
|
||||
/* Security attribution for registers for IRQ channels. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARA
|
||||
#define BSP_TZ_CFG_ICUSARA (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
|
||||
@ -213,12 +213,12 @@ extern "C" {
|
||||
0xFFFF0000U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for NMI registers. */
|
||||
/* Security attribution for NMI registers. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARB
|
||||
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for DMAC channels */
|
||||
/* Security attribution for registers for DMAC channels */
|
||||
#ifndef BSP_TZ_CFG_ICUSARC
|
||||
#define BSP_TZ_CFG_ICUSARC (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
|
||||
@ -232,29 +232,29 @@ extern "C" {
|
||||
0xFFFFFF00U)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for SELSR0. */
|
||||
/* Security attribution registers for SELSR0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARD
|
||||
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN0. */
|
||||
/* Security attribution registers for WUPEN0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARE
|
||||
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN1. */
|
||||
/* Security attribution registers for WUPEN1. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARF
|
||||
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Set DTCSTSAR if the Secure program uses the DTC. */
|
||||
/* Set DTCSTSAR if the Secure program uses the DTC. */
|
||||
#if RA_NOT_DEFINED == RA_NOT_DEFINED
|
||||
#define BSP_TZ_CFG_DTC_USED (0U)
|
||||
#define BSP_TZ_CFG_DTC_USED (0U)
|
||||
#else
|
||||
#define BSP_TZ_CFG_DTC_USED (1U)
|
||||
#endif
|
||||
|
||||
/* Security attribution of FLWT and FCKMHZ registers. */
|
||||
/* Security attribution of FLWT and FCKMHZ registers. */
|
||||
#ifndef BSP_TZ_CFG_FSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for nonsecure applications to access FLWT and FCKMHZ. */
|
||||
@ -267,118 +267,123 @@ extern "C" {
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for SRAM registers. */
|
||||
/* Security attribution for SRAM registers. */
|
||||
#ifndef BSP_TZ_CFG_SRAMSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
|
||||
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
|
||||
#define BSP_TZ_CFG_SRAMSAR (\
|
||||
#define BSP_TZ_CFG_SRAMSAR (\
|
||||
1 | \
|
||||
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
|
||||
4 | \
|
||||
0xFFFFFFF8U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for Standby RAM registers. */
|
||||
/* Security attribution for Standby RAM registers. */
|
||||
#ifndef BSP_TZ_CFG_STBRAMSAR
|
||||
#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
|
||||
#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for the DMAC Bus Master MPU settings. */
|
||||
/* Security attribution for the DMAC Bus Master MPU settings. */
|
||||
#ifndef BSP_TZ_CFG_MMPUSARA
|
||||
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
|
||||
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
|
||||
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
|
||||
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
|
||||
#endif
|
||||
|
||||
/* Security Attribution Register A for BUS Control registers. */
|
||||
/* Security Attribution Register A for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARA
|
||||
#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
|
||||
#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Security Attribution Register B for BUS Control registers. */
|
||||
/* Security Attribution Register B for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARB
|
||||
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
|
||||
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Enable Uninitialized Non-Secure Application Fallback. */
|
||||
/* Enable Uninitialized Non-Secure Application Fallback. */
|
||||
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
|
||||
#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
|
||||
#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
|
||||
#endif
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
|
||||
/* Option Function Select Register 1 Security Attribution */
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
|
||||
/* Option Function Select Register 1 Security Attribution */
|
||||
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
|
||||
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
|
||||
#else
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
|
||||
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
|
||||
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
|
||||
|
||||
/* Dual Mode Select Register */
|
||||
/* Dual Mode Select Register */
|
||||
#ifndef BSP_CFG_ROM_REG_DUALSEL
|
||||
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
|
||||
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
|
||||
#endif
|
||||
|
||||
/* Block Protection Register 0 */
|
||||
/* Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS0
|
||||
#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
|
||||
#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 1 */
|
||||
/* Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS1
|
||||
#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
|
||||
#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 2 */
|
||||
/* Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS2
|
||||
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
|
||||
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 3 */
|
||||
/* Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS3
|
||||
#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
|
||||
#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Permanent Block Protection Register 0 */
|
||||
/* Permanent Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS0
|
||||
#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
|
||||
#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 1 */
|
||||
/* Permanent Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS1
|
||||
#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
|
||||
#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 2 */
|
||||
/* Permanent Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS2
|
||||
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
|
||||
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 3 */
|
||||
/* Permanent Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS3
|
||||
#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
|
||||
#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
|
||||
#endif
|
||||
/* Security Attribution for Bank Select Register */
|
||||
#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
|
||||
#define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -1,37 +1,35 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
|
||||
#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */
|
||||
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
|
||||
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
|
||||
#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
|
||||
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */
|
||||
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
|
||||
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
|
||||
#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
|
||||
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
|
||||
#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */
|
||||
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
|
||||
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
|
||||
#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
|
||||
|
||||
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */
|
||||
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
|
||||
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
|
||||
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
|
||||
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */
|
||||
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
|
||||
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
|
||||
#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
|
||||
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
|
||||
#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */
|
||||
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
|
||||
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
|
||||
#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
INCLUDE memory_regions.ld
|
||||
|
||||
/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
|
||||
/*
|
||||
XIP_SECONDARY_SLOT_IMAGE = 1;
|
||||
@ -14,8 +20,6 @@ ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
|
||||
ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
|
||||
DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
|
||||
DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
|
||||
NS_OFFSET_START = DEFINED(NS_OFFSET_START) ? NS_OFFSET_START : 0;
|
||||
NS_IMAGE_OFFSET = DEFINED(PROJECT_NONSECURE) ? NS_OFFSET_START : 0;
|
||||
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
|
||||
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
|
||||
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
|
||||
@ -32,20 +36,21 @@ PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)
|
||||
USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
|
||||
|
||||
__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
|
||||
FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
|
||||
(DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
|
||||
FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
|
||||
__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
|
||||
__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
|
||||
__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
|
||||
__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_NS_START - FLASH_APPLICATION_NSC_LENGTH;
|
||||
__bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
|
||||
__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
|
||||
RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
|
||||
@ -55,7 +60,7 @@ __bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
__bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
|
||||
__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START;
|
||||
__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
|
||||
__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
|
||||
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
|
||||
FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
|
||||
@ -67,30 +72,34 @@ FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
|
||||
LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
|
||||
DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
|
||||
FLASH_LENGTH;
|
||||
OPTION_SETTING_SAS_SIZE = 0x34;
|
||||
OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
|
||||
OPTION_SETTING_LENGTH == 0 ? 0 :
|
||||
OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
ITCM (rx) : ORIGIN = ITCM_START + NS_IMAGE_OFFSET, LENGTH = ITCM_LENGTH
|
||||
DTCM (rwx) : ORIGIN = DTCM_START + NS_IMAGE_OFFSET, LENGTH = DTCM_LENGTH
|
||||
FLASH (rx) : ORIGIN = FLASH_ORIGIN + NS_IMAGE_OFFSET, LENGTH = LIMITED_FLASH_LENGTH
|
||||
RAM (rwx) : ORIGIN = RAM_START + NS_IMAGE_OFFSET, LENGTH = RAM_LENGTH
|
||||
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START + NS_IMAGE_OFFSET, LENGTH = DATA_FLASH_LENGTH
|
||||
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
|
||||
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
|
||||
OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_LENGTH
|
||||
OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = 0x18
|
||||
OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET + 0x34, LENGTH = OPTION_SETTING_LENGTH - 0x34
|
||||
OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_S_LENGTH
|
||||
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
|
||||
ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
|
||||
DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
|
||||
FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
|
||||
RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
|
||||
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
|
||||
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
|
||||
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
|
||||
OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
|
||||
OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
|
||||
OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
|
||||
OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
|
||||
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
GROUP(libgcc.a libc.a libm.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
@ -144,27 +153,6 @@ ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Initialized ITCM data. */
|
||||
.itcm_data :
|
||||
{
|
||||
/* Start of ITCM Secure Trustzone region. */
|
||||
__tz_ITCM_S = ABSOLUTE(ITCM_START);
|
||||
|
||||
/* All ITCM data start */
|
||||
__itcm_data_start__ = .;
|
||||
|
||||
KEEP(*(.itcm_data*))
|
||||
|
||||
/* All ITCM data end */
|
||||
__itcm_data_end__ = .;
|
||||
|
||||
/*
|
||||
* Start of the ITCM Non-Secure Trustzone region.
|
||||
* ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end__, 8192);
|
||||
} > ITCM
|
||||
|
||||
.text :
|
||||
{
|
||||
__tz_FLASH_S = ABSOLUTE(FLASH_START);
|
||||
@ -177,17 +165,17 @@ SECTIONS
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
|
||||
/* Some devices have a gap of code flash between the vector table and ROM Registers.
|
||||
* The flash gap section allows applications to place code and data in this section. */
|
||||
*(.flash_gap*)
|
||||
|
||||
/* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
|
||||
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
|
||||
KEEP(*(.rom_registers*))
|
||||
|
||||
/* Reserving 0x100 bytes of space for ROM registers. */
|
||||
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
|
||||
|
||||
/* Allocate flash write-boundary-aligned
|
||||
* space for sce9 wrapped public keys for mcuboot if the module is used.
|
||||
*/
|
||||
. = ALIGN(128);
|
||||
KEEP(*(.mcuboot_sce9_key*))
|
||||
|
||||
*(.text*)
|
||||
@ -233,16 +221,54 @@ SECTIONS
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
.ARM.extab :
|
||||
. = .;
|
||||
__itcm_data_pre_location = .;
|
||||
|
||||
/* Initialized ITCM data. */
|
||||
/* Aligned to FCACHE2 for RA8. */
|
||||
.itcm_data : ALIGN(16)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
/* Start of ITCM Secure Trustzone region. */
|
||||
__tz_ITCM_S = ABSOLUTE(ITCM_START);
|
||||
|
||||
/* All ITCM data start */
|
||||
__itcm_data_start = .;
|
||||
|
||||
KEEP(*(.itcm_data*))
|
||||
|
||||
/* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* All ITCM data end */
|
||||
__itcm_data_end = .;
|
||||
|
||||
/*
|
||||
* Start of the ITCM Non-Secure Trustzone region.
|
||||
* ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
|
||||
} > ITCM AT > FLASH = 0x00
|
||||
|
||||
/* Addresses exported for ITCM initialization. */
|
||||
__itcm_data_init_start = LOADADDR(.itcm_data);
|
||||
__itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
|
||||
|
||||
ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
|
||||
ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
|
||||
ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
|
||||
|
||||
/* Restore location counter. */
|
||||
/* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
|
||||
/* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
|
||||
. = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
}
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
@ -337,50 +363,76 @@ SECTIONS
|
||||
|
||||
} > RAM AT > FLASH
|
||||
|
||||
/* Start address of the initial values for .dtcm_data. */
|
||||
__dtcm_data_init_start = __etext + __data_end__ - __data_start__;
|
||||
. = .;
|
||||
__dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
/* Initialized DTCM data. */
|
||||
.dtcm_data :
|
||||
/* Aligned to FCACHE2 for RA8. */
|
||||
.dtcm_data : ALIGN(16)
|
||||
{
|
||||
/* Start of DTCM Secure Trustzone region. */
|
||||
__tz_DTCM_S = ABSOLUTE(DTCM_START);
|
||||
|
||||
/* Initialized DTCM data start */
|
||||
__dtcm_data_start__ = .;
|
||||
__dtcm_data_start = .;
|
||||
|
||||
KEEP(*(.dtcm_data*))
|
||||
|
||||
/* Initialized DTCM data end */
|
||||
__dtcm_data_end__ = .;
|
||||
} > DTCM AT > FLASH
|
||||
/* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* Initialized DTCM data end */
|
||||
__dtcm_data_end = .;
|
||||
} > DTCM AT > FLASH = 0x00
|
||||
|
||||
. = __dtcm_data_end;
|
||||
/* Uninitialized DTCM data. */
|
||||
.dtcm_noinit (NOLOAD):
|
||||
/* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
|
||||
.dtcm_bss ALIGN(8) (NOLOAD) :
|
||||
{
|
||||
/* Uninitialized DTCM data start */
|
||||
__dtcm_noinit_start = .;
|
||||
__dtcm_bss_start = .;
|
||||
|
||||
KEEP(*(.dtcm_noinit*))
|
||||
KEEP(*(.dtcm_bss*))
|
||||
|
||||
/* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
|
||||
. = ALIGN(8);
|
||||
|
||||
/* Uninitialized DTCM data end */
|
||||
__dtcm_noinit_end = .;
|
||||
__dtcm_bss_end = .;
|
||||
|
||||
/*
|
||||
* Start of the DTCM Non-Secure Trustzone region.
|
||||
* DTCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
|
||||
* DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
|
||||
*/
|
||||
__tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_noinit_end, 8192);
|
||||
__tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
|
||||
} > DTCM
|
||||
|
||||
/* TrustZone Secure Gateway Stubs Section. */
|
||||
/* Addresses exported for DTCM initialization. */
|
||||
__dtcm_data_init_start = LOADADDR(.dtcm_data);
|
||||
__dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
|
||||
|
||||
/* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */
|
||||
/* 1. Get the address to the next block after the .data section in FLASH. */
|
||||
DATA_END = LOADADDR(.data) + SIZEOF(.data);
|
||||
/* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */
|
||||
SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024);
|
||||
/* 3. Manually specify the start location for .gnu.sgstubs */
|
||||
ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
|
||||
ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
|
||||
ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
|
||||
ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
|
||||
ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
|
||||
ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
|
||||
ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
|
||||
|
||||
/* Restore location counter. */
|
||||
/* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
|
||||
/* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
|
||||
. = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
|
||||
|
||||
/* TrustZone Secure Gateway Stubs Section */
|
||||
|
||||
/* Store location counter for SPI non-retentive sections. */
|
||||
sgstubs_pre_location = .;
|
||||
|
||||
/* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
|
||||
SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
|
||||
.gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
|
||||
{
|
||||
__tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
|
||||
@ -407,8 +459,8 @@ SECTIONS
|
||||
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
|
||||
|
||||
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
|
||||
__qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.qspi_non_retentive : AT (__qspi_flash_code_addr__)
|
||||
__qspi_flash_code_addr__ = sgstubs_pre_location;
|
||||
.qspi_non_retentive : AT(__qspi_flash_code_addr__)
|
||||
{
|
||||
__qspi_non_retentive_start__ = .;
|
||||
KEEP(*(.qspi_non_retentive*))
|
||||
@ -456,8 +508,8 @@ SECTIONS
|
||||
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
|
||||
|
||||
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
|
||||
__ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
|
||||
.ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
|
||||
{
|
||||
__ospi_device_0_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_0_non_retentive*))
|
||||
@ -486,8 +538,8 @@ SECTIONS
|
||||
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
|
||||
|
||||
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
|
||||
__ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
|
||||
.ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
|
||||
{
|
||||
__ospi_device_1_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_1_non_retentive*))
|
||||
@ -527,7 +579,6 @@ SECTIONS
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
PROVIDE(end = .);
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
@ -615,7 +666,6 @@ SECTIONS
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
|
||||
|
||||
25
hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld
Normal file
25
hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld
Normal file
@ -0,0 +1,25 @@
|
||||
|
||||
/* generated memory regions file - do not edit */
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x80000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x200000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x68000000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x8000000;
|
||||
OSPI_DEVICE_1_START = 0x70000000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x10000000;
|
||||
|
||||
/* Board has bootloader */
|
||||
FLASH_IMAGE_START = 0x10000;
|
||||
@ -0,0 +1,240 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<raConfiguration version="9">
|
||||
<generalSettings>
|
||||
<option key="#Board#" value="board.custom"/>
|
||||
<option key="CPU" value="RA6M5"/>
|
||||
<option key="Core" value="CM33"/>
|
||||
<option key="#TargetName#" value="R7FA6M5BH3CFC"/>
|
||||
<option key="#TargetARCHITECTURE#" value="cortex-m33"/>
|
||||
<option key="#DeviceCommand#" value="R7FA6M5BH"/>
|
||||
<option key="#RTOS#" value="_none"/>
|
||||
<option key="#pinconfiguration#" value="R7FA6M5BH3CFC.pincfg"/>
|
||||
<option key="#FSPVersion#" value="5.6.0"/>
|
||||
<option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
|
||||
</generalSettings>
|
||||
<raBspConfiguration>
|
||||
<config id="config.bsp.ra6m5.R7FA6M5BH3CFC">
|
||||
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
|
||||
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
|
||||
<property id="config.bsp.rom_size_bytes_hidden" value="2097152"/>
|
||||
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
|
||||
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
|
||||
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
|
||||
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
|
||||
<property id="config.bsp.irq_count_hidden" value="96"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra6m5">
|
||||
<property id="config.bsp.series" value="config.bsp.series.value"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra6m5.fsp">
|
||||
<property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
|
||||
<property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
|
||||
<property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
|
||||
<property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
|
||||
<property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
|
||||
<property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/>
|
||||
<property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
|
||||
<property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
|
||||
<property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/>
|
||||
<property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/>
|
||||
<property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/>
|
||||
<property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
|
||||
<property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
|
||||
<property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/>
|
||||
<property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
|
||||
<property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
|
||||
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
|
||||
<property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/>
|
||||
<property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
|
||||
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
|
||||
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
|
||||
<property id="config.bsp.fsp.BPS.BPS0" value=""/>
|
||||
<property id="config.bsp.fsp.BPS.BPS1" value=""/>
|
||||
<property id="config.bsp.fsp.BPS.BPS2" value=""/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
|
||||
<property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
|
||||
<property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
|
||||
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16666666"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/>
|
||||
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
|
||||
<property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/>
|
||||
<property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/>
|
||||
<property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="8"/>
|
||||
<property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="4864"/>
|
||||
<property id="config.bsp.fsp.mcu.canfd.afl_rules" value="128"/>
|
||||
<property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="64"/>
|
||||
<property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="5"/>
|
||||
<property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x03F9"/>
|
||||
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
|
||||
<property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="65535"/>
|
||||
</config>
|
||||
<config id="config.bsp.ra">
|
||||
<property id="config.bsp.common.main" value="0x1000"/>
|
||||
<property id="config.bsp.common.heap" value="0x1000"/>
|
||||
<property id="config.bsp.common.vcc" value="3300"/>
|
||||
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
|
||||
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
|
||||
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
|
||||
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
|
||||
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
|
||||
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
|
||||
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
|
||||
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
|
||||
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
|
||||
</config>
|
||||
</raBspConfiguration>
|
||||
<raClockConfiguration>
|
||||
<node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
|
||||
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
|
||||
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
|
||||
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
|
||||
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
|
||||
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
|
||||
<node id="board.clock.pll.div" option="board.clock.pll.div.3"/>
|
||||
<node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/>
|
||||
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
|
||||
<node id="board.clock.pll2.source" option="board.clock.pll2.source.xtal"/>
|
||||
<node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
|
||||
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/>
|
||||
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
|
||||
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
|
||||
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
|
||||
<node id="board.clock.uclk.source" option="board.clock.uclk.source.pll2"/>
|
||||
<node id="board.clock.u60ck.source" option="board.clock.u60ck.source.pll2"/>
|
||||
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
|
||||
<node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
|
||||
<node id="board.clock.cecclk.source" option="board.clock.cecclk.source.disabled"/>
|
||||
<node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
|
||||
<node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
|
||||
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
|
||||
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
|
||||
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
|
||||
<node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
|
||||
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
|
||||
<node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
|
||||
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
|
||||
<node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
|
||||
<node id="board.clock.u60ck.div" option="board.clock.u60ck.div.4"/>
|
||||
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/>
|
||||
<node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.1"/>
|
||||
<node id="board.clock.cecclk.div" option="board.clock.cecclk.div.1"/>
|
||||
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
|
||||
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
|
||||
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
|
||||
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
|
||||
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
|
||||
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
|
||||
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
|
||||
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
|
||||
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
|
||||
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
|
||||
<node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
|
||||
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
|
||||
<node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
|
||||
<node id="board.clock.cecclk.display" option="board.clock.cecclk.display.value"/>
|
||||
</raClockConfiguration>
|
||||
<raComponentSelection>
|
||||
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board Support Package Common Files</description>
|
||||
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>I/O Port</description>
|
||||
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
|
||||
<description>Arm CMSIS Version 6 - Core (M)</description>
|
||||
<originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Custom Board Support Files</description>
|
||||
<originalPack>Renesas.RA_board_custom.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="R7FA6M5BH3CFC" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for R7FA6M5BH3CFC</description>
|
||||
<originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA6M5</description>
|
||||
<originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA6M5 - FSP Data</description>
|
||||
<originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="BSP" condition="" group="ra6m5" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
|
||||
<description>Board support package for RA6M5 - Events</description>
|
||||
<originalPack>Renesas.RA_mcu_ra6m5.5.6.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
<raModuleConfiguration>
|
||||
<module id="module.driver.ioport_on_ioport.0">
|
||||
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
|
||||
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
|
||||
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
</context>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<symbolicName propertyId="p107.symbolic_name" value="LED1"/>
|
||||
<symbolicName propertyId="p408.symbolic_name" value="SW1"/>
|
||||
<pincfg active="true" name="R7FA6M5BH3CFC.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="p107.output.low" configurationId="p107"/>
|
||||
<configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
|
||||
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
|
||||
<configSetting altId="p408.input" configurationId="p408"/>
|
||||
<configSetting altId="p408.gpio_mode.gpio_mode_in" configurationId="p408.gpio_mode"/>
|
||||
<configSetting altId="p408.gpio_pupd.gpio_pupd_ip_up" configurationId="p408.gpio_pupd"/>
|
||||
<configSetting altId="pb01.usbhs0.vbus" configurationId="pb01"/>
|
||||
<configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/>
|
||||
<configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
|
||||
<configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
|
||||
<configSetting altId="usbhs0.mode.device" configurationId="usbhs0.mode"/>
|
||||
<configSetting altId="usbhs0.vbus.pb01" configurationId="usbhs0.vbus"/>
|
||||
</pincfg>
|
||||
</raPinConfiguration>
|
||||
</raConfiguration>
|
||||
@ -1,22 +0,0 @@
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x8000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x40000;
|
||||
DATA_FLASH_START = 0x40100000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x00000000;
|
||||
OPTION_SETTING_LENGTH = 0x0;
|
||||
OPTION_SETTING_S_START = 0x80000000;
|
||||
OPTION_SETTING_S_LENGTH = 0x0;
|
||||
ID_CODE_START = 0x01010018;
|
||||
ID_CODE_LENGTH = 0x20;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x0;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
@ -1,22 +0,0 @@
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x8000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x40000;
|
||||
DATA_FLASH_START = 0x40100000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x00000000;
|
||||
OPTION_SETTING_LENGTH = 0x0;
|
||||
OPTION_SETTING_S_START = 0x80000000;
|
||||
OPTION_SETTING_S_LENGTH = 0x0;
|
||||
ID_CODE_START = 0x01010018;
|
||||
ID_CODE_LENGTH = 0x20;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x0;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
@ -1,22 +0,0 @@
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x20000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x100000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
@ -1,22 +0,0 @@
|
||||
RAM_START = 0x1FFE0000;
|
||||
RAM_LENGTH = 0x40000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x80000;
|
||||
DATA_FLASH_START = 0x40100000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x00000000;
|
||||
OPTION_SETTING_LENGTH = 0x0;
|
||||
OPTION_SETTING_S_START = 0x80000000;
|
||||
OPTION_SETTING_S_LENGTH = 0x0;
|
||||
ID_CODE_START = 0x0100A150;
|
||||
ID_CODE_LENGTH = 0x10;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
@ -1,22 +0,0 @@
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x80000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x200000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x68000000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x8000000;
|
||||
OSPI_DEVICE_1_START = 0x70000000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x10000000;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
Loading…
x
Reference in New Issue
Block a user