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complete the support for correct polling of 1ms 2ms 4ms 8ms
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@ -269,9 +269,9 @@ void test_open_interrupt_hs_interval_8(void)
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pipe_hdl = hcd_pipe_open(dev_addr, &int_edp_interval, TUSB_CLASS_HID);
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p_int_qhd = &ehci_data.device[ pipe_hdl.dev_addr-1].qhd[ pipe_hdl.index ];
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TEST_ASSERT_EQUAL(16, p_int_qhd->interval_ms);
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TEST_ASSERT_EQUAL(255, p_int_qhd->interval_ms);
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TEST_ASSERT_EQUAL(1, count_set_bits(p_int_qhd->interrupt_smask) );
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check_int_endpoint_link( get_period_head(hostid, 16), p_int_qhd);
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check_int_endpoint_link( get_period_head(hostid, 255), p_int_qhd);
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check_int_endpoint_link( get_period_head(hostid, 8) , p_int_qhd);
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}
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@ -524,13 +524,15 @@ void async_list_process_isr(ehci_qhd_t * const async_head)
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// TODO abstract max loop guard for async
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}
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void period_list_process_isr(ehci_qhd_t const * const period_head)
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void period_list_process_isr(uint8_t hostid, uint8_t interval_ms)
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{
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uint8_t max_loop = 0;
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ehci_link_t next_item = period_head->next;
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ehci_link_t next_item = * get_period_head(hostid, interval_ms);
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// TODO abstract max loop guard for period
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while( !next_item.terminate && max_loop < (EHCI_MAX_QHD + EHCI_MAX_ITD + EHCI_MAX_SITD))
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while( !next_item.terminate &&
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!(interval_ms > 1 && align32(next_item.address) == get_period_head(hostid, 1)) &&
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max_loop < (EHCI_MAX_QHD + EHCI_MAX_ITD + EHCI_MAX_SITD))
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{
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switch ( next_item.type )
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{
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@ -641,12 +643,15 @@ void hcd_isr(uint8_t hostid)
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//------------- some QTD/SITD/ITD with IOC set is completed -------------//
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if (int_status & EHCI_INT_MASK_NXP_ASYNC)
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{
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async_list_process_isr(get_async_head(hostid));
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async_list_process_isr( get_async_head(hostid) );
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}
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if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
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{
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period_list_process_isr( get_period_head(hostid, 1) );
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for (uint8_t i=1; i <= EHCI_FRAMELIST_SIZE; i *= 2)
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{
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period_list_process_isr( hostid, i );
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}
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}
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//------------- There is some removed async previously -------------//
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