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https://github.com/hathach/tinyusb.git
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Fix EP0 issue (again)
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fa9a327a71
commit
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@ -86,7 +86,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
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// DMA descriptors shouldn't be placed in ITCM !
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CFG_TUSB_MEM_SECTION dma_desc_t dma_desc[6];
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xfer_ctl_t xfer_status[EP_MAX+1];
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xfer_ctl_t xfer_status[EP_MAX];
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static const tusb_desc_endpoint_t ep0_desc =
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{
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@ -205,29 +205,32 @@ static void dcd_ep_handler(uint8_t ep_ix)
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{
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uint32_t int_status = USBHS->USBHS_DEVEPTISR[ep_ix];
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int_status &= USBHS->USBHS_DEVEPTIMR[ep_ix];
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uint16_t count = (USBHS->USBHS_DEVEPTISR[ep_ix] &
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USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos;
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xfer_ctl_t *xfer = &xfer_status[ep_ix];
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if (ep_ix == 0U)
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{
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static uint8_t ctrl_dir;
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if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI)
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{
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ctrl_dir = (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk) >> USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos;
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// Setup packet should always be 8 bytes. If not, ignore it, and try again.
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if (count == 8)
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{
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uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
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dcd_event_setup_received(0, ptr, true);
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}
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// Acknowledge the interrupt
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// Ack and disable SETUP interrupt
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USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_CTRL_RXSTPIC;
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// Workaround :
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// Clear spurious OUT irq
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USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
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int_status &=~USBHS_DEVEPTISR_RXOUTI;
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USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_RXSTPEC;
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}
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if (int_status & USBHS_DEVEPTISR_RXOUTI)
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{
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uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
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xfer_ctl_t *xfer = &xfer_status[0];
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if (count && xfer->total_len)
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{
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uint16_t remain = xfer->total_len - xfer->queued_len;
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@ -252,14 +255,17 @@ static void dcd_ep_handler(uint8_t ep_ix)
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dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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// Disable the interrupt
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USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
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// Though the host could still send, we don't know.
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// Re-enable SETUP interrupt
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if (ctrl_dir == 1)
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{
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USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
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}
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}
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}
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if (int_status & USBHS_DEVEPTISR_TXINI)
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{
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// Disable the interrupt
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USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
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xfer_ctl_t * xfer = &xfer_status[EP_MAX];
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if ((xfer->total_len != xfer->queued_len))
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{
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// TX not complete
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@ -268,13 +274,17 @@ static void dcd_ep_handler(uint8_t ep_ix)
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{
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// TX complete
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dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
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// Re-enable SETUP interrupt
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if (ctrl_dir == 0)
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{
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USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
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}
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}
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}
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} else
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{
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if (int_status & USBHS_DEVEPTISR_RXOUTI)
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{
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xfer_ctl_t *xfer = &xfer_status[ep_ix];
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if (count && xfer->total_len)
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{
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uint16_t remain = xfer->total_len - xfer->queued_len;
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@ -308,7 +318,6 @@ static void dcd_ep_handler(uint8_t ep_ix)
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{
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// Acknowledge the interrupt
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USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
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xfer_ctl_t * xfer = &xfer_status[ep_ix];;
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if ((xfer->total_len != xfer->queued_len))
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{
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// TX not complete
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@ -466,7 +475,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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if (epnum == 0)
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{
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xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
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// Enable the control endpoint - Endpoint 0
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USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
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// Configure the Endpoint 0 configuration register
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@ -591,8 +599,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_ctl_t * xfer = &xfer_status[epnum];
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if(ep_addr == 0x80)
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xfer = &xfer_status[EP_MAX];
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xfer->buffer = buffer;
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xfer->total_len = total_bytes;
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