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Merge pull request #1765 from hathach/rp2040-host-bulk-comment
Rp2040 host bulk comment
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commit
f24f47d038
@ -84,7 +84,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dev_speed(void)
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return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
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}
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static bool need_pre(uint8_t dev_addr)
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TU_ATTR_ALWAYS_INLINE static inline bool need_pre(uint8_t dev_addr)
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{
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// If this device is different to the speed of the root device
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// (i.e. is a low speed device on a full speed hub) then need pre
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@ -129,7 +129,8 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void)
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if ( ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS )
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{
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TU_LOG(3, "Double Buffered: ");
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}else
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}
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else
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{
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TU_LOG(3, "Single Buffered: ");
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}
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@ -242,7 +243,9 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
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if ( status & USB_INTS_ERROR_DATA_SEQ_BITS )
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{
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usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
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TU_LOG(3, " Seq Error: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(*epx.buffer_control), tu_u32_high16(*epx.buffer_control));
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TU_LOG(3, " Seq Error: [0] = 0x%04u [1] = 0x%04x\r\n",
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tu_u32_low16(*epx.buffer_control),
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tu_u32_high16(*epx.buffer_control));
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panic("Data Seq Error \n");
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}
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@ -325,8 +328,10 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
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ep->wMaxPacketSize = wMaxPacketSize;
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ep->transfer_type = transfer_type;
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pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
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pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
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pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr),
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ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
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pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr),
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ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
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uint dpram_offset = hw_data_offset(ep->hw_data_buf);
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// Bits 0-5 should be 0
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assert(!(dpram_offset & 0b111111));
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@ -434,6 +439,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
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{
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(void) rhport;
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assert(rhport == 0);
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// TODO: Should enumval this register
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switch ( dev_speed() )
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{
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@ -548,7 +554,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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// If a normal transfer (non-interrupt) then initiate using
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// sie ctrl registers. Otherwise interrupt ep registers should
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// already be configured
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if (ep == &epx) {
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if ( ep == &epx )
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{
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hw_endpoint_xfer_start(ep, buffer, buflen);
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// That has set up buffer control, endpoint control etc
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@ -556,10 +563,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
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uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
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(ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
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// Set pre if we are a low speed device on full speed hub
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flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
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(ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS) |
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(need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
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usb_hw->sie_ctrl = flags;
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}else
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{
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@ -47,6 +47,12 @@ TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_lock_update(__unused struc
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static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
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static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
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// if usb hardware is in host mode
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TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
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{
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return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false;
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}
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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@ -69,6 +75,8 @@ void rp2040_usb_init(void)
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// Mux the controller to the onboard usb phy
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usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
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TU_LOG2_INT(sizeof(hw_endpoint_t));
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}
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void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
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@ -81,13 +89,17 @@ void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
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void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
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uint32_t value = 0;
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if (and_mask) {
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if ( and_mask )
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{
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value = *ep->buffer_control & and_mask;
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}
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if (or_mask) {
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if ( or_mask )
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{
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value |= or_mask;
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if (or_mask & USB_BUF_CTRL_AVAIL) {
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if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
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if ( or_mask & USB_BUF_CTRL_AVAIL )
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{
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if ( *ep->buffer_control & USB_BUF_CTRL_AVAIL )
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{
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panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
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}
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*ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
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@ -152,12 +164,14 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo
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// always compute and start with buffer 0
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uint32_t buf_ctrl = prepare_ep_buffer(ep, 0) | USB_BUF_CTRL_SEL;
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// For now: skip double buffered for Device mode, OUT endpoint since
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// For now: skip double buffered for OUT endpoint in Device mode, since
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// host could send < 64 bytes and cause short packet on buffer0
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// NOTE this could happen to Host mode IN endpoint
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// Also, Host mode interrupt endpoint hardware is only single buffered
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bool const force_single = (!(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr)) ||
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((usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && tu_edpt_number(ep->ep_addr) != 0);
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// NOTE: this could happen to Host mode IN endpoint
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// Also, Host mode "interrupt" endpoint hardware is only single buffered,
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// NOTE2: Currently Host bulk is implemented using "interrupt" endpoint
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bool const is_host = is_host_mode();
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bool const force_single = (!is_host && !tu_edpt_dir(ep->ep_addr)) ||
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(is_host && tu_edpt_number(ep->ep_addr) != 0);
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if(ep->remaining_len && !force_single)
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{
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@ -82,19 +82,23 @@ void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
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void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
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TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {
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TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32 (struct hw_endpoint *ep)
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{
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return *ep->buffer_control;
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}
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TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) {
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TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32 (struct hw_endpoint *ep, uint32_t value)
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{
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return _hw_endpoint_buffer_control_update32(ep, 0, value);
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}
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TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) {
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TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32 (struct hw_endpoint *ep, uint32_t value)
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{
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return _hw_endpoint_buffer_control_update32(ep, ~value, value);
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}
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TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) {
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TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32 (struct hw_endpoint *ep, uint32_t value)
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{
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return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
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}
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