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add edpt0_open(), slightly update dtog

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hathach 2024-07-30 21:35:24 +07:00
parent 1cf8e34ae5
commit f4aaad6869
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4 changed files with 62 additions and 52 deletions
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2
src/device/dcd.h
View File

@ -180,7 +180,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
// Configure and enable an ISO endpoint according to descriptor
TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
//--------------------------------------------------------------------+
// Event API (implemented by stack)

74
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
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@ -178,6 +178,8 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
static bool dcd_write_packet_memory_ff(tu_fifo_t *ff, uint16_t dst, uint16_t wNBytes);
static bool dcd_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes);
TU_ATTR_UNUSED static void edpt0_open(uint8_t rhport);
//--------------------------------------------------------------------+
// Inline helper
//--------------------------------------------------------------------+
@ -277,19 +279,7 @@ static void handle_bus_reset(uint8_t rhport) {
// Reset PMA allocation
ep_buf_ptr = FSDEV_BTABLE_BASE + 8 * FSDEV_EP_COUNT;
tusb_desc_endpoint_t ep0_desc = {
.bLength = sizeof(tusb_desc_endpoint_t),
.bDescriptorType = TUSB_DESC_ENDPOINT,
.bEndpointAddress = 0x00,
.bmAttributes = {.xfer = TUSB_XFER_CONTROL},
.wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
.bInterval = 0
};
dcd_edpt_open(rhport, &ep0_desc);
ep0_desc.bEndpointAddress = 0x80;
dcd_edpt_open(rhport, &ep0_desc);
edpt0_open(rhport); // open control endpoint (both IN & OUT)
USB->DADDR = USB_DADDR_EF; // Enable USB Function
}
@ -610,8 +600,32 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
TU_ASSERT(0);
}
// The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
// so I'm using the #define from HAL here, instead.
void edpt0_open(uint8_t rhport) {
(void) rhport;
dcd_ep_alloc(0x0, TUSB_XFER_CONTROL);
dcd_ep_alloc(0x80, TUSB_XFER_CONTROL);
xfer_status[0][0].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
xfer_status[0][0].ep_idx = 0;
xfer_status[0][1].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
xfer_status[0][1].ep_idx = 0;
uint16_t pma_addr0 = dcd_pma_alloc(CFG_TUD_ENDPOINT0_SIZE, false);
uint16_t pma_addr1 = dcd_pma_alloc(CFG_TUD_ENDPOINT0_SIZE, false);
btable_set_addr(0, BTABLE_BUF_RX, pma_addr0);
btable_set_addr(0, BTABLE_BUF_TX, pma_addr1);
uint32_t ep_reg = FSDEV_REG->ep[0].reg & ~USB_EPREG_MASK;
ep_reg |= USB_EP_CONTROL | USB_EP_CTR_RX | USB_EP_CTR_TX;
ep_reg = ep_add_tx_status(ep_reg, USB_EP_TX_NAK);
ep_reg = ep_add_rx_status(ep_reg, USB_EP_RX_NAK);
// no need to explicitly set DTOG bits since we aren't masked DTOG bit
pcd_set_endpoint(USB, 0, ep_reg);
}
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
(void)rhport;
@ -626,9 +640,6 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
// Set type
switch (desc_ep->bmAttributes.xfer) {
case TUSB_XFER_CONTROL:
ep_reg |= USB_EP_CONTROL;
break;
case TUSB_XFER_BULK:
ep_reg |= USB_EP_CONTROL; // FIXME should it be bulk?
break;
@ -718,35 +729,34 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
btable_set_addr(ep_idx, 0, pma_addr);
btable_set_addr(ep_idx, 1, pma_addr2);
pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
return true;
}
bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
{
bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
(void)rhport;
uint8_t const ep_addr = p_endpoint_desc->bEndpointAddress;
uint8_t const ep_addr = desc_ep->bEndpointAddress;
uint8_t const ep_idx = xfer_ctl_ptr(ep_addr)->ep_idx;
uint8_t const dir = tu_edpt_dir(ep_addr);
xfer_ctl_ptr(ep_addr)->max_packet_size = tu_edpt_packet_size(p_endpoint_desc);
xfer_ctl_ptr(ep_addr)->max_packet_size = tu_edpt_packet_size(desc_ep);
pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
pcd_set_ep_address(USB, ep_idx, tu_edpt_number(ep_addr));
pcd_clear_tx_dtog(USB, ep_idx);
pcd_clear_rx_dtog(USB, ep_idx);
uint32_t ep_reg = FSDEV_REG->ep[0].reg & ~USB_EPREG_MASK;
ep_reg |= tu_edpt_number(ep_addr) | USB_EP_ISOCHRONOUS | USB_EP_CTR_RX | USB_EP_CTR_TX;
ep_reg = ep_add_tx_status(ep_reg, USB_EP_TX_DIS);
ep_reg = ep_add_rx_status(ep_reg, USB_EP_RX_DIS);
// no need to explicitly set DTOG bits since we aren't masked DTOG bit
if (dir == TUSB_DIR_IN) {
pcd_rx_dtog(USB, ep_idx);
ep_reg = ep_add_rx_dtog(ep_reg, 1);
} else {
pcd_tx_dtog(USB, ep_idx);
ep_reg = ep_add_tx_dtog(ep_reg, 1);
}
pcd_set_endpoint(USB, ep_idx, ep_reg);
return true;
}

30
src/portable/st/stm32_fsdev/fsdev_common.h
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@ -112,14 +112,6 @@ static volatile uint16_t * const pma = (volatile uint16_t*)USB_PMAADDR;
#endif
typedef struct {
// _va32 fsdev_bus_t EP0R; // 00: USB Endpoint 0 register
// _va32 fsdev_bus_t EP1R; // 04: USB Endpoint 1 register
// _va32 fsdev_bus_t EP2R; // 08: USB Endpoint 2 register
// _va32 fsdev_bus_t EP3R; // 0C: USB Endpoint 3 register
// _va32 fsdev_bus_t EP4R; // 10: USB Endpoint 4 register
// _va32 fsdev_bus_t EP5R; // 14: USB Endpoint 5 register
// _va32 fsdev_bus_t EP6R; // 18: USB Endpoint 6 register
// _va32 fsdev_bus_t EP7R; // 1C: USB Endpoint 7 register
struct {
_va32 fsdev_bus_t reg;
}ep[FSDEV_EP_COUNT];
@ -140,6 +132,22 @@ TU_VERIFY_STATIC(sizeof(fsdev_regs_t) == 0x5C, "Size is not correct");
#define FSDEV_REG ((fsdev_regs_t*) FSDEV_REG_BASE)
#ifndef USB_EPTX_STAT
#define USB_EPTX_STAT 0x0030U
#endif
#ifndef USB_EPRX_STAT
#define USB_EPRX_STAT 0x3000U
#endif
#ifndef USB_EP_DTOG_TX_Pos
#define USB_EP_DTOG_TX_Pos (6U)
#endif
#ifndef USB_EP_DTOG_RX_Pos
#define USB_EP_DTOG_RX_Pos (14U)
#endif
//--------------------------------------------------------------------+
// BTable
//--------------------------------------------------------------------+
@ -244,7 +252,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,
regVal &= USB_EPREG_MASK;
regVal |= bAddr;
regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
pcd_set_endpoint(USBx, bEpIdx,regVal);
pcd_set_endpoint(USBx, bEpIdx, regVal);
}
TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) {
@ -291,11 +299,11 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_add_rx_status(uint32_t reg, uint
}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_add_tx_dtog(uint32_t reg, uint32_t state) {
return reg | ((reg ^ state) & USB_EP_DTOG_TX);
return reg | ((reg ^ (state << USB_EP_DTOG_TX_Pos)) & USB_EP_DTOG_TX);
}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_add_rx_dtog(uint32_t reg, uint32_t state) {
return reg | ((reg ^ state) & USB_EP_DTOG_RX);
return reg | ((reg ^ (state << USB_EP_DTOG_RX_Pos)) & USB_EP_DTOG_RX);
}
/**

8
src/portable/st/stm32_fsdev/fsdev_stm32.h
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@ -202,14 +202,6 @@
#error "FSDEV_REG_BASE not defined"
#endif
#ifndef USB_EPTX_STAT
#define USB_EPTX_STAT 0x0030U
#endif
#ifndef USB_EPRX_STAT
#define USB_EPRX_STAT 0x3000U
#endif
// This checks if the device has "LPM"
#if defined(USB_ISTR_L1REQ)
#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)