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https://github.com/hathach/tinyusb.git
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nxp tdi implement remote wakeup
enhance bus reset, unplugged, suspend, resume detection
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27800f7e4f
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@ -245,7 +245,7 @@ void dcd_init(uint8_t rhport)
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dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
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dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
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dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
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@ -273,8 +273,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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void dcd_remote_wakeup(uint8_t rhport)
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void dcd_remote_wakeup(uint8_t rhport)
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{
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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(void) dcd_reg;
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dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
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// dcd_reg->PORTSC1 =
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}
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}
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void dcd_connect(uint8_t rhport)
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void dcd_connect(uint8_t rhport)
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@ -423,15 +422,42 @@ void dcd_int_handler(uint8_t rhport)
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// disabled interrupt sources
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// disabled interrupt sources
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if (int_status == 0) return;
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if (int_status == 0) return;
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if (int_status & INTR_RESET)
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// Set if the port controller enters the full or high-speed operational state.
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{
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// either from Bus Reset or Suspended state
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bus_reset(rhport);
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if (int_status & INTR_PORT_CHANGE)
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uint32_t speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS;
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{
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dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true);
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// TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1);
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}
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// Reset interrupt is not enabled, we manually check if Port Change is due
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// to connection / disconnection
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if ( dcd_reg->USBSTS & INTR_RESET )
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{
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dcd_reg->USBSTS = INTR_RESET;
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if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS)
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{
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uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS;
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bus_reset(rhport);
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dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true);
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}else
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{
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dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
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}
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}
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else
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{
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// Triggered by resuming from suspended state
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if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) )
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{
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dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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}
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}
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}
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if (int_status & INTR_SUSPEND)
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if (int_status & INTR_SUSPEND)
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{
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{
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// TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1);
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if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
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if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
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{
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{
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// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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@ -443,15 +469,6 @@ void dcd_int_handler(uint8_t rhport)
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}
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}
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}
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}
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// Set if the port controller enters the full or high-speed operational state.
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if (int_status & INTR_PORT_CHANGE)
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{
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if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) )
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{
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dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
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}
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}
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// Make sure we read the latest version of _dcd_data.
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// Make sure we read the latest version of _dcd_data.
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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