Some ST parts (like STM32F74xxx / STM32F75xxx) allow the USB_OTG_HS core to be used with
either an external high-speed ULPI PHY or an internal full-speed-only (12mbps) PHY. Currently
the code assumes than an ULPI PHY is used unless the chip has an internal high-speed PHY
(`#if defined(USB_HS_PHYC)`), with no provision to use the internal FS PHY.
This example code creates USB Audio 2.0 headset device.
Device has two audio interfaces first stereo speaker
with 48kHz stereo stream.
Second interface for microphone with 48kHz mono stream.
This example can be used to start working on audio device.
It can be also used to verify ISO endpoints for boards.
Speaker adaptive clock (bound to SOF).
Microphone for now has asynchronous clock.
Volume and mute control while present are not used for data stream
modification.
Feature unit descriptor size depends on number of channels.
So far only single channel feature unit was present.
This change adds feature unit descriptor for two channels.
OSAL_QUEUE_DEF was not updated while FIFO was changed
to use unmasked pointers.
Two fields that are crucial to new functionality were left
uninitialized resulting in FIFO slowing down in time.
FIFO is limited to 64 bytes yet MCU is capable of transmitting
larger packets provided that FIFO will be filled on the fly
and USB_USB_TXCx_REG_USB_LAST_Msk bit is set after FIFO is
filled with all the data that should be transmitted.
This change allows to use FIFO level warning interrupt to fill
FIFO. When DMA is available it will be used instead of interrupts.
Some function names were changed to better reflect what each function
does.
Closing endpoints can be important when there are alternate
instances. This adds functionality of closing endpoints
similar to what exists in other drivers.
Internal FIFO for each endpoint is limited to 64 bytes.
It is possible to have longer packets if respective FIFO
is read during actual packet transmission.
This change updates receive data path to allow packets (and
endpoint size) larger then 64 bytes.
If DMA is not used yet DMA is setup for reception of big packets.
If DMA is already assigned to some transfer, code enables FIFO level
warning interrupts and tries to read data before FIFO is filled up.
