19 Commits

Author	SHA1	Message	Date
hathach	7ab3da1e03	same70 xplained uart via edbg work with board_test	2020-11-09 01:01:05 +07:00
hathach	ec018fbf4e	clean up jlink default interface	2020-10-08 17:17:37 +07:00
hathach	10d5dac913	update doc	2020-09-04 11:20:09 +07:00
hathach	76fe8ac612	fix samg55 ci build	2020-08-21 12:19:38 +07:00
hathach	50be9d7c3a	mass rename tud/dcd_irq_handler to tud/dcd_init_handler	2020-04-17 12:27:53 +07:00
hathach	dc4bf02dcb	mass rename tud_isr to tud_irq_handler	2020-04-06 17:04:49 +07:00
hathach	5fa1e6e242	hack to undef LITTLE_ENDIAN for samg55	2020-03-11 12:32:29 +07:00
hathach	487b887f80	freertos demo use static only for most optmized sram	2020-03-11 00:09:37 +07:00
hathach	85a3315a99	Adding lwip_webserver to ci ... - buil_al.py skip specific MCU if .skip.MCU_ exists - reduce stm32f070 heap & stack size to compile webserver	2020-03-09 15:51:29 +07:00
hathach	759fa76280	implementing dcd_edpt_open	2019-12-09 21:36:15 +07:00
hathach	bc21714c7e	detect bus reset	2019-11-27 14:49:19 +07:00
hathach	745f0b4521	clean up	2019-11-27 11:02:24 +07:00
hathach	4c9c13c767	add uart sync support	2019-11-26 18:21:46 +07:00
hathach	387384c0d9	fix samg55 with newlib missing end symbol	2019-11-26 17:39:51 +07:00
hathach	c691dc4cb2	update	2019-11-25 10:42:32 +07:00
hathach	58e8265964	usb hw init OK	2019-11-24 23:46:28 +07:00
hathach	8cd19f88b9	clean up	2019-11-04 22:03:31 +07:00
hathach	42b55f6621	clean up	2019-11-04 15:00:44 +07:00
hathach	6baa79b330	board test works	2019-11-04 14:54:04 +07:00