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Commit Graph

446 Commits

Author SHA1 Message Date
Uwe Bonnes
f6660c39a1 Add Stm32F7xxdisco board support files 
Status with examples/device/cdc_msc:
- make BOARD=stm32f723disco        => OK
- make BOARD=stm32f723disco PORT=1 => No Reaction
- make BOARD=stm32f746disco        => OK
- make BOARD=stm32f746disco PORT=1 => Hangs during enumeration
- make BOARD=stm32f769disco        => Hangs during enumeration
 2020-06-30 11:02:38 +02:00
Uwe Bonnes
4b7f848e1f stm32h743nucleo: Enable Log via STLINK-VCP. 2020-06-30 11:01:44 +02:00
hathach
ab75998316 Merge branch 'master' into add-stm-hs 2020-06-30 01:55:57 +07:00
hathach
2dff40236c add kaluga files 2020-06-29 18:40:23 +07:00
hathach
50b569ad1b added esp32s2 kaluga bsp 2020-06-29 16:52:08 +07:00
hathach
667eaa6dd6 fix stm32h743 priority with freeRTOS 2020-06-16 00:03:52 +07:00
hathach
0bfa839ac0 clean up, update other example config 2020-06-15 23:06:17 +07:00
hathach
a347de6e50 revert CFG_TUSB_RHPORT0_MODE to previous way 2020-06-14 18:28:45 +07:00
hathach
e92118635c adding speed detect on bus reset 2020-06-01 13:40:18 +07:00
hathach
5ffba8536d able to detect as hs 2020-05-31 19:41:22 +07:00
hathach
e0490ae786 fix idf usb pin init changes 2020-05-29 13:06:33 +07:00
hathach
227bffe04b adding h743 uart, but not enabled yet since it conflict with OTG_FS2 2020-05-27 01:14:52 +07:00
hathach
0482f0d686 update h743eval with rhport=1 highspeed 2020-05-26 22:15:00 +07:00
hathach
fad088719e merge CFG_TUSB_RHPORT1_MODE into CFG_TUSB_RHPORT0_MODE 
each port is 1 byte for easy maintenance
 2020-05-26 15:21:23 +07:00
hathach
62a746bdc7 wip 2020-05-26 12:18:36 +07:00
hathach
ba9c774a2a board test work fine 2020-05-23 13:29:30 +07:00
hathach
550746097b fix cast-align warning for nuc505 2020-05-18 13:03:41 +07:00
hathach
1a8ce043ed enable -Wcast-align 
suppress vendor sdk driver at board.mk
 2020-05-17 14:24:15 +07:00
Mark Olsson
3c43009278 Add support for stm32f746nucleo board 2020-05-15 10:23:01 +02:00
Jerzy Kasenberg
615369a6eb stm32l476disco: Fix system clock setup 
Code suggested that PLL with MSI is used resulting in 80MHz clock.
When in fact PLL was not configured and system clock was left at MSI 48MHz.

This happens because PLL configuration requires that SysTick interrupt
has interrupt priority level configured correctly.
As it seems ST code intentionally setups variable uwTickPrio to invalid
value and later when it is not setup by user code configuration
of oscillator will fail before PLL is configured.

This simple changes systick priority to some valid value that
allows clock to use PLL.
 2020-05-06 15:13:55 +02:00
Jerzy Kasenberg
d9e534f6f2 stm32l476disco: fix uninitialized filed usage 
Field PLLState was not initialized in RCC_OscInitStruct.PLL in
function SystemClock_Config().
Value is used in HAL_RCC_OscConfig() regardless of oscillator.
In lucky case value would be 0 RCC_PLL_NONE and nothing would
happen.
If value was incorrect following line would end up in assert:
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

If value was valid but no RCC_PLL_NONE pll could be configured
with some other random values.

Setting PLLState to RCC_PLL_NONE eliminates potential problem.
 2020-05-06 14:25:46 +02:00
hathach
94fed7db0e fix esp32 ci adding FREERTOS STATIC to sdkconfig default 2020-04-29 11:31:04 +07:00
hathach
7acdcc2ebc Merge branch 'master' into add-more-example 2020-04-22 19:50:23 +07:00
hathach
1fc7f54a8a
added swo as logger 
tested with feather nrf52840 + jlink
 2020-04-22 19:18:03 +07:00
hathach
afc4042375 add LOGGER option to use rtt 
update example readme for debug log. Update bug template to ask for LOG
as well.
 2020-04-22 17:08:41 +07:00
hathach
e4570c35f7 add uart for ea4357 2020-04-20 00:27:35 +07:00
Ha Thach
1f69807621
Merge pull request #354 from hathach/cxd56-disconnect-connect 
Cxd56 disconnect connect
 2020-04-17 13:12:47 +07:00
hathach
50be9d7c3a
mass rename tud/dcd_irq_handler to tud/dcd_init_handler 2020-04-17 12:27:53 +07:00
hathach
89f99426fc
add code for disconnect/connect (not tested) 2020-04-17 11:48:49 +07:00
hathach
989cca5b1a
update per review 2020-04-17 09:29:02 +07:00
hathach
bb2669fbc0
add dfu generate target for fomu 2020-04-16 22:24:48 +07:00
hathach
a009775745
dcd disconnect/connect for transdimension ip 2020-04-16 16:56:16 +07:00
Ha Thach
04a06ec401
Merge branch 'master' into refactor-irqhandler 2020-04-11 15:49:34 +07:00
hathach
d8d5902ccb change saola-1 led to pin 18 by default 2020-04-10 15:44:50 +07:00
hathach
cefbd9579c add neopixel led strip driver for saola, make saola as an component 2020-04-09 11:02:16 +07:00
hathach
40e23672ff rename hal_dcd_isr to dcd_irq_handler for fomu 2020-04-08 16:47:20 +07:00
hathach
e879ad1e6f move irq from msp430 2020-04-08 16:42:36 +07:00
hathach
8f17945b67 move irq for stm32 synopsys 2020-04-08 16:37:09 +07:00
hathach
9014ca5528 move irq for stm32 fsdev 2020-04-08 16:26:14 +07:00
hathach
fc9170b2c1 clean up 2020-04-08 15:15:52 +07:00
hathach
70df1aff13 add TODO for saola on-board neopixel 2020-04-08 15:00:16 +07:00
hathach
a2dee7fb50 rename saola to saola_1 2020-04-07 23:07:25 +07:00
hathach
6a9f971882 add saola button pin support, esp32 build with board_test 2020-04-07 13:42:48 +07:00
hathach
a344427e3f fix CROSS_COMPILE for esp32s2 2020-04-06 20:39:20 +07:00
hathach
06377a341b add tud_irq_handler() for all lpc ip3511 (13, 15, 11) 2020-04-06 18:00:37 +07:00
hathach
138965d1d1 add tud_irq_handler() to all NUC board 2020-04-06 17:43:56 +07:00
hathach
4179334aca call tud_irq_handler() for all nrf5x board 2020-04-06 17:35:11 +07:00
hathach
dc4bf02dcb mass rename tud_isr to tud_irq_handler 2020-04-06 17:04:49 +07:00
hathach
2d6d298302 move irqhandler to application 
tud_isr() must be called by application to forward the irqhandle to the
stack
 2020-04-06 14:11:45 +07:00
hathach
748cc88769 add saola board.mk 2020-04-03 12:20:06 +07:00