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4a5fee503b
- add ch32v203_ro_1v0 board - CFG_EXAMPLE_MSC_DUAL_READONLY to build msc_dual_lun for ch32v203
55 lines
1.7 KiB
Makefile
55 lines
1.7 KiB
Makefile
# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
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#CROSS_COMPILE ?= riscv32-unknown-elf-
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# Toolchain from https://nucleisys.com/download.php
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#CROSS_COMPILE ?= riscv-nuclei-elf-
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
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CROSS_COMPILE ?= riscv-none-elf-
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CH32_FAMILY = ch32v20x
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SDK_DIR = hw/mcu/wch/ch32v20x
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SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
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include $(TOP)/$(BOARD_PATH)/board.mk
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CPU_CORE ?= rv32imac-ilp32
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CFLAGS += \
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-mcmodel=medany \
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-ffunction-sections \
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-fdata-sections \
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-ffat-lto-objects \
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-flto \
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-DCH32V20x_${MCU_VARIANT} \
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-DCFG_TUSB_MCU=OPT_MCU_CH32V20X \
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-DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \
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LDFLAGS_GCC += \
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-nostdlib -nostartfiles \
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--specs=nosys.specs --specs=nano.specs \
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LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld
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SRC_C += \
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src/portable/wch/dcd_ch32_usbfs.c \
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$(SDK_SRC_DIR)/Core/core_riscv.c \
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$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_gpio.c \
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$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_misc.c \
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$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_rcc.c \
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$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_usart.c \
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SRC_S += $(SDK_SRC_DIR)/Startup/startup_ch32v20x_${MCU_VARIANT}.S
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INC += \
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$(TOP)/$(BOARD_PATH) \
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$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
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FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
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# wch-link is not supported yet in official openOCD yet. We need to either use
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# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
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# 2. compiled from modified source https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
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OPENOCD ?= $(HOME)/app/riscv-openocd-wch/src/openocd
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flash: $(BUILD)/$(PROJECT).elf
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$(OPENOCD) -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "flash write_image $<" -c reset -c exit
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