mirror of
https://github.com/hathach/tinyusb.git
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163 lines
6.2 KiB
C
163 lines
6.2 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LED_PORT GPIOA
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#define LED_PIN GPIO_PIN_4
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#define LED_STATE_ON 1
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// Tamper push-button
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#define BUTTON_PORT GPIOC
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#define BUTTON_PIN GPIO_PIN_13
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#define BUTTON_STATE_ACTIVE 0
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// Need to change jumper setting J7 and J8 from RS-232 to STLink
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#define UART_DEV USART1
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#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
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#define UART_GPIO_PORT GPIOB
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#define UART_GPIO_AF GPIO_AF4_USART1
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#define UART_TX_PIN GPIO_PIN_14
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#define UART_RX_PIN GPIO_PIN_15
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// VBUS Sense detection
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#define OTG_FS_VBUS_SENSE 1
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#define OTG_HS_VBUS_SENSE 0
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// USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
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#define ULPI_PINS \
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{GPIOA, GPIO_PIN_3 }, {GPIOA, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_0 }, {GPIOB, GPIO_PIN_1 }, \
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{GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \
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{GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOH, GPIO_PIN_4 }, {GPIOI, GPIO_PIN_11}
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//--------------------------------------------------------------------+
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// RCC Clock
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//--------------------------------------------------------------------+
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static inline void board_stm32h7_clock_init(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
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RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
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/*!< Supply configuration update enable */
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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// PLL1 for System Clock
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#ifdef TRACE_ETM
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// From H743 eval board manual
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// - ETM can only work at 50 MHz clock by default because ETM signals are shared with other peripherals. If better
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// performance of ETM is required (84 MHz/98 MHz), R217, R230, R231, R234, R236, SB2, SB5, SB8, SB11,
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// SB42, SB57 must be removed to reduce the stub on ETM signals. In this configuration SAI and PDM are not
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// functional and NOR Flash and the address of SRAM are limited on A18.
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// - ETM trace function would be abnormal as SAI_SDB share the same pins with TRACE_D0, and TRACE_D0
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// would be forced high by SAI_SDB. When using ETM trace it is necessary to set ADCDAT1 pin (SAI_SDB signal
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// of the STM32) of audio codec WM8994ECS/R (U22) by software to be tri-state.
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// Since Trace CLK = PLL1 / 3 --> max PLL1 clock is 150Mhz
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RCC_OscInitStruct.PLL.PLLM = 2;
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RCC_OscInitStruct.PLL.PLLN = 24;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 4;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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#else
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// Set PLL1 to 400Mhz
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RCC_OscInitStruct.PLL.PLLM = 5;
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RCC_OscInitStruct.PLL.PLLN = 160;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLQ = 4;
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#endif
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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/* Select PLL as system clock source and configure bus clocks dividers */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 |
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RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
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/* PLL3 for USB Clock */
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PeriphClkInitStruct.PLL3.PLL3M = 25;
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PeriphClkInitStruct.PLL3.PLL3N = 336;
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PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
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PeriphClkInitStruct.PLL3.PLL3P = 2;
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PeriphClkInitStruct.PLL3.PLL3Q = 7;
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PeriphClkInitStruct.PLL3.PLL3R = 2;
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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/*activate CSI clock mondatory for I/O Compensation Cell*/
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__HAL_RCC_CSI_ENABLE() ;
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/* Enable SYSCFG clock mondatory for I/O Compensation Cell */
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__HAL_RCC_SYSCFG_CLK_ENABLE() ;
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/* Enables the I/O Compensation Cell */
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HAL_EnableCompensationCell();
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}
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static inline void board_stm32h7_post_init(void)
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{
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// For this board does nothing
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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