mirror of
https://github.com/hathach/tinyusb.git
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140 lines
5.3 KiB
C
140 lines
5.3 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LED_PORT GPIOB
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#define LED_PIN GPIO_PIN_2
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#define LED_STATE_ON 1
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#define BUTTON_PORT GPIOA
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#define BUTTON_PIN GPIO_PIN_0
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#define BUTTON_STATE_ACTIVE 1
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#define UART_DEV USART2
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#define UART_CLK_EN __HAL_RCC_USART2_CLK_ENABLE
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#define UART_GPIO_PORT GPIOD
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#define UART_GPIO_AF GPIO_AF7_USART2
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#define UART_TX_PIN GPIO_PIN_5
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#define UART_RX_PIN GPIO_PIN_6
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//--------------------------------------------------------------------+
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// RCC Clock
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//--------------------------------------------------------------------+
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
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*
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* If define USB_USE_LSE_MSI_CLOCK enabled:
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* System Clock source = PLL (MSI)
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* SYSCLK(Hz) = 80000000
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* HCLK(Hz) = 80000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 1
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* APB2 Prescaler = 2
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* MSI Frequency(Hz) = 4800000
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* LSE Frequency(Hz) = 32768
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* PLL_M = 6
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* PLL_N = 40
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* PLL_P = 7
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* PLL_Q = 4
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* PLL_R = 4
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* Flash Latency(WS) = 4
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* @param None
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* @retval None
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*/
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static inline void board_clock_init(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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/* Enable the LSE Oscillator */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
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HAL_RCCEx_DisableLSECSS();
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/* Set tick interrupt priority, default HAL value is intentionally invalid
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and that prevents PLL initialization in HAL_RCC_OscConfig() */
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HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
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/* Enable MSI Oscillator and activate PLL with MSI as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLM = 6;
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RCC_OscInitStruct.PLL.PLLN = 40;
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RCC_OscInitStruct.PLL.PLLP = 7;
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RCC_OscInitStruct.PLL.PLLQ = 4;
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RCC_OscInitStruct.PLL.PLLR = 4;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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/* Enable MSI Auto-calibration through LSE */
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HAL_RCCEx_EnableMSIPLLMode();
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/* Select MSI output as USB clock source */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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}
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static inline void board_vbus_sense_init(void)
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{
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// L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others
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// Disable VBUS Sense and force device mode
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USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
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USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */
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