285 lines
13 KiB
C
285 lines
13 KiB
C
/**************************************************************************//**
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* @file CM3DS_MPS2.h
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* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
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* Device CM3DS_MPS2
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* @version V3.01
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* @date 06. March 2012
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*
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* @note
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* Copyright (C) 2010-2017 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef CM3DS_MPS2_H
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#define CM3DS_MPS2_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup CM3DS_MPS2_Definitions CM3DS_MPS2 Definitions
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This file defines all structures and symbols for CM3DS_MPS2:
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- registers and bitfields
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- peripheral base address
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- peripheral ID
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- Peripheral definitions
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@{
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*/
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#include <stdint.h>
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/******************************************************************************/
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/* Processor and Core Peripherals */
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/******************************************************************************/
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/** @addtogroup CM3DS_MPS2_CMSIS Device CMSIS Definitions
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Configuration of the Cortex-M3 Processor and Core Peripherals
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@{
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*/
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** CM3DS_MPS2 Specific Interrupt Numbers *******************************************************/
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UARTRX_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
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UARTTX_IRQn = 1, /* Undefined */
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UARTOVR_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
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ACC_IRQn = 3, /* Hardware Accelerator Return Interrupt */
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CAM_IRQn = 4, /* Camera Interrupt */
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M3 Processor and Core Peripherals */
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#define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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/*@}*/ /* end of group CM3DS_MPS2_CMSIS */
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#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
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#include "system_CM3DS.h" /* CM3DS System include file */
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/******************************************************************************/
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/* Device Specific Peripheral registers structures */
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/******************************************************************************/
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/** @addtogroup CM3DS_MPS2_Peripherals CM3DS_MPS2 Peripherals
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CM3DS_MPS2 Device Specific Peripheral registers structures
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@{
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*/
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#if defined ( __CC_ARM )
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#pragma push
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#pragma anon_unions
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#elif defined(__ICCARM__)
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#pragma language=extended
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning 586
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#else
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#warning Not supported compiler type
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#endif
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/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
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typedef struct
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{
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__IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
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__IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
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__IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
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union {
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__I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
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__O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
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};
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__IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
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} UART_TypeDef;
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/* UART DATA Register Definitions */
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#define UART_DATA_Pos 0 /*!< UART_DATA_Pos: DATA Position */
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#define UART_DATA_Msk (0xFFul << UART_DATA_Pos) /*!< UART DATA: DATA Mask */
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#define UART_STATE_RXOR_Pos 3 /*!< UART STATE: RXOR Position */
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#define UART_STATE_RXOR_Msk (0x1ul << UART_STATE_RXOR_Pos) /*!< UART STATE: RXOR Mask */
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#define UART_STATE_TXOR_Pos 2 /*!< UART STATE: TXOR Position */
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#define UART_STATE_TXOR_Msk (0x1ul << UART_STATE_TXOR_Pos) /*!< UART STATE: TXOR Mask */
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#define UART_STATE_RXBF_Pos 1 /*!< UART STATE: RXBF Position */
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#define UART_STATE_RXBF_Msk (0x1ul << UART_STATE_RXBF_Pos) /*!< UART STATE: RXBF Mask */
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#define UART_STATE_TXBF_Pos 0 /*!< UART STATE: TXBF Position */
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#define UART_STATE_TXBF_Msk (0x1ul << UART_STATE_TXBF_Pos ) /*!< UART STATE: TXBF Mask */
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#define UART_CTRL_HSTM_Pos 6 /*!< UART CTRL: HSTM Position */
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#define UART_CTRL_HSTM_Msk (0x01ul << UART_CTRL_HSTM_Pos) /*!< UART CTRL: HSTM Mask */
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#define UART_CTRL_RXORIRQEN_Pos 5 /*!< UART CTRL: RXORIRQEN Position */
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#define UART_CTRL_RXORIRQEN_Msk (0x01ul << UART_CTRL_RXORIRQEN_Pos) /*!< UART CTRL: RXORIRQEN Mask */
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#define UART_CTRL_TXORIRQEN_Pos 4 /*!< UART CTRL: TXORIRQEN Position */
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#define UART_CTRL_TXORIRQEN_Msk (0x01ul << UART_CTRL_TXORIRQEN_Pos) /*!< UART CTRL: TXORIRQEN Mask */
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#define UART_CTRL_RXIRQEN_Pos 3 /*!< UART CTRL: RXIRQEN Position */
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#define UART_CTRL_RXIRQEN_Msk (0x01ul << UART_CTRL_RXIRQEN_Pos) /*!< UART CTRL: RXIRQEN Mask */
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#define UART_CTRL_TXIRQEN_Pos 2 /*!< UART CTRL: TXIRQEN Position */
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#define UART_CTRL_TXIRQEN_Msk (0x01ul << UART_CTRL_TXIRQEN_Pos) /*!< UART CTRL: TXIRQEN Mask */
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#define UART_CTRL_RXEN_Pos 1 /*!< UART CTRL: RXEN Position */
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#define UART_CTRL_RXEN_Msk (0x01ul << UART_CTRL_RXEN_Pos) /*!< UART CTRL: RXEN Mask */
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#define UART_CTRL_TXEN_Pos 0 /*!< UART CTRL: TXEN Position */
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#define UART_CTRL_TXEN_Msk (0x01ul << UART_CTRL_TXEN_Pos) /*!< UART CTRL: TXEN Mask */
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#define UART_INTSTATUS_RXORIRQ_Pos 3 /*!< UART CTRL: RXORIRQ Position */
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#define UART_CTRL_RXORIRQ_Msk (0x01ul << UART_INTSTATUS_RXORIRQ_Pos) /*!< UART CTRL: RXORIRQ Mask */
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#define UART_CTRL_TXORIRQ_Pos 2 /*!< UART CTRL: TXORIRQ Position */
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#define UART_CTRL_TXORIRQ_Msk (0x01ul << UART_CTRL_TXORIRQ_Pos) /*!< UART CTRL: TXORIRQ Mask */
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#define UART_CTRL_RXIRQ_Pos 1 /*!< UART CTRL: RXIRQ Position */
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#define UART_CTRL_RXIRQ_Msk (0x01ul << UART_CTRL_RXIRQ_Pos) /*!< UART CTRL: RXIRQ Mask */
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#define UART_CTRL_TXIRQ_Pos 0 /*!< UART CTRL: TXIRQ Position */
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#define UART_CTRL_TXIRQ_Msk (0x01ul << UART_CTRL_TXIRQ_Pos) /*!< UART CTRL: TXIRQ Mask */
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#define UART_BAUDDIV_Pos 0 /*!< UART BAUDDIV: BAUDDIV Position */
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#define UART_BAUDDIV_Msk (0xFFFFFul << UART_BAUDDIV_Pos) /*!< UART BAUDDIV: BAUDDIV Mask */
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/*------------------- FPGA control ----------------------------------------------*/
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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typedef struct
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{
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volatile uint32_t BTN0;
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} APB_BTN_TypeDef;
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typedef struct
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{
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volatile uint32_t LEDS;
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} APB_LED_TypeDef;
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typedef struct
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{
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volatile uint32_t TIME;
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} APB_TIMER_TypeDef;
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typedef struct
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{
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volatile uint32_t IGNIT;
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} APB_IGNITER_TypeDef;
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/*------------------ SysTick ------------------------------------------------------*/
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typedef struct
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{
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volatile uint32_t CTRL;
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volatile uint32_t LOAD;
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volatile uint32_t VALUE;
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volatile uint32_t CALIB;
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}SysTickType;
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/* -------------------- End of section using anonymous unions ------------------- */
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#if defined ( __CC_ARM )
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#pragma pop
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#elif defined(__ICCARM__)
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/* leave anonymous unions enabled */
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning restore
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#else
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#warning Not supported compiler type
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#endif
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/* Peripheral and SRAM base address */
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#define CM3DS_MPS2_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
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#define CM3DS_MPS2_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
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#define CM3DS_MPS2_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
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#define CM3DS_MPS2_RAM_BASE (0x20000000UL)
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#define CM3DS_MPS2_APB_BASE (0x40000000UL)
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/* SysTick */
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#define SysTick_BASE (0xe000e010UL)
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/* APB peripherals */
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#define APB_LED_BASE (CM3DS_MPS2_APB_BASE + 0x0000UL)
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#define APB_BTN_BASE (CM3DS_MPS2_APB_BASE + 0x1000UL)
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#define APB_UART_BASE (CM3DS_MPS2_APB_BASE + 0x2000UL)
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#define APB_TIME_BASE (CM3DS_MPS2_APB_BASE + 0x3000UL)
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#define APB_IGNITER_BASE (CM3DS_MPS2_APB_BASE + 0x4000UL)
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/******************************************************************************/
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/* Peripheral declaration */
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/******************************************************************************/
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#define SysTick ((SysTickType *) SysTick_BASE )
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#define APB_LED ((APB_LED_TypeDef *) APB_LED_BASE )
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#define APB_BTN ((APB_BTN_TypeDef *) APB_BTN_BASE )
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#define UART ((UART_TypeDef *) APB_UART_BASE )
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#define TIMER ((APB_TIMER_TypeDef *) APB_TIME_BASE )
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#define IGNITER ((APB_IGNITER_TypeDef *) APB_IGNITER_BASE )
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#ifdef __cplusplus
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}
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#endif
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#endif /* CM3DS_MPS2_H */
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