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https://github.com/WangXuan95/FPGA-DDR-SDRAM.git
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update
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WangXuan95
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@ -60,15 +60,15 @@
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* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.
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* - Added tRFC checking during Load Mode and Precharge.
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* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.
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* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
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* JMK 02/11/2005 - Changed the display format for numbers to hex.
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* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
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* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
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* JMK 02/11/2005 - Changed the display format for numbers to hex.
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* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
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* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.
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* - Renamed parameters file with .vh extension.
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* - Renamed parameters file with .vh extension.
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* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb
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* - Added x32 functionality
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* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model
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* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets
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* - Added x32 functionality
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* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model
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* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets
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****************************************************************************************/
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// DO NOT CHANGE THE TIMESCALE, MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
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@ -305,7 +305,7 @@ module micron_ddr_sdram_model #(
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// Burst Length Decode
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wire [3:0] burst_length = 1 << (Mode_reg[2:0]);
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reg [3:0] read_precharge_truncation;
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reg [3:0] read_precharge_truncation;
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// CAS Latency Decode
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wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4];
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@ -485,7 +485,7 @@ module micron_ddr_sdram_model #(
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if (Burst_counter >= burst_length) begin
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Data_in_enable = 1'b0;
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Data_out_enable = 1'b0;
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read_precharge_truncation = 4'h0;
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read_precharge_truncation = 4'h0;
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end
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end
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@ -526,7 +526,7 @@ module micron_ddr_sdram_model #(
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if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
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if (Data_out_enable === 1'b1) begin
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Data_out_enable = 1'b0;
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read_precharge_truncation = 4'hF;
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read_precharge_truncation = 4'hF;
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end
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end
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end
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@ -800,39 +800,39 @@ module micron_ddr_sdram_model #(
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// The device start internal precharge when:
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// 1. Meet tRAS requirement
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// 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command
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if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
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if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
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if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin
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Pc_b0 = 1'b1;
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Act_b0 = 1'b0;
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RP_chk0 = $time;
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Act_b0 = 1'b0;
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RP_chk0 = $time;
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Write_precharge[0] = 1'b0;
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end
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end
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if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
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if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
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Pc_b1 = 1'b1;
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Act_b1 = 1'b0;
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RP_chk1 = $time;
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Write_precharge[1] = 1'b0;
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end
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end
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if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
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if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
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Pc_b2 = 1'b1;
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Act_b2 = 1'b0;
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RP_chk2 = $time;
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Write_precharge[2] = 1'b0;
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end
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end
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if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
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if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
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Pc_b3 = 1'b1;
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Act_b3 = 1'b0;
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RP_chk3 = $time;
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Write_precharge[3] = 1'b0;
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end
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end
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if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
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if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
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Pc_b1 = 1'b1;
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Act_b1 = 1'b0;
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RP_chk1 = $time;
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Write_precharge[1] = 1'b0;
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end
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end
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if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
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if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
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Pc_b2 = 1'b1;
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Act_b2 = 1'b0;
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RP_chk2 = $time;
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Write_precharge[2] = 1'b0;
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end
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end
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if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
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if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
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Pc_b3 = 1'b1;
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Act_b3 = 1'b0;
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RP_chk3 = $time;
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Write_precharge[3] = 1'b0;
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end
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end
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end
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endtask
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@ -1107,7 +1107,7 @@ module micron_ddr_sdram_model #(
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end
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// Record variable for checking violation
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RRD_chk = $time;
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Prev_bank = Ba;
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Prev_bank = Ba;
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read_precharge_truncation[Ba] = 1'b0;
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end
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end
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@ -1264,31 +1264,31 @@ module micron_ddr_sdram_model #(
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$display ("At time %t ERROR: tRAP violation during Read", $time);
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end
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// Interrupt a Read with Auto Precharge (same bank only)
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if (Read_precharge [Ba] === 1'b1) begin
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$display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
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if (!no_halt) $stop (0);
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// Cancel Auto Precharge
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if (Addr[10] === 1'b0) begin
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Read_precharge [Ba]= 1'b0;
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end
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end
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// Activate to Read
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if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
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(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
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$display("At time %t ERROR: Bank is not Activated for Read", $time);
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if (!no_halt) $stop (0);
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end else begin
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// CAS Latency pipeline
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Read_cmnd[cas_latency_x2] = 1'b1;
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Read_bank[cas_latency_x2] = Ba;
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Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
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// Auto Precharge
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if (Addr[10] === 1'b1) begin
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Read_precharge [Ba]= 1'b1;
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Count_precharge [Ba]= 0;
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end
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end
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// Interrupt a Read with Auto Precharge (same bank only)
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if (Read_precharge [Ba] === 1'b1) begin
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$display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
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if (!no_halt) $stop (0);
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// Cancel Auto Precharge
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if (Addr[10] === 1'b0) begin
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Read_precharge [Ba]= 1'b0;
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end
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end
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// Activate to Read
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if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
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(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
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$display("At time %t ERROR: Bank is not Activated for Read", $time);
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if (!no_halt) $stop (0);
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end else begin
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// CAS Latency pipeline
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Read_cmnd[cas_latency_x2] = 1'b1;
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Read_bank[cas_latency_x2] = Ba;
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Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
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// Auto Precharge
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if (Addr[10] === 1'b1) begin
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Read_precharge [Ba]= 1'b1;
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Count_precharge [Ba]= 0;
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end
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end
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end
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// Write Command
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@ -1318,31 +1318,31 @@ module micron_ddr_sdram_model #(
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end
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end
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// Interrupt a Write with Auto Precharge (same bank only)
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if (Write_precharge [Ba] === 1'b1) begin
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$display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
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if (!no_halt) $stop (0);
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// Cancel Auto Precharge
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if (Addr[10] === 1'b0) begin
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Write_precharge [Ba]= 1'b0;
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end
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end
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// Activate to Write
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if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
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(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
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$display("At time %t ERROR: Bank is not Activated for Write", $time);
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if (!no_halt) $stop (0);
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end else begin
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// Pipeline for Write
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Write_cmnd [3] = 1'b1;
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Write_bank [3] = Ba;
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Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
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// Auto Precharge
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if (Addr[10] === 1'b1) begin
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Write_precharge [Ba]= 1'b1;
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Count_precharge [Ba]= 0;
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end
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end
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// Interrupt a Write with Auto Precharge (same bank only)
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if (Write_precharge [Ba] === 1'b1) begin
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$display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
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if (!no_halt) $stop (0);
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// Cancel Auto Precharge
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if (Addr[10] === 1'b0) begin
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Write_precharge [Ba]= 1'b0;
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end
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end
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// Activate to Write
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if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
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(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
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$display("At time %t ERROR: Bank is not Activated for Write", $time);
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if (!no_halt) $stop (0);
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end else begin
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// Pipeline for Write
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Write_cmnd [3] = 1'b1;
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Write_bank [3] = Ba;
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Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
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// Auto Precharge
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if (Addr[10] === 1'b1) begin
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Write_precharge [Ba]= 1'b1;
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Count_precharge [Ba]= 0;
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end
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end
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end
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end
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endtask
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