From 4fb758bbbf6ed1fc242c188af56a42b53c656383 Mon Sep 17 00:00:00 2001 From: WangXuan95 <629708558@qq.com> Date: Fri, 8 Apr 2022 13:49:54 +0800 Subject: [PATCH] update --- SIM/micron_ddr_sdram_model.sv | 178 +++++++++++++++++----------------- 1 file changed, 89 insertions(+), 89 deletions(-) diff --git a/SIM/micron_ddr_sdram_model.sv b/SIM/micron_ddr_sdram_model.sv index a768a2d..1c826f4 100644 --- a/SIM/micron_ddr_sdram_model.sv +++ b/SIM/micron_ddr_sdram_model.sv @@ -60,15 +60,15 @@ * 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate. * - Added tRFC checking during Load Mode and Precharge. * 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences. -* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences. -* JMK 02/11/2005 - Changed the display format for numbers to hex. -* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation. +* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences. +* JMK 02/11/2005 - Changed the display format for numbers to hex. +* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation. * 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error. -* - Renamed parameters file with .vh extension. +* - Renamed parameters file with .vh extension. * 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb -* - Added x32 functionality -* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model -* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets +* - Added x32 functionality +* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model +* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets ****************************************************************************************/ // DO NOT CHANGE THE TIMESCALE, MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION @@ -305,7 +305,7 @@ module micron_ddr_sdram_model #( // Burst Length Decode wire [3:0] burst_length = 1 << (Mode_reg[2:0]); - reg [3:0] read_precharge_truncation; + reg [3:0] read_precharge_truncation; // CAS Latency Decode wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4]; @@ -485,7 +485,7 @@ module micron_ddr_sdram_model #( if (Burst_counter >= burst_length) begin Data_in_enable = 1'b0; Data_out_enable = 1'b0; - read_precharge_truncation = 4'h0; + read_precharge_truncation = 4'h0; end end @@ -526,7 +526,7 @@ module micron_ddr_sdram_model #( if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin if (Data_out_enable === 1'b1) begin Data_out_enable = 1'b0; - read_precharge_truncation = 4'hF; + read_precharge_truncation = 4'hF; end end end @@ -800,39 +800,39 @@ module micron_ddr_sdram_model #( // The device start internal precharge when: // 1. Meet tRAS requirement // 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command - - if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin + + if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin Pc_b0 = 1'b1; - Act_b0 = 1'b0; - RP_chk0 = $time; + Act_b0 = 1'b0; + RP_chk0 = $time; Write_precharge[0] = 1'b0; end end - if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin - if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $time; - Write_precharge[1] = 1'b0; - end - end - if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin - if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $time; - Write_precharge[2] = 1'b0; - end - end - if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin - if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $time; - Write_precharge[3] = 1'b0; - end - end + if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin + if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Write_precharge[1] = 1'b0; + end + end + if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin + if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Write_precharge[2] = 1'b0; + end + end + if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin + if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Write_precharge[3] = 1'b0; + end + end end endtask @@ -1107,7 +1107,7 @@ module micron_ddr_sdram_model #( end // Record variable for checking violation RRD_chk = $time; - Prev_bank = Ba; + Prev_bank = Ba; read_precharge_truncation[Ba] = 1'b0; end end @@ -1264,31 +1264,31 @@ module micron_ddr_sdram_model #( $display ("At time %t ERROR: tRAP violation during Read", $time); end - // Interrupt a Read with Auto Precharge (same bank only) - if (Read_precharge [Ba] === 1'b1) begin - $display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time); - if (!no_halt) $stop (0); - // Cancel Auto Precharge - if (Addr[10] === 1'b0) begin - Read_precharge [Ba]= 1'b0; - end - end - // Activate to Read - if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || - (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin - $display("At time %t ERROR: Bank is not Activated for Read", $time); - if (!no_halt) $stop (0); - end else begin - // CAS Latency pipeline - Read_cmnd[cas_latency_x2] = 1'b1; - Read_bank[cas_latency_x2] = Ba; - Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; - // Auto Precharge - if (Addr[10] === 1'b1) begin - Read_precharge [Ba]= 1'b1; - Count_precharge [Ba]= 0; - end - end + // Interrupt a Read with Auto Precharge (same bank only) + if (Read_precharge [Ba] === 1'b1) begin + $display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time); + if (!no_halt) $stop (0); + // Cancel Auto Precharge + if (Addr[10] === 1'b0) begin + Read_precharge [Ba]= 1'b0; + end + end + // Activate to Read + if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || + (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin + $display("At time %t ERROR: Bank is not Activated for Read", $time); + if (!no_halt) $stop (0); + end else begin + // CAS Latency pipeline + Read_cmnd[cas_latency_x2] = 1'b1; + Read_bank[cas_latency_x2] = Ba; + Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; + // Auto Precharge + if (Addr[10] === 1'b1) begin + Read_precharge [Ba]= 1'b1; + Count_precharge [Ba]= 0; + end + end end // Write Command @@ -1318,31 +1318,31 @@ module micron_ddr_sdram_model #( end end - // Interrupt a Write with Auto Precharge (same bank only) - if (Write_precharge [Ba] === 1'b1) begin - $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time); - if (!no_halt) $stop (0); - // Cancel Auto Precharge - if (Addr[10] === 1'b0) begin - Write_precharge [Ba]= 1'b0; - end - end - // Activate to Write - if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || - (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin - $display("At time %t ERROR: Bank is not Activated for Write", $time); - if (!no_halt) $stop (0); - end else begin - // Pipeline for Write - Write_cmnd [3] = 1'b1; - Write_bank [3] = Ba; - Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; - // Auto Precharge - if (Addr[10] === 1'b1) begin - Write_precharge [Ba]= 1'b1; - Count_precharge [Ba]= 0; - end - end + // Interrupt a Write with Auto Precharge (same bank only) + if (Write_precharge [Ba] === 1'b1) begin + $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time); + if (!no_halt) $stop (0); + // Cancel Auto Precharge + if (Addr[10] === 1'b0) begin + Write_precharge [Ba]= 1'b0; + end + end + // Activate to Write + if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || + (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin + $display("At time %t ERROR: Bank is not Activated for Write", $time); + if (!no_halt) $stop (0); + end else begin + // Pipeline for Write + Write_cmnd [3] = 1'b1; + Write_bank [3] = Ba; + Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; + // Auto Precharge + if (Addr[10] === 1'b1) begin + Write_precharge [Ba]= 1'b1; + Count_precharge [Ba]= 0; + end + end end end endtask