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README.md
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README.md
@ -409,7 +409,7 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据
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| :---- | :--- |
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| tb_ddr_sdram_ctrl.sv | 仿真顶层 |
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| axi_self_test_master.sv | 是 AXI4 主机，通过 AXI4 先把有规律的数据写入 DDR1，然后读回，比较读回的数据是否符合规律，并对不匹配的情况进行计数。 |
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| micron_ddr_sdram_model.v | [MICRON 公司提供的 DDR1 仿真模型](https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b) |
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| micron_ddr_sdram_model.sv | [MICRON 公司提供的 DDR1 仿真模型](https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b) |
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该仿真工程的行为和自测程序一样， axi_self_test_master.sv 作为 AXI4 主机，将有规律的数据写入 DDR1 中，只不过不是全部写入，而是只写入 DDR1 的前 16KB （因为仿真模型的存储空间有限），然后一轮一轮地反复读出数据，比较是否有不匹配的数据，若有，则在 error 信号上产生一个时钟周期的高电平。
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@ -421,23 +421,19 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据
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## 修改仿真参数
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以上仿真默认配置的参数是使用 MT46V64M8 ，即 ROW_BITS=13，COL_BITS=11，DQ_BITS=8。
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以上仿真默认配置的参数是使用 MT46V64M8 ，即 ROW_BITS=13，COL_BITS=11，DQ_BITS=8 。如果想对其它型号的 DDR1 芯片进行仿真，你需要在 tb_ddr_sdram_ctrl.sv 里修改它们。对于 MICRON 公司的 DDR1 系列，这些参数应该这样修改：
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如果想对其它型号的 DDR1 芯片进行仿真，你需要在 tb_ddr_sdram_ctrl.sv 和 micron_ddr_sdram_model.v 里修改它们（注意两个文件要同步修改！）
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对于 MICRON 公司的 DDR1 系列，这些参数应该这样修改：
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| 芯片名称 | BA_BITS | ROW_BITS | COL_BITS | DQ_LEVEL | DQ_BITS
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| :--: | :--: | :--: | :--: | :--: | :--: |
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| MT46V64M4 | 2 | 13 | 11 | 0 | 4 |
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| MT46V128M4 | 2 | 13 | 12 | 0 | 4 |
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| MT46V256M4 | 2 | 14 | 12 | 0 | 4 |
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| MT46V32M8 | 2 | 13 | 10 | 1 | 8 |
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| MT46V64M8 | 2 | 13 | 11 | 1 | 8 |
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| MT46V128M8 | 2 | 14 | 11 | 1 | 8 |
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| MT46V16M16 | 2 | 13 | 9 | 2 | 16 |
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| MT46V32M16 | 2 | 13 | 10 | 2 | 16 |
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| MT46V64M16 | 2 | 14 | 10 | 2 | 16 |
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| 芯片名称 | BA_BITS | ROW_BITS | COL_BITS | DQ_LEVEL |
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| :--: | :--: | :--: | :--: | :--: |
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| MT46V64M4 | 2 | 13 | 11 | 0 |
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| MT46V128M4 | 2 | 13 | 12 | 0 |
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| MT46V256M4 | 2 | 14 | 12 | 0 |
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| MT46V32M8 | 2 | 13 | 10 | 1 |
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| MT46V64M8 | 2 | 13 | 11 | 1 |
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| MT46V128M8 | 2 | 14 | 11 | 1 |
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| MT46V16M16 | 2 | 13 | 9 | 2 |
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| MT46V32M16 | 2 | 13 | 10 | 2 |
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| MT46V64M16 | 2 | 14 | 10 | 2 |
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另外，你可以修改 tb_ddr_sdram_ctrl.sv 的第 18 和 19 行来修改仿真时的突发读写的长度。
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@ -1,11 +1,4 @@
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/****************************************************************************************
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*
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* File Name: ddr.v
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* Version: 6.00
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* Model: BUS Functional
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*
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* Dependencies: ddr_parameters.v
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*
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* Description: Micron SDRAM DDR (Double Data Rate)
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*
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* Limitation: - Doesn't check for 8K-cycle refresh.
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@ -78,23 +71,22 @@
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* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets
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****************************************************************************************/
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// DO NOT CHANGE THE TIMESCALE
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// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
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// DO NOT CHANGE THE TIMESCALE, MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
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`timescale 1ps/1ps
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module micron_ddr_sdram_model (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs);
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`define sg5B
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module micron_ddr_sdram_model #(
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parameter BA_BITS = 2,
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parameter ROW_BITS = 13,
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parameter COL_BITS = 11,
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parameter DQ_LEVEL = 1
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) (
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Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs
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);
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parameter no_halt = 1; // If set to 1, the model won't halt on command sequence/major errors
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parameter DEBUG = 1; // Turn on DEBUG message
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parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits are used
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parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used
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parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
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parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used
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parameter DQ_BITS = 4<<DQ_LEVEL;
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parameter ADDR_BITS = ROW_BITS;
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@ -105,6 +97,8 @@ module micron_ddr_sdram_model (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , A
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parameter DQS_BITS = (DQ_BITS + 4) / 8;
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parameter DM_BITS = DQS_BITS;
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`define sg5B
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`ifdef sg5B // Timing Parameters for -5B (CL = 3)
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parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.4; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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@ -10,11 +10,23 @@
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module tb_ddr_sdram_ctrl();
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// -------------------------------------------------------------------------------------
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// self test error signal, 1'b1 indicates error
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// -------------------------------------------------------------------------------------
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wire error;
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// -----------------------------------------------------------------------------------------------------------------------------
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// simulation control
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// -----------------------------------------------------------------------------------------------------------------------------
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initial $dumpvars(0, tb_ddr_sdram_ctrl);
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initial #200000000 $finish; // simulation for 200us
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initial begin
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#200000000; // simulation for 200us
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if(error)
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$display("*** Error: there are mismatch when read out and compare!!! see wave for detail.");
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else
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$display("validation successful !!");
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$finish;
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end
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// -------------------------------------------------------------------------------------
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// DDR-SDRAM parameters
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@ -23,6 +35,7 @@ localparam BA_BITS = 2;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 11;
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localparam DQ_LEVEL = 1;
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localparam DQ_BITS = (4<<DQ_LEVEL);
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localparam DQS_BITS = ((1<<DQ_LEVEL)+1)/2;
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@ -81,11 +94,6 @@ wire rready;
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wire rlast;
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wire [D_WIDTH-1:0] rdata;
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// -------------------------------------------------------------------------------------
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// self test error signal, 1'b1 indicates error
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// -------------------------------------------------------------------------------------
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wire error;
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// -------------------------------------------------------------------------------------
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// meta AXI4 master for testing
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// -------------------------------------------------------------------------------------
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@ -173,7 +181,12 @@ ddr_sdram_ctrl #(
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// -------------------------------------------------------------------------------------
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// MICRON DDR-SDRAM simulation model
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// -------------------------------------------------------------------------------------
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micron_ddr_sdram_model ddr_model_i (
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micron_ddr_sdram_model #(
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.BA_BITS ( BA_BITS ),
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.ROW_BITS ( ROW_BITS ),
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.COL_BITS ( COL_BITS ),
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.DQ_LEVEL ( DQ_LEVEL )
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) ddr_model_i (
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.Clk ( ddr_ck_p ),
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.Clk_n ( ddr_ck_n ),
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.Cke ( ddr_cke ),
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@ -1,5 +1,5 @@
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del sim.out dump.vcd
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iverilog -g2005-sv -o sim.out tb_ddr_sdram_ctrl.sv axi_self_test_master.sv micron_ddr_sdram_model.v ../RTL/ddr_sdram_ctrl.sv
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iverilog -g2005-sv -o sim.out tb_ddr_sdram_ctrl.sv axi_self_test_master.sv micron_ddr_sdram_model.sv ../RTL/ddr_sdram_ctrl.sv
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vvp -n sim.out
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del sim.out
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pause
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