From d3d1de4fb3c96b79d8dbabdf1a9e0e2926fe9457 Mon Sep 17 00:00:00 2001
From: WangXuan95 <629708558@qq.com>
Date: Fri, 9 Jun 2023 16:12:15 +0800
Subject: [PATCH] change to Verilog2001

---
 RTL/ddr_sdram_ctrl.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/RTL/ddr_sdram_ctrl.v b/RTL/ddr_sdram_ctrl.v
index 113c3c3..5c2bf08 100644
--- a/RTL/ddr_sdram_ctrl.v
+++ b/RTL/ddr_sdram_ctrl.v
@@ -536,7 +536,7 @@ generate if(READ_BUFFER) begin
                 valid <= 1'b1;
         end
 
-    reg [DWIDTH-1:0] mem [(1<<AWIDTH)];
+    reg [DWIDTH-1:0] mem [((1<<AWIDTH)-1) : 0];
 
     always @ (posedge clk)
         if(i_v_e)