FPGA/FPGA-DDR-SDRAM
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change to Verilog2001

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WangXuan95 2023-06-09 16:12:15 +08:00
parent 2c6c3843a8
commit d3d1de4fb3
1 changed files with 1 additions and 1 deletions
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RTL/ddr_sdram_ctrl.v
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@ -536,7 +536,7 @@ generate if(READ_BUFFER) begin
valid <= 1'b1; valid <= 1'b1;
end end
reg [DWIDTH-1:0] mem [(1<<AWIDTH)]; reg [DWIDTH-1:0] mem [((1<<AWIDTH)-1) : 0];
always @ (posedge clk) always @ (posedge clk)
if(i_v_e) if(i_v_e)