FPGA/FPGA-DDR-SDRAM
1
0
Fork 0
mirror of https://github.com/WangXuan95/FPGA-DDR-SDRAM.git synced 2025-02-07 06:44:08 +08:00
Code Issues Projects Releases Wiki Activity

Update README.md

Browse Source
This commit is contained in:
X.Wang 2022-04-11 10:57:43 +08:00 committed by GitHub
parent 4fb758bbbf
commit fa28ae6606
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -399,8 +399,6 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据
# 仿真
## 建立仿真工程
仿真所需要的文件在目录 SIM 里，其中：
| 文件路径 | 用途 |