From ffa1fe041406eed16ab7cc1367900653e1eb1296 Mon Sep 17 00:00:00 2001 From: WangXuan95 <629708558@qq.com> Date: Tue, 6 Jun 2023 19:52:19 +0800 Subject: [PATCH] change to Verilog2001 --- README.md | 945 +++++++++--------- RTL/{ddr_sdram_ctrl.sv => ddr_sdram_ctrl.v} | 173 ++-- ..._test_master.sv => axi_self_test_master.v} | 41 +- ...dram_model.sv => micron_ddr_sdram_model.v} | 0 ..._ddr_sdram_ctrl.sv => tb_ddr_sdram_ctrl.v} | 2 +- SIM/tb_ddr_sdram_ctrl_run_iverilog.bat | 2 +- example-selftest/SignalTap/stp1.stp | 6 +- ..._test_master.sv => axi_self_test_master.v} | 41 +- example-selftest/ddr_test.qsf | 58 +- example-selftest/{top.sv => fpga_top.v} | 6 +- example-uart-read-write/ddr_test.qsf | 15 +- .../{top.sv => fpga_top.v} | 21 +- example-uart-read-write/uart/uart2axi4.v | 295 ++++++ example-uart-read-write/uart/uart_rx.v | 335 +++++++ example-uart-read-write/uart/uart_tx.v | 340 +++++++ example-uart-read-write/uart2axi4.sv | 401 -------- figures/UartSession.png | Bin 22809 -> 8775 bytes 17 files changed, 1645 insertions(+), 1036 deletions(-) rename RTL/{ddr_sdram_ctrl.sv => ddr_sdram_ctrl.v} (81%) rename SIM/{axi_self_test_master.sv => axi_self_test_master.v} (79%) rename SIM/{micron_ddr_sdram_model.sv => micron_ddr_sdram_model.v} (100%) rename SIM/{tb_ddr_sdram_ctrl.sv => tb_ddr_sdram_ctrl.v} (96%) rename example-selftest/{axi_self_test_master.sv => axi_self_test_master.v} (79%) rename example-selftest/{top.sv => fpga_top.v} (97%) rename example-uart-read-write/{top.sv => fpga_top.v} (92%) create mode 100644 example-uart-read-write/uart/uart2axi4.v create mode 100644 example-uart-read-write/uart/uart_rx.v create mode 100644 example-uart-read-write/uart/uart_tx.v delete mode 100644 example-uart-read-write/uart2axi4.sv diff --git a/README.md b/README.md index 7e5d6a3..cc1a37d 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,462 @@ -![语言](https://img.shields.io/badge/语言-systemverilog_(IEEE1800_2005)-CAD09D.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg) +![语言](https://img.shields.io/badge/语言-verilog_(IEEE1364_2001)-9A90FD.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg) -中文 | [English](#en) +[English](#en) | [中文](#cn) -FPGA DDR-SDRAM +　 + +FPGA DDR-SDRAM =========================== +DDR1-SDRAM controller with a AXI4 slave port. + +Replacing SDR-SDRAM with DDR-SDRAM (DDR1) in low-end FPGA designs. + +# Introduction + + |------------------------------| |-----------| + | | | | + ----->| driving clock and reset | | | + | | | | + ------------| | DDR-SDRAM interface |--------->| | + | AXI4 | | | | + AXI4 master |-------->| AXI4 slave | | | + | | | | | + ------------| |------------------------------| |-----------| + User Logic DDR1 Controller (ddr_sdram_ctrl.v) DDR1 chip + +Many low-end FPGA development boards use SDR-SDRAM as off-chip memory, but DDR-SDRAM (DDR1) is larger and less expensive than SDR-SDRAM. And like SDR-SDRAM, DDR1 can also be directly driven by common IO pins of low-end FPGAs. I write a soft core DDR1 controller with a slave AXI4 interface for user. The features of this controller are: + +* **Platform Independent** : Written in pure SystemVerilog and can run on various FPGAs including Altera and Xilinx. +* **Compatible** : Supports DDR1 of various bit widths and capacities (this has been verify by simulation on MICRON's DDR1 models). + +To demonstrate the use of this controller, I provide two demo projects: + +* **Self-test demo** : Through the DDR1 controller, write data into DDR1, then read it out, and compare whether the read data is consistent with the written data. +* **UART DDR1 read/write demo** : Convert UART commands into AXI4 bus actions to read and write DDR1 through the DDR1 controller. + +In addition, since the interface timing of each generation of DDR-SDRAM (such as DDR3, DDR2, DDR1) is similar, this repository can also facilitate those who are familiar with Verilog to learn the DDR-SDRAM interface. + +　 + +# Table of Contents + +* [Hardware Design Guidelines](#Hardware Design Guidelines) +* [Hard Design Example](#Hard Design Example) +* [DDR1 Control Module Manual](#DDR1 Control Module Manual) + * [Module Parameters](#Module Parameters) + * [Module Interface: clock and reset](#Module Interface: clock and reset) + * [Module Interface: DDR1 interface](#Module Interface: DDR1 interface) + * [Module Interface: AXI4 slave](#Module Interface: AXI4 slave) + * [Bit Width Parameters](#Bit Width Parameters) + * [Timing Parameters](#Timing Parameters) +* [FPGA Demo Projects](#FPGA Demo Projects) + * [Self-test demo](#Self-test demo) + * [UART DDR1 read/write demo](#UART DDR1 read/write demo) +* [RTL Simulation](#RTL Simulation) + * [Modify Simulation Attributes](#Modify Simulation Attributes) + +　 + +# Hardware Design Guidelines + +For FPGA selection, only an FPGA with a sufficient number of common IOs can drive DDR1. The IO level standard of DDR1 is often SSTL-2, which is compatible with 2.5V LVTTL or 2.5V LVCMOS, so the power supply of the corresponding FPGA IO bank should be 2.5V, and should be configured as 2.5V LVTTL or 2.5V LVCMOS in the FPGA development software . + +The following table shows the pin defination of the DDR1 chip and the points that should be paid attention to when connecting it to the FPGA. + +| pin name | direction | width | introduction | level | note | +| :----------------------------: | :---------: | :-----------------: | :-------------------------------- | :--------- | :------------------------------- | +| ddr_ck_p | FPGA output | 1 | DDR1 clock p , ≥75MHz | 2.5V LVTTL | differential route with ddr_ck_n | +| ddr_ck_n | FPGA output | 1 | DDR1 clock n , ≥75MHz | 2.5V LVTTL | differential route with ddr_ck_p | +| ddr_cke, ddr_cs_n | FPGA output | 1 | low speed | 2.5V LVTTL | | +| ddr_ras_n, ddr_cas_n, ddr_we_n | FPGA output | 1 | sync with ddr_ck_p's falling edge | 2.5V LVTTL | same length as ddr_ck_p | +| ddr_ba | FPGA output | 2 | sync with ddr_ck_p's falling edge | 2.5V LVTTL | same length as ddr_ck_p | +| ddr_a | FPGA output | depend on DDR1 part | sync with ddr_ck_p's falling edge | 2.5V LVTTL | same length as ddr_ck_p | +| ddr_dqs | inout | depend on DDR1 part | | 2.5V LVTTL | | +| ddr_dm、ddr_dq | inout | depend on DDR1 part | sync with ddr_dqs's double edge | 2.5V LVTTL | same length as ddr_dqs | + +　 + +# Hard Design Example + +For demonstration, I used the cheapest FPGA of Altera Cyclone IV (model: EP4CE6E22C8N) and MICRON's 64MB DDR1 (model MT46V64M8TG-6T) to design a small board. All the demo project of this repository can run on this board directly. If you want to use DDR1 in your own PCB design, just refer to this board's design. + +| ![board-image](./figures/board.jpg) | +| :----------------------------------: | +| **Figure** : FPGA + DDR1 demo board. | + +See board schematic [PCB/sch.pdf](./PCB/sch.pdf) and manufacturing file [PCB/gerber.zip](./PCB/gerber.zip) . It is a double-layer board, and it is not necessary to pay attention to impedance matching like DDR2 and DDR3, because the operating frequency of the circuit is 75MHz on both sides, which is not particularly high. Just pay attention to keeping the distance between FPGA and DDR as close as possible, and the wiring as short as possible. For example, I put the DDR1 chip on the opposite side of the FPGA chip to keep the wiring short. + +The design of this board is open in LCEDA, see [oshwhub.com/wangxuan/fpga-ddr-ce-shi-ban](https://oshwhub.com/wangxuan/fpga-ddr-ce-shi-ban) . + +　 + +# DDR1 Control Module Manual + +See [RTL/ddr_sdram_ctrl.v](./RTL/ddr_sdram_ctrl.v) for the DDR1 controller code, which can automatically initialize DDR1 and refresh it regularly. The module has a AXI4 slave interface through which reads and writes to DDR1 can be accomplished. This section introduce in detail how to use this module. + +## Module Parameters + +Verilog parameters of this module are defined as follows: + +```Verilog +module ddr_sdram_ctrl #( + parameter READ_BUFFER = 1, + parameter BA_BITS = 2, + parameter ROW_BITS = 13, + parameter COL_BITS = 11, + parameter DQ_LEVEL = 1, + parameter [9:0] tREFC = 10'd256, + parameter [7:0] tW2I = 8'd7, + parameter [7:0] tR2I = 8'd7 +) +``` + +These parameters are described in the table below: + +| Parameter | Type | value range | default value | introduction | +| :---------: | :----: | :---------: | :-----------: | :----------------------------------------------------------- | +| READ_BUFFER | | 0 or 1 | 1 | If it is set to 0, there will be no read data buffer in the DDR1 controller, and the read data will not wait for the AXI4 host to accept it, that is, the rvalid signal will not wait for the rready signal, and will be directly poured out at the highest rate. At this time, AXI4 is not Complete, but can reduce the latency of readout. If it is set to 1, there will be a large enough read data buffer in the DDR1 controller, and the rvalid signal will shake hands with the rready signal to confirm that the AXI4 host is ready before reading the data. | +| BA_BITS | Width | 1~4 | 2 | The width of DDR BANK ADDRESS (ddr_ba) is specified. Regular DDR1 BANK ADDRESS is 2bit, so this parameter is usually fixed to the default value and does not need to be changed. | +| ROW_BITS | Width | 1~15 | 13 | It specifies the width of the DDR ROW ADDRESS, and also determines the width of the address line pins (ddr_a) of the DDR1 chip. This parameter depends on the selection of the DDR1 chip. For example, MT46V64M8 has 8192 COLs per bank, considering 2^11=8192, this parameter should be 13. Similarly, for MT46V128M8, this parameter should be 14 | +| COL_BITS | Width | 1~14 | 11 | Specifies the width of the DDR COL ADDRESS. This parameter depends on the selection of the DDR1 chip. For example, MT46V64M8 has 2048 COLs per ROW. Considering 2^11=2048, this parameter should be 11. Similarly, for MT46V32M16, this parameter should be 10. | +| DQ_LEVEL | Width | 0~7 | 1 | The data bit width of the DDR1 chip is specified. For a chip with a bit width of x4 (such as MT46V64M4), this parameter should be 0; for a chip with a bit width of x8 (such as MT46V64M8), this parameter should be 1; for a chip with a bit width of x16 ( For example, MT46V64M16), this parameter should be 2; for the case of bit width x32 (such as two pieces of MT46V64M16 extended bit width), this parameter should be 3; and so on. | +| tREFC | Timing | 1\~1023 | 256 | The controller will refresh DDR1 periodically, and this parameter specifies the refresh interval of DDR1. See [Timing Parameters](#Timing Parameters) for details. | +| tW2I | Timing | 1\~255 | 7 | This parameter specifies the interval from the last write command of a write action to the activation command (ACT) of the next action. See [Timing Parameters](#Timing Parameters) for details. | +| tR2I | Timing | 1\~255 | 7 | This parameter specifies the interval from the last read command of a read action to the activation command (ACT) of the next action. See [Timing Parameters](#Timing Parameters) for details. | + +## Module Interface: clock and reset + +This module requires a drive clock and a drive reset, as follows: + +```Verilog + input wire rstn_async, + input wire drv_clk, +``` + +`rstn_async` is a low-level reset signal and should be set high during normal operation. `drv_clk` is the driving clock, and its frequency is 4 times the user clock. + +Before the module starts working, the `rstn_async` signal should be set low to reset the module, and then set rstn_async high to release the reset. + +### Clock freqency selection + +In this module, the driving clock `drv_clk` is divided by 4 to generate the DDR1 clock (`ddr_ck_p/ddr_ck_n`) and the AXI4 bus user clock (`clk`). This section describes how to determine the frequency of the drive clock `drv_clk`. + +First, the clock frequency is limited by the DDR1 chip. Considering that all DDR1 interface frequencies are at least 75MHz, the lower limit of `drv_clk` is 75\*4=300MHz. + +The upper limit of `drv_clk` also depends on the chip model of DDR1. For example, for MT46V64M8P-5B, check the chip manual, the maximum clock frequency of DDR1 with -5B suffix is 133MHz when CAS Latency (CL)=2, then the upper limit of `drv_clk` is 133 \*4=532MHz. + +> Note: This controller has a fixed CAS Latency (CL) = 2. + +In addition, the upper limit of the clock frequency is also limited by the speed of the FPGA. Too high a clock frequency can easily lead to timing failure. This design fully considers the timing safety design, most registers work in the clk clock domain with a lower frequency; some registers work in a clock that is twice the frequency of the clk clock, and the combinational logic of the input port is very short; Under the `drv_clk` of the frequency, but the input port comes directly from the register output of the upper stage (no combinational logic). Therefore, even on the EP4CE6E22C8N with a very low speed class, the correct operation of the module is guaranteed at a drive clock of 300MHz. + +## Module Interface: DDR1 interface + +Following is the DDR1 interface of this module. These signals should be pinout directly from the FPGA and connected to the DDR1 chip. + +```Verilog + output wire ddr_ck_p, ddr_ck_n, + output wire ddr_cke, + output reg ddr_cs_n, + output reg ddr_ras_n, + output reg ddr_cas_n, + output reg ddr_we_n, + output reg [ BA_BITS-1:0] ddr_ba, + output reg [ ROW_BITS-1:0] ddr_a, + output wire [((1< Note: When the module parameter `READ_BUFFER=0`, the module will save a BRAM resource and also reduce the delay between address channel handshake and data transfer. But the DDR1 controller ignores the `rready=0` condition and does not wait for the AXI4 host to be ready to accept data. This will destroy the completeness of the AXI4 protocol, but it may be useful in some simple situations. + + +## Bit Width Parameters + +This section describes how to determine the 4 parameters: `BA_BITS` , `ROW_BITS` , `COL_BITS` and `DQ_LEVEL`. + +Take [MICRON's DDR-SDRAM](https://www.micron.com/products/dram/ddr-sdram) series chips as an example, different chips have different ROW ADDRESS BITS, COL ADDRESS BITS and DATA BITS, which means that their bit width parameters are also different, as shown in the following table (note: these parameters can be found in the chip datasheet). + +| chip part | ddr_dq width | ddr_dm ddr_dqs width | DQ_LEVEL | BA_BITS | ROW_BITS | COL_BITS | byte per row | total capacity | awaddr/araddr width | +| :--------: | :----------: | :------------------: | :------: | :-----: | :------: | :------: | :----------: | :------------------------- | :-----------------: | +| MT46V64M4 | 4 | 1 | 0 | 2 | 13 | 11 | 1024 | 4\*2^(2+13+11)=256Mb=32MB | 25 | +| MT46V128M4 | 4 | 1 | 0 | 2 | 13 | 12 | 2048 | 4\*2^(2+13+12)=512Mb=64MB | 26 | +| MT46V256M4 | 4 | 1 | 0 | 2 | 14 | 12 | 4096 | 4\*2^(2+14+12)=1Gb=128MB | 27 | +| MT46V32M8 | 8 | 1 | 1 | 2 | 13 | 10 | 1024 | 8\*2^(2+13+10)=256Mb=32MB | 25 | +| MT46V64M8 | 8 | 1 | 1 | 2 | 13 | 11 | 2048 | 8\*2^(2+13+11)=512Mb=64MB | 26 | +| MT46V128M8 | 8 | 1 | 1 | 2 | 14 | 11 | 4096 | 8\*2^(2+14+11)=1Gb=128MB | 27 | +| MT46V16M16 | 16 | 2 | 2 | 2 | 13 | 9 | 1024 | 16\*2^(2+13+9)=256Mb=32MB | 25 | +| MT46V32M16 | 16 | 2 | 2 | 2 | 13 | 10 | 2048 | 16\*2^(2+13+10)=512Mb=64MB | 26 | +| MT46V64M16 | 16 | 2 | 2 | 2 | 14 | 10 | 4096 | 16\*2^(2+14+10)=1Gb=128MB | 27 | + +## Timing Parameters + +This section describes how to determine the 3 timing parameters `tREFC`, `tW2I` and `tR2I`. + +We know that DDR1 requires periodic refresh action, and `tREFC` specifies the refresh clock cycle interval (subject to clk). For example, if the user clock is 75MHz, according to the chip manual of MT46V64M8, it needs to be refreshed once at most 7.8125us. Considering that 75MHz * 7.8125us = 585.9, this parameter can be set to a value less than 585, such as `10'd512`. + +`tW2I` specifies the minimum number of clock cycles (in clk) from the last write command of a write operation to the active command (ACT) of the next operation. The following figure shows a write operation on a DDR1 interface. The first rising edge of ddr_cas_n represents the end of the last write command of a write operation, and the second falling edge of ddr_ras_n represents the next operation (may be read, write, Refresh), there are 5 clock cycles between them, `tW2I` is used to specify the lower limit of the number of cycles. The default value of `tW2I` is `8'd7`, which is a conservative value compatible with most DDR1s. For different DDR1 chips, there are different shrinkage margins (see DDR1 chip datasheet for details). + + __ __ __ __ __ __ __ __ __ __ __ __ + ddr_ck_p __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__ + _____ _______________________________________________ ________ + ddr_ras_n \_____/ \_____/ + _________________ ____________________________________________ + ddr_cas_n \___________/ + _________________ ____________________________________________ + ddr_we_n \___________/ + _____ + ddr_a[10] XXXXXXXXXXXXXXXXXX_____/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + _______________________ + ddr_ba XXXXXX__________BA___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + _______________________ + ddr_a XXXXXX__RA_XXXXXXX_CA0_X_CA1_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +`tR2I` specifies the minimum number of clock cycles (in `clk`) from the last read command of a read operation to the active command (ACT) of the next operation. The figure below shows a read operation on a DDR1 interface. The first rising edge of ddr_cas_n represents the end of the last read command of a read operation, and the second falling edge of ddr_ras_n represents the next operation (may be read, write, Refresh), there are 5 clock cycles between them, `tR2I` is used to specify the lower limit of the number of cycles. The default value of `tR2I` is `8'd7`, which is a conservative value compatible with most DDR1. For different DDR1 chips, there are different shrinkage margins (see DDR1 chip datasheet for details). + + __ __ __ __ __ __ __ __ __ __ __ __ + ddr_ck_p __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__ + _____ _______________________________________________ ________ + ddr_ras_n \_____/ \_____/ + _________________ ____________________________________________ + ddr_cas_n \___________/ + __________________________________________________________________________ + ddr_we_n + _____ + ddr_a[10] XXXXXXXXXXXXXXXXXX_____/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + _______________________ + ddr_ba XXXXXX__________BA___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + _______________________ + ddr_a XXXXXX__RA_XXXXXXX_CA0_X_CA1_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +　 + +# FPGA Demo Projects + +## Self-test demo + +I provide a DDR1 read and write self-test project based on the [FPGA+DDR1 board](#Hardware Design Example) I designed. The project directory is [example-selftest](./example-selftest) , please open it with Quartus. + +This project contains following files: + +| File Name | Introduction | +| :--------------------------------------- | :----------------------------------------------------------- | +| example-selftest/fpga_top.v | top-level module | +| example-selftest/axi_self_test_master.v | AXI4 master. First, write the data into DDR1 through AXI4, and then read back and verify. | +| RTL/ddr_sdram_ctrl.v | DDR1 controller | + +The behavior of the demo project is: + +**Write**: After the project starts running, it will first write the entire DDR1 through AXI4, and directly write the address word to the corresponding address. For example, if the data width of AXI4 is 16bit, then write 0x0001 at address 0x000002. Write 0x3456 at address 0x123456. + +**Read & Error Check**: After writing the entire DDR1, the project will repeatedly read the entire DDR1 round by round. error) to generate a high-level pulse, and the error count signal (error_cnt) +1. If the DDR1 configuration is correct, there should be no error signal. You can measure the pin corresponding to error_cnt, if it is 0 (all low), it means there is no error. + +**SignalTap waveform capture**: This project contains a SignalTap file stp1.stp, which can be used to view the waveform on the DDR1 interface when the program is running. It triggers with error=1, so if there is no error in the read and write self-test, it will not be triggered. Because the project is reading DDR1 at any time, if you want to see the waveform on the DDR1 interface, just press the "Stop" button. + +**Modify AXI4 burst length**: You can modify WBURST_LEN and RBURST_LEN in lines 82 and 83 of fpga_top.v to modify the write/read burst length during self-test. The self-test program only supports 2^n-1 This burst length, ie WBURST_LEN and RBURST_LEN must take values like 0, 1, 3, 7, 15, 31, ... (note that this is only a limitation of the self-test program I wrote, DDR1 controller supports 0 Any burst length between ~255. + +> WBURST_LEN and RBURST_LEN can be set differently. + +## UART DDR1 read/write demo + +I provide a UART read and write project based on the [FPGA+DDR1 board](#Hardware Design Example) I designed. In this project, you can read and write DDR1 with different burst lengths through UART commands. The project directory is [example-uart-read-write](./example-uart-read-write) , please open it with Quartus. + +The project contains the following files: + +| File Name | Introduction | +| :----------------------------------- | :----------------------------------------------------------- | +| example-uart-read-write/fpga_top.v | top-level module | +| example-uart-read-write/uart/uart2axi4.v | an AXI4 master, which can convert the commands received by UART RX into AXI4 read and write operations, and send the data read out by read operations through UART TX. see https://github.com/WangXuan95/Verilog-UART for detail. | +| example-uart-read-write/uart/uart_rx.v | called by uart2axi4.v | +| example-uart-read-write/uart/uart_tx.v | called by uart2axi4.v | +| RTL/ddr_sdram_ctrl.v | DDR1 controller | + +There is a CH340E chip (USB to UART) on the [FPGA+DDR1 board](#Hardware Design Example), so after plugging in the USB cable, you can see the serial port corresponding to the UART on the computer (you need to download and install the driver of CH341 on [www.wch. cn/product/CH340.html](http://www.wch.cn/product/CH340.html) first). + +After the project is programed to FPGA, double-click to open a serial port tool **UartSession.exe** (it is in the [example-uart-read-write](./example-uart-read-write) directory), open the COM port corresponding to the board according to the prompt, and then type the following command + Enter, you can Write the 4 data 0x0123, 0x4567, 0x89ab, and 0xcdef into the starting address 0x12345. (A write operation with a burst length of 4 occurs on the AXI4 bus). + + w12345 0123 4567 89ab cdef + +Then use the following command + enter to read 8 data from the starting address 0x12345. + + r12345 8 + +The effect is as shown in the figure below. The first 4 data (0123 4567 89ab cdef) are what we have written into DDR1, and the last 4 data are random data that comes with DDR1 after initialization. + +| ![](./figures/UartSession.png) | +| :------------------------------------------------------: | +| Figure : Use UartSession.exe to perform DDR1 read/write. | + +The length of the write burst is how much data there is in the write command. For example, the burst length of the following write command is 10, and 10 pieces of data are written to the starting address 0x00000 + + w0 1234 2345 3456 4567 5678 6789 789a 89ab 9abc abcd + +The read command needs to specify the burst length. For example, the burst length of the following command is 30 (0x1e), and 30 data are read from the starting address 0x00000 + + r0 1e + +　 + +# RTL Simulation + +The files required for the simulation are in the [SIM](./SIM) folder, where: + +| File Name | Introduction | +| :------------------------ | :----------------------------------------------------------- | +| tb_ddr_sdram_ctrl.v | Testbench code, simulation top-level. | +| axi_self_test_master.v | AXI4 master. First, write the data into DDR1 through AXI4, and then read back and verify. | +| micron_ddr_sdram_model.v | [MICRON's DDR1 simulation model](https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b) | + +The behavior of the simulation project is the same as that of the self-test program, axi_self_test_master.v, as the AXI4 host, writes regular data into DDR1, but not all of them, only the first 16KB of DDR1 (because the memory spave of the simulation model is limited), and then repeatedly read data round by round to compare whether there is unmatched data, if there is, generate a high level of one clock cycle on the `error` signal. + +Before using iverilog for simulation, you need to install iverilog , see: [iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) + +Then double-click tb_ddr_sdram_ctrl_run_iverilog.bat to run the simulation, and then you can open the generated dump.vcd file to view the waveform. + +## Modify Simulation Attributes + +The default configuration parameters of the above simulation fit MT46V64M8, namely `ROW_BITS=13`, `COL_BITS=11`, and `DQ_BITS=8`. If you want to simulate other DDR1 chips, you need to modify them in tb_ddr_sdram_ctrl.v. For MICRON's DDR1 series, these parameters should be modified as follows: + +| DDR1 part | BA_BITS | ROW_BITS | COL_BITS | DQ_LEVEL | +| :--------: | :-----: | :------: | :------: | :------: | +| MT46V64M4 | 2 | 13 | 11 | 0 | +| MT46V128M4 | 2 | 13 | 12 | 0 | +| MT46V256M4 | 2 | 14 | 12 | 0 | +| MT46V32M8 | 2 | 13 | 10 | 1 | +| MT46V64M8 | 2 | 13 | 11 | 1 | +| MT46V128M8 | 2 | 14 | 11 | 1 | +| MT46V16M16 | 2 | 13 | 9 | 2 | +| MT46V32M16 | 2 | 13 | 10 | 2 | +| MT46V64M16 | 2 | 14 | 10 | 2 | + +In addition, you can modify lines 18\~19 of tb_ddr_sdram_ctrl.v to modify the burst length of reads and writes during simulation. + +　 + +# Related Links + +* MICRON's DDR1 simulation model : https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b +* MT46V64M8 datasheet : https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr1/512mb_ddr.pdf?rev=4e1e995d6d2240e293286770f193d57d + +　 + +　 + +　 + +　 + +　 + +FPGA DDR-SDRAM +=========================== + +DDR1 SDRAM 控制器，具有 AXI4 slave 接口，接收 AXI4 读写操作进行 DDR1 读写。 + 在低端FPGA设计中用 DDR-SDRAM（DDR1）替换 SDR-SDRAM。 # 简介 @@ -32,7 +484,7 @@ FPGA DDR-SDRAM 另外，由于各代 DDR-SDRAM（例如DDR3、DDR2、DDR1）的接口时序大同小异，本库也可以方便那些熟悉 Verilog 的人来学习 DDR-SDRAM 接口。 - +　 # 目录 @@ -51,7 +503,7 @@ FPGA DDR-SDRAM * [仿真](#仿真) * [修改仿真参数](#修改仿真参数) - +　 # 硬件设计指南 @@ -70,6 +522,7 @@ FPGA DDR-SDRAM | ddr_dqs | inout | 取决于芯片型号 | | 2.5V LVTTL | 布线尽量短 | | ddr_dm、ddr_dq | inout | 取决于芯片型号 | 与 ddr_dqs 双沿同步 | 2.5V LVTTL | 布线尽量短，与 ddr_dqs 大致等长（别太离谱即可） | +　 # 硬件设计示例 @@ -83,11 +536,11 @@ FPGA DDR-SDRAM 该板子的设计在立创EDA中开放，见 [oshwhub.com/wangxuan/fpga-ddr-ce-shi-ban](https://oshwhub.com/wangxuan/fpga-ddr-ce-shi-ban)。 - +　 # DDR1控制器模块 -DDR1 控制器代码见 RTL/ddr_sdram_ctrl.sv ，它能自动对 DDR1 进行初始化，并定时进行刷新（Refresh）。该模块有一个简化但完备的 AXI4 从接口，通过它可以完成对 DDR1 的读写。本节详细解释该模块的使用方法。 +DDR1 控制器代码见 RTL/ddr_sdram_ctrl.v ，它能自动对 DDR1 进行初始化，并定时进行刷新（Refresh）。该模块有一个简化但完备的 AXI4 从接口，通过它可以完成对 DDR1 的读写。本节详细解释该模块的使用方法。 ## 模块参数 @@ -330,7 +783,7 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 _______________________ ddr_a XXXXXX__RA_XXXXXXX_CA0_X_CA1_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - +　 # 示例程序 @@ -342,9 +795,9 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 | 文件名称 | 用途 | | :---- | :--- | -| example-selftest/top.sv | 顶层 | -| example-selftest/axi_self_test_master.sv | 是 AXI4 主机，通过 AXI4 先把有规律的数据写入 DDR1，然后读回，比较读回的数据是否符合规律，并对不匹配的情况进行计数。 | -| RTL/ddr_sdram_ctrl.sv | DDR1 控制器 | +| example-selftest/fpga_top.v | 顶层 | +| example-selftest/axi_self_test_master.v | 是 AXI4 主机，通过 AXI4 先把有规律的数据写入 DDR1，然后读回，比较读回的数据是否符合规律，并对不匹配的情况进行计数。 | +| RTL/ddr_sdram_ctrl.v | DDR1 控制器 | 该示例程序的行为是： @@ -354,7 +807,7 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 **SignalTap抓波形**：该工程包含一个 SignalTap 文件 stp1.stp，在程序运行时，可以用它查看 DDR1 接口上的波形。它以 error=1 为触发信号，因此如果读写自测没有出错，它就不会被触发。因为该工程随时都在读取 DDR1，要想看 DDR1 接口上的波形，直接按“停止”按钮即可。 -**修改 AXI4 突发长度**：在 top.sv 的第 82，83 行可以修改 WBURST_LEN 和 RBURST_LEN，从而修改自测时的写/读突发长度，该自测程序只支持 2^n-1 这种突发长度，即 WBURST_LEN 和 RBURST_LEN 必须取形如 0,1,3,7,15,31,…… 的值（注意，这只是我编写的自测程序的限制，DDR1 控制器是支持 0~255 之间的任意突发长度的。 +**修改 AXI4 突发长度**：在 fpga_top.v 的第 82，83 行可以修改 WBURST_LEN 和 RBURST_LEN，从而修改自测时的写/读突发长度，该自测程序只支持 2^n-1 这种突发长度，即 WBURST_LEN 和 RBURST_LEN 必须取形如 0,1,3,7,15,31,…… 的值（注意，这只是我编写的自测程序的限制，DDR1 控制器是支持 0~255 之间的任意突发长度的。 > WBURST_LEN 和 RBURST_LEN 可以设置的不一样。 @@ -366,9 +819,11 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 | 文件名称 | 用途 | | :---- | :--- | -| example-uart-read-write/top.sv | 顶层 | -| example-uart-read-write/uart2axi4.sv | 是 AXI4 主机，能把 UART RX 收到的命令转换成 AXI4 读写操作，并把读操作读出的数据通过 UART TX 发送出去 | -| RTL/ddr_sdram_ctrl.sv | DDR1 控制器 | +| example-uart-read-write/fpga_top.v | 顶层 | +| example-uart-read-write/uart/uart2axi4.v | 是 AXI4 主机，能把 UART RX 收到的命令转换成 AXI4 读写操作，并把读操作读出的数据通过 UART TX 发送出去 (详见 https://github.com/WangXuan95/Verilog-UART) | +| example-uart-read-write/uart/uart_rx.v | 被 uart2axi4.v 调用 | +| example-uart-read-write/uart/uart_tx.v | 被 uart2axi4.v 调用 | +| RTL/ddr_sdram_ctrl.v | DDR1 控制器 | [FPGA+DDR1测试板](#硬件设计示例)上有一个 CH340E 芯片（USB 转 UART），因此插上 USB 线后就可以在电脑上看见 UART 对应的 COM 口（需要先在 [www.wch.cn/product/CH340.html](http://www.wch.cn/product/CH340.html) 下载安装 CH341 的驱动）。 @@ -376,9 +831,9 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 w12345 0123 4567 89ab cdef -然后用以下命令+回车，可以以 0x12345 为起始地址，以 7 为突发长度，读取 8 个数据。 +然后用以下命令+回车，可以以 0x12345 为起始地址，以 8 为突发长度，读取 8 个数据。 - r12345 7 + r12345 8 效果如下图，前4个数据 (0123 4567 89ab cdef) 就是我们已经写入 DDR1 的，后4个数据我们没写过，是 DDR1 初始化后自带的随机数据。 @@ -386,15 +841,15 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 | :--: | | 图：使用 UartSession.exe 测试 DDR1 读写 | -写命令里有多少数据，写突发长度就是多少，例如以下写命令的突发长度是 9，将 10 个数据写入起始地址 0x00000 +写命令里有多少数据，写突发长度就是多少，例如以下写命令的突发长度是 10，将 10 个数据写入起始地址 0x00000 w0 1234 2345 3456 4567 5678 6789 789a 89ab 9abc abcd -读命令则直接指定突发长度，例如以下命令的突发长度为 30 （0x1e），从起始地址 0x00000 将 31 个数据读出 +读命令则直接指定突发长度，例如以下命令的突发长度为 30 （0x1e），从起始地址 0x00000 将 30 个数据读出 r0 1e - +　 # 仿真 @@ -402,11 +857,11 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 | 文件路径 | 用途 | | :---- | :--- | -| tb_ddr_sdram_ctrl.sv | 仿真顶层 | -| axi_self_test_master.sv | 是 AXI4 主机，通过 AXI4 先把有规律的数据写入 DDR1，然后读回，比较读回的数据是否符合规律，并对不匹配的情况进行计数。 | -| micron_ddr_sdram_model.sv | [MICRON 公司提供的 DDR1 仿真模型](https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b) | +| tb_ddr_sdram_ctrl.v | 仿真顶层 | +| axi_self_test_master.v | 是 AXI4 主机，通过 AXI4 先把有规律的数据写入 DDR1，然后读回，比较读回的数据是否符合规律，并对不匹配的情况进行计数。 | +| micron_ddr_sdram_model.v | [MICRON 公司提供的 DDR1 仿真模型](https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b) | -该仿真工程的行为和自测程序一样， axi_self_test_master.sv 作为 AXI4 主机，将有规律的数据写入 DDR1 中，只不过不是全部写入，而是只写入 DDR1 的前 16KB （因为仿真模型的存储空间有限），然后一轮一轮地反复读出数据，比较是否有不匹配的数据，若有，则在 error 信号上产生一个时钟周期的高电平。 +该仿真工程的行为和自测程序一样， axi_self_test_master.v 作为 AXI4 主机，将有规律的数据写入 DDR1 中，只不过不是全部写入，而是只写入 DDR1 的前 16KB （因为仿真模型的存储空间有限），然后一轮一轮地反复读出数据，比较是否有不匹配的数据，若有，则在 error 信号上产生一个时钟周期的高电平。 使用 iverilog 进行仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) @@ -414,7 +869,7 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 ## 修改仿真参数 -以上仿真默认配置的参数是使用 MT46V64M8 ，即 ROW_BITS=13，COL_BITS=11，DQ_BITS=8 。如果想对其它型号的 DDR1 芯片进行仿真，你需要在 tb_ddr_sdram_ctrl.sv 里修改它们。对于 MICRON 公司的 DDR1 系列，这些参数应该这样修改： +以上仿真默认配置的参数是使用 MT46V64M8 ，即 ROW_BITS=13，COL_BITS=11，DQ_BITS=8 。如果想对其它型号的 DDR1 芯片进行仿真，你需要在 tb_ddr_sdram_ctrl.v 里修改它们。对于 MICRON 公司的 DDR1 系列，这些参数应该这样修改： | 芯片名称 | BA_BITS | ROW_BITS | COL_BITS | DQ_LEVEL | | :--: | :--: | :--: | :--: | :--: | @@ -428,448 +883,12 @@ AXI4 总线的地址（awaddr和araddr）统一是字节地址，模块会根据 | MT46V32M16 | 2 | 13 | 10 | 2 | | MT46V64M16 | 2 | 14 | 10 | 2 | -另外，你可以修改 tb_ddr_sdram_ctrl.sv 的第 18 和 19 行来修改仿真时的突发读写的长度。 - +另外，你可以修改 tb_ddr_sdram_ctrl.v 的第 18 和 19 行来修改仿真时的突发读写的长度。 +　 # 参考资料 * MICRON 公司提供的 DDR1 仿真模型: https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b * MT46V64M8 芯片手册: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr1/512mb_ddr.pdf?rev=4e1e995d6d2240e293286770f193d57d - - - - -FPGA DDR-SDRAM -=========================== - -Replacing SDR-SDRAM with DDR-SDRAM (DDR1) in low-end FPGA designs. - -# Introduction - - |------------------------------| |-----------| - | | | | - ----->| driving clock and reset | | | - | | | | - ------------| | DDR-SDRAM interface |--------->| | - | AXI4 | | | | - AXI4 master |-------->| AXI4 slave | | | - | | | | | - ------------| |------------------------------| |-----------| - User Logic DDR1 Controller (ddr_sdram_ctrl.sv) DDR1 chip - -Many low-end FPGA development boards use SDR-SDRAM as off-chip memory, but DDR-SDRAM (DDR1) is larger and less expensive than SDR-SDRAM. And like SDR-SDRAM, DDR1 can also be directly driven by common IO pins of low-end FPGAs. I write a soft core DDR1 controller with a slave AXI4 interface for user. The features of this controller are: - -* **Platform Independent** : Written in pure SystemVerilog and can run on various FPGAs including Altera and Xilinx. -* **Compatible** : Supports DDR1 of various bit widths and capacities (this has been verify by simulation on MICRON's DDR1 models). - -To demonstrate the use of this controller, I provide two demo projects: - -* **Self-test demo** : Through the DDR1 controller, write data into DDR1, then read it out, and compare whether the read data is consistent with the written data. -* **UART DDR1 read/write demo** : Convert UART commands into AXI4 bus actions to read and write DDR1 through the DDR1 controller. - -In addition, since the interface timing of each generation of DDR-SDRAM (such as DDR3, DDR2, DDR1) is similar, this repository can also facilitate those who are familiar with Verilog to learn the DDR-SDRAM interface. - - - -# Table of Contents - -* [Hardware Design Guidelines](#Hardware Design Guidelines) -* [Hard Design Example](#Hard Design Example) -* [DDR1 Control Module Manual](#DDR1 Control Module Manual) - * [Module Parameters](#Module Parameters) - * [Module Interface: clock and reset](#Module Interface: clock and reset) - * [Module Interface: DDR1 interface](#Module Interface: DDR1 interface) - * [Module Interface: AXI4 slave](#Module Interface: AXI4 slave) - * [Bit Width Parameters](#Bit Width Parameters) - * [Timing Parameters](#Timing Parameters) -* [FPGA Demo Projects](#FPGA Demo Projects) - * [Self-test demo](#Self-test demo) - * [UART DDR1 read/write demo](#UART DDR1 read/write demo) -* [RTL Simulation](#RTL Simulation) - * [Modify Simulation Attributes](#Modify Simulation Attributes) - - - -# Hardware Design Guidelines - -For FPGA selection, only an FPGA with a sufficient number of common IOs can drive DDR1. The IO level standard of DDR1 is often SSTL-2, which is compatible with 2.5V LVTTL or 2.5V LVCMOS, so the power supply of the corresponding FPGA IO bank should be 2.5V, and should be configured as 2.5V LVTTL or 2.5V LVCMOS in the FPGA development software . - -The following table shows the pin defination of the DDR1 chip and the points that should be paid attention to when connecting it to the FPGA. - -| pin name | direction | width | introduction | level | note | -| :----------------------------: | :---------: | :-----------------: | :-------------------------------- | :--------- | :------------------------------- | -| ddr_ck_p | FPGA output | 1 | DDR1 clock p , ≥75MHz | 2.5V LVTTL | differential route with ddr_ck_n | -| ddr_ck_n | FPGA output | 1 | DDR1 clock n , ≥75MHz | 2.5V LVTTL | differential route with ddr_ck_p | -| ddr_cke, ddr_cs_n | FPGA output | 1 | low speed | 2.5V LVTTL | | -| ddr_ras_n, ddr_cas_n, ddr_we_n | FPGA output | 1 | sync with ddr_ck_p's falling edge | 2.5V LVTTL | same length as ddr_ck_p | -| ddr_ba | FPGA output | 2 | sync with ddr_ck_p's falling edge | 2.5V LVTTL | same length as ddr_ck_p | -| ddr_a | FPGA output | depend on DDR1 part | sync with ddr_ck_p's falling edge | 2.5V LVTTL | same length as ddr_ck_p | -| ddr_dqs | inout | depend on DDR1 part | | 2.5V LVTTL | | -| ddr_dm、ddr_dq | inout | depend on DDR1 part | sync with ddr_dqs's double edge | 2.5V LVTTL | same length as ddr_dqs | - - -# Hard Design Example - -For demonstration, I used the cheapest FPGA of Altera Cyclone IV (model: EP4CE6E22C8N) and MICRON's 64MB DDR1 (model MT46V64M8TG-6T) to design a small board. All the demo project of this repository can run on this board directly. If you want to use DDR1 in your own PCB design, just refer to this board's design. - -| ![board-image](./figures/board.jpg) | -| :----------------------------------: | -| **Figure** : FPGA + DDR1 demo board. | - -See board schematic [PCB/sch.pdf](./PCB/sch.pdf) and manufacturing file [PCB/gerber.zip](./PCB/gerber.zip) . It is a double-layer board, and it is not necessary to pay attention to impedance matching like DDR2 and DDR3, because the operating frequency of the circuit is 75MHz on both sides, which is not particularly high. Just pay attention to keeping the distance between FPGA and DDR as close as possible, and the wiring as short as possible. For example, I put the DDR1 chip on the opposite side of the FPGA chip to keep the wiring short. - -The design of this board is open in LCEDA, see [oshwhub.com/wangxuan/fpga-ddr-ce-shi-ban](https://oshwhub.com/wangxuan/fpga-ddr-ce-shi-ban) . - - - -# DDR1 Control Module Manual - -See [RTL/ddr_sdram_ctrl.sv](./RTL/ddr_sdram_ctrl.sv) for the DDR1 controller code, which can automatically initialize DDR1 and refresh it regularly. The module has a AXI4 slave interface through which reads and writes to DDR1 can be accomplished. This section introduce in detail how to use this module. - -## Module Parameters - -Verilog parameters of this module are defined as follows: - -```Verilog -module ddr_sdram_ctrl #( - parameter READ_BUFFER = 1, - parameter BA_BITS = 2, - parameter ROW_BITS = 13, - parameter COL_BITS = 11, - parameter DQ_LEVEL = 1, - parameter [9:0] tREFC = 10'd256, - parameter [7:0] tW2I = 8'd7, - parameter [7:0] tR2I = 8'd7 -) -``` - -These parameters are described in the table below: - -| Parameter | Type | value range | default value | introduction | -| :---------: | :----: | :---------: | :-----------: | :----------------------------------------------------------- | -| READ_BUFFER | | 0 or 1 | 1 | If it is set to 0, there will be no read data buffer in the DDR1 controller, and the read data will not wait for the AXI4 host to accept it, that is, the rvalid signal will not wait for the rready signal, and will be directly poured out at the highest rate. At this time, AXI4 is not Complete, but can reduce the latency of readout. If it is set to 1, there will be a large enough read data buffer in the DDR1 controller, and the rvalid signal will shake hands with the rready signal to confirm that the AXI4 host is ready before reading the data. | -| BA_BITS | Width | 1~4 | 2 | The width of DDR BANK ADDRESS (ddr_ba) is specified. Regular DDR1 BANK ADDRESS is 2bit, so this parameter is usually fixed to the default value and does not need to be changed. | -| ROW_BITS | Width | 1~15 | 13 | It specifies the width of the DDR ROW ADDRESS, and also determines the width of the address line pins (ddr_a) of the DDR1 chip. This parameter depends on the selection of the DDR1 chip. For example, MT46V64M8 has 8192 COLs per bank, considering 2^11=8192, this parameter should be 13. Similarly, for MT46V128M8, this parameter should be 14 | -| COL_BITS | Width | 1~14 | 11 | Specifies the width of the DDR COL ADDRESS. This parameter depends on the selection of the DDR1 chip. For example, MT46V64M8 has 2048 COLs per ROW. Considering 2^11=2048, this parameter should be 11. Similarly, for MT46V32M16, this parameter should be 10. | -| DQ_LEVEL | Width | 0~7 | 1 | The data bit width of the DDR1 chip is specified. For a chip with a bit width of x4 (such as MT46V64M4), this parameter should be 0; for a chip with a bit width of x8 (such as MT46V64M8), this parameter should be 1; for a chip with a bit width of x16 ( For example, MT46V64M16), this parameter should be 2; for the case of bit width x32 (such as two pieces of MT46V64M16 extended bit width), this parameter should be 3; and so on. | -| tREFC | Timing | 1\~1023 | 256 | The controller will refresh DDR1 periodically, and this parameter specifies the refresh interval of DDR1. See [Timing Parameters](#Timing Parameters) for details. | -| tW2I | Timing | 1\~255 | 7 | This parameter specifies the interval from the last write command of a write action to the activation command (ACT) of the next action. See [Timing Parameters](#Timing Parameters) for details. | -| tR2I | Timing | 1\~255 | 7 | This parameter specifies the interval from the last read command of a read action to the activation command (ACT) of the next action. See [Timing Parameters](#Timing Parameters) for details. | - -## Module Interface: clock and reset - -This module requires a drive clock and a drive reset, as follows: - -```Verilog - input wire rstn_async, - input wire drv_clk, -``` - -`rstn_async` is a low-level reset signal and should be set high during normal operation. `drv_clk` is the driving clock, and its frequency is 4 times the user clock. - -Before the module starts working, the `rstn_async` signal should be set low to reset the module, and then set rstn_async high to release the reset. - -### Clock freqency selection - -In this module, the driving clock `drv_clk` is divided by 4 to generate the DDR1 clock (`ddr_ck_p/ddr_ck_n`) and the AXI4 bus user clock (`clk`). This section describes how to determine the frequency of the drive clock `drv_clk`. - -First, the clock frequency is limited by the DDR1 chip. Considering that all DDR1 interface frequencies are at least 75MHz, the lower limit of `drv_clk` is 75\*4=300MHz. - -The upper limit of `drv_clk` also depends on the chip model of DDR1. For example, for MT46V64M8P-5B, check the chip manual, the maximum clock frequency of DDR1 with -5B suffix is 133MHz when CAS Latency (CL)=2, then the upper limit of `drv_clk` is 133 \*4=532MHz. - -> Note: This controller has a fixed CAS Latency (CL) = 2. - -In addition, the upper limit of the clock frequency is also limited by the speed of the FPGA. Too high a clock frequency can easily lead to timing failure. This design fully considers the timing safety design, most registers work in the clk clock domain with a lower frequency; some registers work in a clock that is twice the frequency of the clk clock, and the combinational logic of the input port is very short; Under the `drv_clk` of the frequency, but the input port comes directly from the register output of the upper stage (no combinational logic). Therefore, even on the EP4CE6E22C8N with a very low speed class, the correct operation of the module is guaranteed at a drive clock of 300MHz. - -## Module Interface: DDR1 interface - -Following is the DDR1 interface of this module. These signals should be pinout directly from the FPGA and connected to the DDR1 chip. - -```Verilog - output wire ddr_ck_p, ddr_ck_n, - output wire ddr_cke, - output reg ddr_cs_n, - output reg ddr_ras_n, - output reg ddr_cas_n, - output reg ddr_we_n, - output reg [ BA_BITS-1:0] ddr_ba, - output reg [ ROW_BITS-1:0] ddr_a, - output wire [((1< Note: When the module parameter `READ_BUFFER=0`, the module will save a BRAM resource and also reduce the delay between address channel handshake and data transfer. But the DDR1 controller ignores the `rready=0` condition and does not wait for the AXI4 host to be ready to accept data. This will destroy the completeness of the AXI4 protocol, but it may be useful in some simple situations. - - -## Bit Width Parameters - -This section describes how to determine the 4 parameters: `BA_BITS` , `ROW_BITS` , `COL_BITS` and `DQ_LEVEL`. - -Take [MICRON's DDR-SDRAM](https://www.micron.com/products/dram/ddr-sdram) series chips as an example, different chips have different ROW ADDRESS BITS, COL ADDRESS BITS and DATA BITS, which means that their bit width parameters are also different, as shown in the following table (note: these parameters can be found in the chip datasheet). - -| chip part | ddr_dq width | ddr_dm ddr_dqs width | DQ_LEVEL | BA_BITS | ROW_BITS | COL_BITS | byte per row | total capacity | awaddr/araddr width | -| :--------: | :----------: | :------------------: | :------: | :-----: | :------: | :------: | :----------: | :------------------------- | :-----------------: | -| MT46V64M4 | 4 | 1 | 0 | 2 | 13 | 11 | 1024 | 4\*2^(2+13+11)=256Mb=32MB | 25 | -| MT46V128M4 | 4 | 1 | 0 | 2 | 13 | 12 | 2048 | 4\*2^(2+13+12)=512Mb=64MB | 26 | -| MT46V256M4 | 4 | 1 | 0 | 2 | 14 | 12 | 4096 | 4\*2^(2+14+12)=1Gb=128MB | 27 | -| MT46V32M8 | 8 | 1 | 1 | 2 | 13 | 10 | 1024 | 8\*2^(2+13+10)=256Mb=32MB | 25 | -| MT46V64M8 | 8 | 1 | 1 | 2 | 13 | 11 | 2048 | 8\*2^(2+13+11)=512Mb=64MB | 26 | -| MT46V128M8 | 8 | 1 | 1 | 2 | 14 | 11 | 4096 | 8\*2^(2+14+11)=1Gb=128MB | 27 | -| MT46V16M16 | 16 | 2 | 2 | 2 | 13 | 9 | 1024 | 16\*2^(2+13+9)=256Mb=32MB | 25 | -| MT46V32M16 | 16 | 2 | 2 | 2 | 13 | 10 | 2048 | 16\*2^(2+13+10)=512Mb=64MB | 26 | -| MT46V64M16 | 16 | 2 | 2 | 2 | 14 | 10 | 4096 | 16\*2^(2+14+10)=1Gb=128MB | 27 | - -## Timing Parameters - -This section describes how to determine the 3 timing parameters `tREFC`, `tW2I` and `tR2I`. - -We know that DDR1 requires periodic refresh action, and `tREFC` specifies the refresh clock cycle interval (subject to clk). For example, if the user clock is 75MHz, according to the chip manual of MT46V64M8, it needs to be refreshed once at most 7.8125us. Considering that 75MHz * 7.8125us = 585.9, this parameter can be set to a value less than 585, such as `10'd512`. - -`tW2I` specifies the minimum number of clock cycles (in clk) from the last write command of a write operation to the active command (ACT) of the next operation. The following figure shows a write operation on a DDR1 interface. The first rising edge of ddr_cas_n represents the end of the last write command of a write operation, and the second falling edge of ddr_ras_n represents the next operation (may be read, write, Refresh), there are 5 clock cycles between them, `tW2I` is used to specify the lower limit of the number of cycles. The default value of `tW2I` is `8'd7`, which is a conservative value compatible with most DDR1s. For different DDR1 chips, there are different shrinkage margins (see DDR1 chip datasheet for details). - - __ __ __ __ __ __ __ __ __ __ __ __ - ddr_ck_p __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__ - _____ _______________________________________________ ________ - ddr_ras_n \_____/ \_____/ - _________________ ____________________________________________ - ddr_cas_n \___________/ - _________________ ____________________________________________ - ddr_we_n \___________/ - _____ - ddr_a[10] XXXXXXXXXXXXXXXXXX_____/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - _______________________ - ddr_ba XXXXXX__________BA___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - _______________________ - ddr_a XXXXXX__RA_XXXXXXX_CA0_X_CA1_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - -`tR2I` specifies the minimum number of clock cycles (in `clk`) from the last read command of a read operation to the active command (ACT) of the next operation. The figure below shows a read operation on a DDR1 interface. The first rising edge of ddr_cas_n represents the end of the last read command of a read operation, and the second falling edge of ddr_ras_n represents the next operation (may be read, write, Refresh), there are 5 clock cycles between them, `tR2I` is used to specify the lower limit of the number of cycles. The default value of `tR2I` is `8'd7`, which is a conservative value compatible with most DDR1. For different DDR1 chips, there are different shrinkage margins (see DDR1 chip datasheet for details). - - __ __ __ __ __ __ __ __ __ __ __ __ - ddr_ck_p __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__ - _____ _______________________________________________ ________ - ddr_ras_n \_____/ \_____/ - _________________ ____________________________________________ - ddr_cas_n \___________/ - __________________________________________________________________________ - ddr_we_n - _____ - ddr_a[10] XXXXXXXXXXXXXXXXXX_____/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - _______________________ - ddr_ba XXXXXX__________BA___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - _______________________ - ddr_a XXXXXX__RA_XXXXXXX_CA0_X_CA1_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - - - -# FPGA Demo Projects - -## Self-test demo - -I provide a DDR1 read and write self-test project based on the [FPGA+DDR1 board](#Hardware Design Example) I designed. The project directory is [example-selftest](./example-selftest) , please open it with Quartus. - -This project contains following files: - -| File Name | Introduction | -| :--------------------------------------- | :----------------------------------------------------------- | -| example-selftest/top.sv | top-level module | -| example-selftest/axi_self_test_master.sv | AXI4 master. First, write the data into DDR1 through AXI4, and then read back and verify. | -| RTL/ddr_sdram_ctrl.sv | DDR1 controller | - -The behavior of the demo project is: - -**Write**: After the project starts running, it will first write the entire DDR1 through AXI4, and directly write the address word to the corresponding address. For example, if the data width of AXI4 is 16bit, then write 0x0001 at address 0x000002. Write 0x3456 at address 0x123456. - -**Read & Error Check**: After writing the entire DDR1, the project will repeatedly read the entire DDR1 round by round. error) to generate a high-level pulse, and the error count signal (error_cnt) +1. If the DDR1 configuration is correct, there should be no error signal. You can measure the pin corresponding to error_cnt, if it is 0 (all low), it means there is no error. - -**SignalTap waveform capture**: This project contains a SignalTap file stp1.stp, which can be used to view the waveform on the DDR1 interface when the program is running. It triggers with error=1, so if there is no error in the read and write self-test, it will not be triggered. Because the project is reading DDR1 at any time, if you want to see the waveform on the DDR1 interface, just press the "Stop" button. - -**Modify AXI4 burst length**: You can modify WBURST_LEN and RBURST_LEN in lines 82 and 83 of top.sv to modify the write/read burst length during self-test. The self-test program only supports 2^n-1 This burst length, ie WBURST_LEN and RBURST_LEN must take values like 0, 1, 3, 7, 15, 31, ... (note that this is only a limitation of the self-test program I wrote, DDR1 controller supports 0 Any burst length between ~255. - -> WBURST_LEN and RBURST_LEN can be set differently. - -## UART DDR1 read/write demo - -I provide a UART read and write project based on the [FPGA+DDR1 board](#Hardware Design Example) I designed. In this project, you can read and write DDR1 with different burst lengths through UART commands. The project directory is [example-uart-read-write](./example-uart-read-write) , please open it with Quartus. - -The project contains the following files: - -| File Name | Introduction | -| :----------------------------------- | :----------------------------------------------------------- | -| example-uart-read-write/top.sv | top-level module | -| example-uart-read-write/uart2axi4.sv | an AXI4 master, which can convert the commands received by UART RX into AXI4 read and write operations, and send the data read out by read operations through UART TX | -| RTL/ddr_sdram_ctrl.sv | DDR1 controller | - -There is a CH340E chip (USB to UART) on the [FPGA+DDR1 board](#Hardware Design Example), so after plugging in the USB cable, you can see the serial port corresponding to the UART on the computer (you need to download and install the driver of CH341 on [www.wch. cn/product/CH340.html](http://www.wch.cn/product/CH340.html) first). - -After the project is programed to FPGA, double-click to open a serial port tool **UartSession.exe** (it is in the [example-uart-read-write](./example-uart-read-write) directory), open the COM port corresponding to the board according to the prompt, and then type the following command + Enter, you can Write the 4 data 0x0123, 0x4567, 0x89ab, and 0xcdef into the starting address 0x12345. (A write operation with a burst length of 4 occurs on the AXI4 bus). - - w12345 0123 4567 89ab cdef - -Then use the following command + enter to read 8 data from the starting address 0x12345 (7 means the burst length is 8). - - r12345 7 - -The effect is as shown in the figure below. The first 4 data (0123 4567 89ab cdef) are what we have written into DDR1, and the last 4 data are random data that comes with DDR1 after initialization. - -| ![](./figures/UartSession.png) | -| :------------------------------------------------------: | -| Figure : Use UartSession.exe to perform DDR1 read/write. | - -The length of the write burst is how much data there is in the write command. For example, the burst length of the following write command is 9, and 10 pieces of data are written to the starting address 0x00000 - - w0 1234 2345 3456 4567 5678 6789 789a 89ab 9abc abcd - -The read command needs to specify the burst length. For example, the burst length of the following command is 30 (0x1e), and 31 data are read from the starting address 0x00000 - - r0 1e - - - -# RTL Simulation - -The files required for the simulation are in the [SIM](./SIM) folder, where: - -| File Name | Introduction | -| :------------------------ | :----------------------------------------------------------- | -| tb_ddr_sdram_ctrl.sv | Testbench code, simulation top-level. | -| axi_self_test_master.sv | AXI4 master. First, write the data into DDR1 through AXI4, and then read back and verify. | -| micron_ddr_sdram_model.sv | [MICRON's DDR1 simulation model](https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b) | - -The behavior of the simulation project is the same as that of the self-test program, axi_self_test_master.sv, as the AXI4 host, writes regular data into DDR1, but not all of them, only the first 16KB of DDR1 (because the memory spave of the simulation model is limited), and then repeatedly read data round by round to compare whether there is unmatched data, if there is, generate a high level of one clock cycle on the `error` signal. - -Before using iverilog for simulation, you need to install iverilog , see: [iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) - -Then double-click tb_ddr_sdram_ctrl_run_iverilog.bat to run the simulation, and then you can open the generated dump.vcd file to view the waveform. - -## Modify Simulation Attributes - -The default configuration parameters of the above simulation fit MT46V64M8, namely `ROW_BITS=13`, `COL_BITS=11`, and `DQ_BITS=8`. If you want to simulate other DDR1 chips, you need to modify them in tb_ddr_sdram_ctrl.sv. For MICRON's DDR1 series, these parameters should be modified as follows: - -| DDR1 part | BA_BITS | ROW_BITS | COL_BITS | DQ_LEVEL | -| :--------: | :-----: | :------: | :------: | :------: | -| MT46V64M4 | 2 | 13 | 11 | 0 | -| MT46V128M4 | 2 | 13 | 12 | 0 | -| MT46V256M4 | 2 | 14 | 12 | 0 | -| MT46V32M8 | 2 | 13 | 10 | 1 | -| MT46V64M8 | 2 | 13 | 11 | 1 | -| MT46V128M8 | 2 | 14 | 11 | 1 | -| MT46V16M16 | 2 | 13 | 9 | 2 | -| MT46V32M16 | 2 | 13 | 10 | 2 | -| MT46V64M16 | 2 | 14 | 10 | 2 | - -In addition, you can modify lines 18\~19 of tb_ddr_sdram_ctrl.sv to modify the burst length of reads and writes during simulation. - - - -# Related Links - -* MICRON's DDR1 simulation model : https://www.micron.com/products/dram/ddr-sdram/part-catalog/mt46v64m8p-5b -* MT46V64M8 datasheet : https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr1/512mb_ddr.pdf?rev=4e1e995d6d2240e293286770f193d57d diff --git a/RTL/ddr_sdram_ctrl.sv b/RTL/ddr_sdram_ctrl.v similarity index 81% rename from RTL/ddr_sdram_ctrl.sv rename to RTL/ddr_sdram_ctrl.v index 1d0e82d..113c3c3 100644 --- a/RTL/ddr_sdram_ctrl.sv +++ b/RTL/ddr_sdram_ctrl.v @@ -2,8 +2,8 @@ //-------------------------------------------------------------------------------------------------------- // Module : ddr_sdram_ctrl // Type : synthesizable, IP's top -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// Function: DDR-SDRAM (DDR1) controller +// Standard: Verilog 2001 (IEEE1364-2001) +// Function: DDR1 SDRAM controller // with AXI4 interface //-------------------------------------------------------------------------------------------------------- @@ -59,18 +59,32 @@ module ddr_sdram_ctrl #( inout [ (4< - + 'error' == high @@ -293,7 +293,7 @@ - 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//-------------------------------------------------------------------------------------------------------- // Module : axi_self_test_master // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // Function: write increase data to AXI4 slave, // then read data and check whether they are increasing //-------------------------------------------------------------------------------------------------------- @@ -39,13 +39,22 @@ module axi_self_test_master #( output reg [ 15:0] error_cnt ); -initial {awaddr, araddr} = '0; -initial {error, error_cnt} = '0; + +initial {awaddr, araddr} = 0; +initial {error, error_cnt} = 0; wire aw_end; -reg awaddr_carry = '0; -reg [7:0] w_cnt = '0; -enum logic [2:0] {INIT, AW, W, B, AR, R} stat = INIT; +reg awaddr_carry = 1'b0; +reg [7:0] w_cnt = 8'd0; + +localparam [2:0] INIT = 3'd0, + AW = 3'd1, + W = 3'd2, + B = 3'd3, + AR = 3'd4, + R = 3'd5; + +reg [2:0] stat = INIT; generate if(A_WIDTH_TEST=8'h30 && rx_byte<=8'h39) || (rx_byte>=8'h41 && rx_byte<=8'h46) || (rx_byte>=8'h61 && rx_byte<=8'h66))); // 0~9, A~F, a~f +wire [ 3:0] rx_hex = (rx_byte>=8'h30 && rx_byte<=8'h39) ? rx_byte[3:0] : (rx_byte[3:0] + 4'd9); + + + +reg rwtype = 1'b0; +reg [A_WIDTH-1:0] addr = 0; +reg [ 8:0] len = 9'h0; +reg wwen = 1'b0; +reg [8*BYTE_WIDTH-1:0] wwdata = 0; +reg [ 7:0] wraddr = 8'h0; + + +localparam [ 3:0] S_IDLE = 4'd0, + S_PARSE_ADDR = 4'd1, + S_PARSE_LEN = 4'd2, + S_PARSE_WDATA = 4'd3, + S_AXI_RADDR = 4'd4, + S_AXI_WADDR = 4'd5, + S_AXI_RDATA = 4'd6, + S_AXI_WDATA = 4'd7, + S_AXI_B = 4'd8, + S_W_DONE = 4'd9, + S_INVALID = 4'd10, + S_FAILED = 4'd11; + +reg [ 3:0] state = S_IDLE; + + +always @ (posedge clk or negedge rstn) + if (~rstn) begin + rwtype <= 1'b0; + addr <= 0; + len <= 9'h0; + wwen <= 1'b0; + wwdata <= 0; + wraddr <= 8'h0; + state <= S_IDLE; + end else begin + case (state) + + S_IDLE : begin + rwtype <= rx_char_w; + addr <= 0; + len <= 9'h0; + wwen <= 1'b0; + wwdata <= 0; + wraddr <= 8'h0; + if (rx_char_w | rx_char_r) + state <= S_PARSE_ADDR; + else if (rx_space | rx_newline) + state <= S_IDLE; + else if (rx_valid) + state <= S_INVALID; + end + + S_PARSE_ADDR : + if (rx_is_hex) begin + addr <= (addr << 4); + addr[3:0] <= rx_hex; + end else if (rx_space) + state <= rwtype ? S_PARSE_WDATA : S_PARSE_LEN; + else if (rx_newline) + state <= S_FAILED; + else if (rx_valid) + state <= S_INVALID; + + S_PARSE_LEN : + if (rx_is_hex) begin + len <= (len << 4); + len[3:0] <= rx_hex; + end else if (rx_newline) begin + len <= (len >= 9'h100) ? 9'hFF : (len == 9'h0) ? 9'h0 : (len - 9'h1); + state <= S_AXI_RADDR; + end else if (rx_space) begin + state <= S_PARSE_LEN; + end else if (rx_valid) begin + state <= S_INVALID; + end + + S_PARSE_WDATA : + if (rx_is_hex) begin + wwen <= 1'b1; + wwdata <= (wwdata << 4); + wwdata[3:0] <= rx_hex; + end else if (rx_space) begin + wwen <= 1'b0; + if (wwen) begin + wwdata <= 0; + len <= len + 9'd1; + end + end else if (rx_newline) begin + if (wwen) begin + state <= ( len < 9'h100) ? S_AXI_WADDR : S_FAILED; + end else begin + state <= (len >= 9'd0 && len <= 9'd100) ? S_AXI_WADDR : S_FAILED; + len <= len - 9'd1; + end + end else if (rx_valid) begin + state <= S_INVALID; + end + + S_AXI_RADDR : + if (arready) + state <= S_AXI_RDATA; + + S_AXI_WADDR : + if (awready) + state <= S_AXI_WDATA; + + S_AXI_RDATA : + if (rvalid) begin + len <= len - 9'd1; + if (rlast || (len==9'd0)) + state <= S_IDLE; + end + + S_AXI_WDATA : + if (wready) begin + wraddr <= wraddr + 8'd1; + if (wraddr >= len[7:0]) + state <= S_AXI_B; + end + + S_AXI_B : + if (bvalid) + state <= S_W_DONE; + + S_W_DONE : + state <= S_IDLE; + + S_INVALID : + if (rx_newline) + state <= S_FAILED; + + default : // S_FAILED : + state <= S_IDLE; + + endcase + end + + +reg [8*BYTE_WIDTH-1:0] wbuf [0:255]; + +always @ (posedge clk) + if ( (state == S_PARSE_WDATA) && (rx_space || rx_newline) && wwen ) + wbuf[len[7:0]] <= wwdata; + +wire [ 7:0] wraddr_next = (wvalid & wready) ? (wraddr + 8'd1) : wraddr; +reg [8*BYTE_WIDTH-1:0] wrdata; + +always @ (posedge clk) + wrdata <= wbuf[wraddr_next]; + + + +assign arvalid = (state == S_AXI_RADDR); +assign araddr = addr; +assign arlen = len[7:0]; + +assign awvalid = (state == S_AXI_WADDR); +assign awaddr = addr; +assign awlen = len[7:0]; + +assign rready = (state == S_AXI_RDATA); + +assign wvalid = (state == S_AXI_WDATA); +assign wlast = (wraddr >= len[7:0]); +assign wdata = wrdata; + +assign bready = 1'b1; // (state == S_AXI_B) + + + + + +function [7:0] toHex; + input [3:0] val; +begin + toHex = (val <= 4'd9) ? {4'h3, val} : {4'd6, 1'b0, val[2:0]-3'h1}; +end +endfunction + + +wire tx_w_done = (state == S_W_DONE); +wire tx_failed = (state == S_FAILED); +wire tx_number = (rvalid & rready); + +wire [8*2*BYTE_WIDTH-1:0] tx_data_failed = 64'h20_64_69_6C_61_76_6E_69; // "invalid" +wire [8*2*BYTE_WIDTH-1:0] tx_data_w_done = 64'h20_20_20_20_79_61_6B_6F; // "okay" +wire [8*2*BYTE_WIDTH-1:0] tx_data_number; + +wire tx_valid = tx_failed | tx_w_done | tx_number; +wire [8*2*BYTE_WIDTH-1:0] tx_data = tx_failed ? tx_data_failed : tx_w_done ? tx_data_w_done : tx_data_number; +wire tx_last = tx_failed ? 1'b1 : tx_w_done ? 1'b1 : (rlast || (len==9'd0)); + + +generate genvar i; + for (i=0; i<2*BYTE_WIDTH; i=i+1) begin : gen_tx_tdata + assign tx_data_number[8*i +: 8] = toHex(rdata[4*(2*BYTE_WIDTH-1-i) +: 4]); + end +endgenerate + + + +uart_tx #( + .CLK_FREQ ( CLK_FREQ ), + .BAUD_RATE ( BAUD_RATE ), + .PARITY ( PARITY ), + .STOP_BITS ( 4 ), + .BYTE_WIDTH ( 2 * BYTE_WIDTH ), + .FIFO_EA ( 9 ), + .EXTRA_BYTE_AFTER_TRANSFER ( " " ), + .EXTRA_BYTE_AFTER_PACKET ( "\n" ) +) u_uart_tx ( + .rstn ( rstn ), + .clk ( clk ), + .i_tready ( ), + .i_tvalid ( tx_valid ), + .i_tdata ( tx_data ), + .i_tkeep ( {(2*BYTE_WIDTH){1'b1}} ), + .i_tlast ( tx_last ), + .o_uart_tx ( o_uart_tx ) +); + + +endmodule diff --git a/example-uart-read-write/uart/uart_rx.v b/example-uart-read-write/uart/uart_rx.v new file mode 100644 index 0000000..66ba82e --- /dev/null +++ b/example-uart-read-write/uart/uart_rx.v @@ -0,0 +1,335 @@ + +//-------------------------------------------------------------------------------------------------------- +// Module : uart_rx +// Type : synthesizable, IP's top +// Standard: Verilog 2001 (IEEE1364-2001) +// Function: input UART signal, +// output AXI-stream (configurable byte data width) +//-------------------------------------------------------------------------------------------------------- + +module uart_rx #( + // clock frequency + parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz + // UART format + parameter BAUD_RATE = 115200, // Unit : Hz + parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" + // RX fifo depth + parameter FIFO_EA = 0 // 0:no fifo 1,2:depth=4 3:depth=8 4:depth=16 ... 10:depth=1024 11:depth=2048 ... +) ( + input wire rstn, + input wire clk, + // UART RX input signal + input wire i_uart_rx, + // output AXI-stream master. Associated clock = clk. + input wire o_tready, + output reg o_tvalid, + output reg [ 7:0] o_tdata, + // report whether there's a overflow + output reg o_overflow +); + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// Generate fractional precise upper limit for counter +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +localparam BAUD_CYCLES = ( (CLK_FREQ*10*2 + BAUD_RATE) / (BAUD_RATE*2) ) / 10 ; +localparam BAUD_CYCLES_FRAC = ( (CLK_FREQ*10*2 + BAUD_RATE) / (BAUD_RATE*2) ) % 10 ; + +localparam HALF_BAUD_CYCLES = BAUD_CYCLES / 2; +localparam THREE_QUARTER_BAUD_CYCLES = (BAUD_CYCLES*3) / 4; + +localparam [9:0] ADDITION_CYCLES = (BAUD_CYCLES_FRAC == 0) ? 10'b0000000000 : + (BAUD_CYCLES_FRAC == 1) ? 10'b0000010000 : + (BAUD_CYCLES_FRAC == 2) ? 10'b0010000100 : + (BAUD_CYCLES_FRAC == 3) ? 10'b0010010010 : + (BAUD_CYCLES_FRAC == 4) ? 10'b0101001010 : + (BAUD_CYCLES_FRAC == 5) ? 10'b0101010101 : + (BAUD_CYCLES_FRAC == 6) ? 10'b1010110101 : + (BAUD_CYCLES_FRAC == 7) ? 10'b1101101101 : + (BAUD_CYCLES_FRAC == 8) ? 10'b1101111011 : + /*BAUD_CYCLES_FRAC == 9)*/ 10'b1111101111 ; + +wire [31:0] cycles [9:0]; + +assign cycles[0] = BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0); +assign cycles[1] = BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0); +assign cycles[2] = BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0); +assign cycles[3] = BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0); +assign cycles[4] = BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0); +assign cycles[5] = BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0); +assign cycles[6] = BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0); +assign cycles[7] = BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0); +assign cycles[8] = BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0); +assign cycles[9] = BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0); + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// Input beat +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +reg rx_d1 = 1'b0; + +always @ (posedge clk or negedge rstn) + if (~rstn) + rx_d1 <= 1'b0; + else + rx_d1 <= i_uart_rx; + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// count continuous '1' +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +reg [31:0] count1 = 0; + +always @ (posedge clk or negedge rstn) + if (~rstn) begin + count1 <= 0; + end else begin + if (rx_d1) + count1 <= (count1 < 'hFFFFFFFF) ? (count1 + 1) : count1; + else + count1 <= 0; + end + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// main FSM +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +localparam [ 3:0] TOTAL_BITS_MINUS1 = (PARITY == "ODD" || PARITY == "EVEN") ? 4'd9 : 4'd8; + +localparam [ 1:0] S_IDLE = 2'd0 , + S_RX = 2'd1 , + S_STOP_BIT = 2'd2 ; + +reg [ 1:0] state = S_IDLE; +reg [ 8:0] rxbits = 9'b0; +reg [ 3:0] rxcnt = 4'd0; +reg [31:0] cycle = 1; +reg [32:0] countp = 33'h1_0000_0000; // countp>=0x100000000 means '1' is majority , countp<0x100000000 means '0' is majority +wire rxbit = countp[32]; // countp>=0x100000000 corresponds to countp[32]==1, countp<0x100000000 corresponds to countp[32]==0 + +wire [ 7:0] rbyte = (PARITY == "ODD" ) ? rxbits[7:0] : + (PARITY == "EVEN") ? rxbits[7:0] : + /*(PARITY == "NONE")*/ rxbits[8:1] ; + +wire parity_correct = (PARITY == "ODD" ) ? ((~(^(rbyte))) == rxbits[8]) : + (PARITY == "EVEN") ? ( (^(rbyte)) == rxbits[8]) : + /*(PARITY == "NONE")*/ 1'b1 ; + + +always @ (posedge clk or negedge rstn) + if (~rstn) begin + state <= S_IDLE; + rxbits <= 9'b0; + rxcnt <= 4'd0; + cycle <= 1; + countp <= 33'h1_0000_0000; + end else begin + case (state) + S_IDLE : begin + if ((count1 >= THREE_QUARTER_BAUD_CYCLES) && (rx_d1 == 1'b0)) // receive a '0' which is followed by continuous '1' for half baud cycles + state <= S_RX; + rxcnt <= 4'd0; + cycle <= 2; // we've already receive a '0', so here cycle = 2 + countp <= (33'h1_0000_0000 - 33'd1); // we've already receive a '0', so here countp = initial_value - 1 + end + + S_RX : + if ( cycle < cycles[rxcnt] ) begin // cycle loop from 1 to cycles[rxcnt] + cycle <= cycle + 1; + countp <= rx_d1 ? (countp + 33'd1) : (countp - 33'd1); + end else begin + cycle <= 1; // reset counter + countp <= 33'h1_0000_0000; // reset counter + + if ( rxcnt < TOTAL_BITS_MINUS1 ) begin // rxcnt loop from 0 to TOTAL_BITS_MINUS1 + rxcnt <= rxcnt + 4'd1; + if ((rxcnt == 4'd0) && (rxbit == 1'b1)) // except start bit, but get '1' + state <= S_IDLE; // RX failed, back to IDLE + end else begin + rxcnt <= 4'd0; + state <= S_STOP_BIT; + end + + rxbits <= {rxbit, rxbits[8:1]}; // put current rxbit to MSB of rxbits, and right shift other bits + end + + default : // S_STOP_BIT + if ( cycle < THREE_QUARTER_BAUD_CYCLES) begin // cycle loop from 1 to THREE_QUARTER_BAUD_CYCLES + cycle <= cycle + 1; + end else begin + cycle <= 1; // reset counter + state <= S_IDLE; // back to IDLE + end + endcase + end + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// RX result byte +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +reg f_tvalid = 1'b0; +reg [7:0] f_tdata = 8'h0; + +always @ (posedge clk or negedge rstn) + if (~rstn) begin + f_tvalid <= 1'b0; + f_tdata <= 8'h0; + end else begin + f_tvalid <= 1'b0; + f_tdata <= 8'h0; + if (state == S_STOP_BIT) begin + if ( cycle < THREE_QUARTER_BAUD_CYCLES) begin + end else begin + if ((count1 >= HALF_BAUD_CYCLES) && parity_correct) begin // stop bit have enough '1', and parity correct + f_tvalid <= 1'b1; + f_tdata <= rbyte; // received a correct byte, output it + end + end + end + end + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// RX fifo +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +wire f_tready; + +generate if (FIFO_EA <= 0) begin // no RX fifo + + assign f_tready = o_tready; + always @ (*) o_tvalid = f_tvalid; + always @ (*) o_tdata = f_tdata; + +end else begin // TX fifo + + localparam EA = (FIFO_EA <= 2) ? 2 : FIFO_EA; + + reg [7:0] buffer [ ((1<= 0) ? (BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0)) : 0 ) + + ( (index >= 1) ? (BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0)) : 0 ) + + ( (index >= 2) ? (BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0)) : 0 ) + + ( (index >= 3) ? (BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0)) : 0 ) + + ( (index >= 4) ? (BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0)) : 0 ) + + ( (index >= 5) ? (BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0)) : 0 ) + + ( (index >= 6) ? (BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0)) : 0 ) + + ( (index >= 7) ? (BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0)) : 0 ) + + ( (index >= 8) ? (BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0)) : 0 ) + + ( (index >= 9) ? (BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0)) : 0 ) ; + + localparam real ideal_time_ns = ((index+1)*1000000000.0/BAUD_RATE); + localparam real actual_time_ns = (cycles_acc*1000000000.0/CLK_FREQ); + localparam real uncertainty = (1000000000.0/CLK_FREQ); + localparam real error = ( (ideal_time_ns>actual_time_ns) ? (ideal_time_ns-actual_time_ns) : (-ideal_time_ns+actual_time_ns) ) + uncertainty; + localparam real relative_error_percent = (error / (1000000000.0/BAUD_RATE)) * 100.0; + + initial if (PARITY == "ODD" || PARITY == "EVEN" || index < 9) begin + $display("uart_rx : t%-2d- t0 = %.0f ns (ideal) %.0f +- %.0f ns (actual). error=%.0f ns relative_error=%.3f%%" , + (index+1) , + ideal_time_ns , + actual_time_ns, + uncertainty, + error, + relative_error_percent + ); + + if ( relative_error_percent > 8.0 ) begin $error("relative_error is too large"); $stop; end // if relative error larger than 8% + end + end +endgenerate + + +endmodule diff --git a/example-uart-read-write/uart/uart_tx.v b/example-uart-read-write/uart/uart_tx.v new file mode 100644 index 0000000..f07d505 --- /dev/null +++ b/example-uart-read-write/uart/uart_tx.v @@ -0,0 +1,340 @@ + +//-------------------------------------------------------------------------------------------------------- +// Module : uart_tx +// Type : synthesizable, IP's top +// Standard: Verilog 2001 (IEEE1364-2001) +// Function: input AXI-stream (configurable data width), +// output UART signal +//-------------------------------------------------------------------------------------------------------- + +module uart_tx #( + // clock frequency + parameter CLK_FREQ = 50000000, // clk frequency, Unit : Hz + // UART format + parameter BAUD_RATE = 115200, // Unit : Hz + parameter PARITY = "NONE", // "NONE", "ODD", or "EVEN" + parameter STOP_BITS = 2, // can be 1, 2, 3, 4, ... + // AXI stream data width + parameter BYTE_WIDTH = 1, // can be 1, 2, 3, 4, ... + // TX fifo depth + parameter FIFO_EA = 0, // 0:no fifo 1,2:depth=4 3:depth=8 4:depth=16 ... 10:depth=1024 11:depth=2048 ... + // do you want to send extra byte after each AXI-stream transfer or packet? + parameter EXTRA_BYTE_AFTER_TRANSFER = "", // specify a extra byte to send after each AXI-stream transfer. when ="", do not send this extra byte + parameter EXTRA_BYTE_AFTER_PACKET = "" // specify a extra byte to send after each AXI-stream packet . when ="", do not send this extra byte +) ( + input wire rstn, + input wire clk, + // input stream : AXI-stream slave. Associated clock = clk + output wire i_tready, + input wire i_tvalid, + input wire [8*BYTE_WIDTH-1:0] i_tdata, + input wire [ BYTE_WIDTH-1:0] i_tkeep, + input wire i_tlast, + // UART TX output signal + output reg o_uart_tx +); + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// TX fifo +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +wire f_tready; +reg f_tvalid; +reg [8*BYTE_WIDTH-1:0] f_tdata; +reg [ BYTE_WIDTH-1:0] f_tkeep; +reg f_tlast; + +generate if (FIFO_EA <= 0) begin // no TX fifo + + assign i_tready = f_tready; + always @ (*) f_tvalid = i_tvalid; + always @ (*) f_tdata = i_tdata; + always @ (*) f_tkeep = i_tkeep; + always @ (*) f_tlast = i_tlast; + +end else begin // TX fifo + + localparam EA = (FIFO_EA<=2) ? 2 : FIFO_EA; + localparam DW = ( 1 + BYTE_WIDTH + 8*BYTE_WIDTH ); // 1-bit tlast, (BYTE_WIDTH)-bit tkeep, (8*BYTE_WIDTH)-bit tdata + + reg [DW-1:0] buffer [ ((1<= ('hFFFFFFFF-9-PARITY_BITS)) ? 'hFFFFFFFF : (PARITY_BITS+STOP_BITS+9); + +localparam [ 0:0] BYTE_T_EN = (EXTRA_BYTE_AFTER_TRANSFER == "") ? 1'b0 : 1'b1; +localparam [ 0:0] BYTE_B_EN = (EXTRA_BYTE_AFTER_PACKET == "") ? 1'b0 : 1'b1; +localparam [ 7:0] BYTE_T = EXTRA_BYTE_AFTER_TRANSFER; +localparam [ 7:0] BYTE_P = EXTRA_BYTE_AFTER_PACKET; + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// function for calculate parity bit +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +function [0:0] get_parity; + input [7:0] data; +begin + get_parity = (PARITY == "ODD" ) ? (~(^(data[7:0]))) : + (PARITY == "EVEN") ? (^(data[7:0])) : + /*(PARITY == "NONE")*/ 1'b1 ; +end +endfunction + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// main FSM +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +localparam [ 1:0] S_IDLE = 2'b01 , // only in state S_IDLE, state[0]==1, the goal is to make f_tready pure register-out + S_PREPARE = 2'b00 , + S_TX = 2'b10 ; + +reg [ 1:0] state = S_IDLE; // FSM state register + +reg [8*BYTE_WIDTH-1:0] data = 0; +reg [ BYTE_WIDTH-1:0] keep = 0; +reg byte_t_en = 1'b0; +reg byte_p_en = 1'b0; +reg [ 9:0] txbits = 10'b0; +reg [ 31:0] txcnt = 0; +reg [ 31:0] cycle = 1; + + +always @ (posedge clk or negedge rstn) + if (~rstn) begin + state <= S_IDLE; + data <= 0; + keep <= 0; + byte_t_en <= 1'b0; + byte_p_en <= 1'b0; + txbits <= 10'b0; + txcnt <= 0; + cycle <= 1; + end else begin + case (state) + S_IDLE : begin + state <= f_tvalid ? S_PREPARE : S_IDLE; + data <= f_tdata; + keep <= f_tkeep; + byte_t_en <= BYTE_T_EN; + byte_p_en <= BYTE_B_EN & f_tlast; + txbits <= 10'b0; + txcnt <= 0; + cycle <= 1; + end + + S_PREPARE : begin + data <= (data >> 8); + keep <= (keep >> 1); + if ( keep[0] == 1'b1 ) begin + txbits <= {get_parity(data[7:0]), data[7:0], 1'b0}; + state <= S_TX; + end else if ( keep != ZERO_KEEP ) begin + state <= S_PREPARE; + end else if ( byte_t_en ) begin + byte_t_en <= 1'b0; + txbits <= {get_parity(BYTE_T), BYTE_T, 1'b0}; + state <= S_TX; + end else if ( byte_p_en ) begin + byte_p_en <= 1'b0; + txbits <= {get_parity(BYTE_P), BYTE_P, 1'b0}; + state <= S_TX; + end else begin + state <= S_IDLE; + end + txcnt <= 0; + cycle <= 1; + end + + default : begin // S_TX + if (keep[0] == 1'b0) begin + data <= (data >> 8); + keep <= (keep >> 1); + end + if ( cycle < ((txcnt<=9) ? cycles[txcnt] : STOP_BIT_CYCLES) ) begin // cycle loop from 1 to ((txcnt<=9) ? cycles[txcnt] : STOP_BIT_CYCLES) + cycle <= cycle + 1; + end else begin + cycle <= 1; + txbits <= {1'b1, txbits[9:1]}; // right shift txbits, and fill '1' to MSB + if ( txcnt < (TOTAL_BITS-1) ) begin // txcnt loop from 0 to (TOTAL_BITS-1) + txcnt <= txcnt + 1; + end else begin + txcnt <= 0; + state <= S_PREPARE; + end + end + end + endcase + end + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// generate UART output +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +initial o_uart_tx = 1'b1; + +always @ (posedge clk or negedge rstn) + if (~rstn) + o_uart_tx <= 1'b1; + else + o_uart_tx <= (state == S_TX) ? txbits[0] : 1'b1; + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// generate AXI-stream TREADY +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +assign f_tready = state[0]; // (state == S_IDLE) + + + +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +// parameter checking +//--------------------------------------------------------------------------------------------------------------------------------------------------------------- +initial begin + if (BYTE_WIDTH <= 0) begin $error("invalid parameter : BYTE_WIDTH<=0"); $stop; end + if (STOP_BITS <= 0) begin $error("invalid parameter : STOP_BITS <=0"); $stop; end + if (BAUD_CYCLES < 1) begin $error("invalid parameter : BAUD_CYCLES < 1, please use a faster driving clock"); $stop; end + + $display("uart_tx : parity = %s" , PARITY ); + $display("uart_tx : clock period = %.0f ns (%-10d Hz)" , 1000000000.0/CLK_FREQ , CLK_FREQ ); + $display("uart_tx : baud rate period = %.0f ns (%-10d Hz)" , 1000000000.0/BAUD_RATE , BAUD_RATE); + $display("uart_tx : baud cycles = %-10d" , BAUD_CYCLES ); + $display("uart_tx : baud cycles frac = %-10d" , BAUD_CYCLES_FRAC ); + + if (PARITY == "ODD" || PARITY == "EVEN") begin + $display("uart_tx : __ ____ ____ ____ ____ ____ ____ ____ ____________ "); + $display("uart_tx : wave \\____/____X____X____X____X____X____X____X____X____/ "); + $display("uart_tx : bits | S | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | P | "); + $display("uart_tx : time_points t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 "); + $display("uart_tx :"); + end else begin + $display("uart_tx : __ ____ ____ ____ ____ ____ ____ ____ _______ "); + $display("uart_tx : wave \\____/____X____X____X____X____X____X____X____/ "); + $display("uart_tx : bits | S | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | "); + $display("uart_tx : time_points t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 "); + $display("uart_tx :"); + end +end + +generate genvar index, i; + for (index=0; index<=9; index=index+1) begin : print_and_check_time + localparam cycles_acc = ( (index >= 0) ? (BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0)) : 0 ) + + ( (index >= 1) ? (BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0)) : 0 ) + + ( (index >= 2) ? (BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0)) : 0 ) + + ( (index >= 3) ? (BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0)) : 0 ) + + ( (index >= 4) ? (BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0)) : 0 ) + + ( (index >= 5) ? (BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0)) : 0 ) + + ( (index >= 6) ? (BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0)) : 0 ) + + ( (index >= 7) ? (BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0)) : 0 ) + + ( (index >= 8) ? (BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0)) : 0 ) + + ( (index >= 9) ? (BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0)) : 0 ) ; + + localparam real ideal_time_ns = ((index+1)*1000000000.0/BAUD_RATE); + localparam real actual_time_ns = (cycles_acc*1000000000.0/CLK_FREQ); + localparam real error = (ideal_time_ns>actual_time_ns) ? (ideal_time_ns-actual_time_ns) : (-ideal_time_ns+actual_time_ns); + localparam real relative_error_percent = (error / (1000000000.0/BAUD_RATE)) * 100.0; + + initial if (PARITY == "ODD" || PARITY == "EVEN" || index < 9) begin + $display("uart_tx : t%-2d- t0 = %.0f ns (ideal) %.0f ns (actual). error=%.0f ns relative_error=%.3f%%" , + (index+1) , + ideal_time_ns , + actual_time_ns, + error, + relative_error_percent + ); + + if ( relative_error_percent > 3.0 ) begin $error("relative_error is too large"); $stop; end // if relative error larger than 3% + end + end +endgenerate + + +endmodule diff --git a/example-uart-read-write/uart2axi4.sv b/example-uart-read-write/uart2axi4.sv deleted file mode 100644 index c0ddc04..0000000 --- a/example-uart-read-write/uart2axi4.sv +++ /dev/null @@ -1,401 +0,0 @@ - -//-------------------------------------------------------------------------------------------------------- -// Module : uart2axi4 -// Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// Function: convert UART command to AXI4 read/write action -//-------------------------------------------------------------------------------------------------------- - -module uart2axi4 #( - parameter A_WIDTH = 26, - parameter D_WIDTH = 16 -) ( - input wire rstn, - input wire clk, - - output wire awvalid, - input wire awready, - output reg [A_WIDTH-1:0] awaddr, - output reg [ 7:0] awlen, - output wire wvalid, - input wire wready, - output wire wlast, - output wire [D_WIDTH-1:0] wdata, - input wire bvalid, - output wire bready, - output wire arvalid, - input wire arready, - output reg [A_WIDTH-1:0] araddr, - output reg [ 7:0] arlen, - input wire rvalid, - output wire rready, - input wire rlast, - input wire [D_WIDTH-1:0] rdata, - - input wire uart_rx, - output wire uart_tx -); - -function automatic logic isW(input [7:0] c); - return c==8'h57 || c==8'h77; -endfunction - -function automatic logic isR(input [7:0] c); - return c==8'h52 || c==8'h72; -endfunction - -function automatic logic isSpace(input [7:0] c); - return c==8'h20 || c==8'h09; -endfunction - -function automatic logic isNewline(input [7:0] c); - return c==8'h0D || c==8'h0A; -endfunction - -function automatic logic [3:0] isHex(input [7:0] c); - if(c>=8'h30 && c<= 8'h39) - return 1'b1; - else if(c>=8'h41 && c<=8'h46 || c>=8'h61 && c<=8'h66) - return 1'b1; - else - return 1'b0; -endfunction - -function automatic logic [3:0] getHex(input [7:0] c); - if(c>=8'h30 && c<= 8'h39) - return c[3:0]; - else if(c>=8'h41 && c<=8'h46 || c>=8'h61 && c<=8'h66) - return c[3:0] + 8'h9; - else - return 4'd0; -endfunction - -localparam V_WIDTH = A_WIDTH>D_WIDTH ? (A_WIDTH>8?A_WIDTH:8) : (D_WIDTH>8?D_WIDTH:8); - -wire rx_valid; -wire [7:0] rx_data; - -reg rw; // 0:write 1:read -reg [V_WIDTH-1:0] value; -reg [ 7:0] value_cnt; -reg wbuf_wen; -reg [ 7:0] wbuf_waddr; -reg [D_WIDTH-1:0] wbuf_wdata; -reg [ 7:0] wbuf_raddr; -reg [D_WIDTH-1:0] wbuf_rdata; -enum logic [3:0] {IDLE, INVALID, GADDR, GRLEN, GWDATA, AXI_AR, AXI_R, AXI_AW, AXI_W, AXI_B} stat; -wire[ 7:0] wbuf_raddr_n = stat == AXI_W && wready ? wbuf_raddr + 8'd1 : wbuf_raddr; - -assign awvalid = stat == AXI_AW; -assign wvalid = stat == AXI_W; -assign wlast = wbuf_raddr == wbuf_waddr; -assign wdata = wbuf_rdata; -assign bready = stat == AXI_B; -assign arvalid = stat == AXI_AR; - -always @ (posedge clk or negedge rstn) - if(~rstn) begin - awaddr <= '0; - awlen <= '0; - araddr <= '0; - arlen <= '0; - rw <= 1'b0; - value <= '0; - value_cnt <= '0; - wbuf_wen <= 1'b0; - wbuf_waddr <= '0; - wbuf_wdata <= '0; - wbuf_raddr <= '0; - stat <= IDLE; - end else begin - wbuf_wen <= 1'b0; - case(stat) - IDLE: if(rx_valid) begin - value <= '0; - value_cnt <= '0; - wbuf_raddr <= '0; - if( isW(rx_data) ) begin - rw <= 1'b0; - stat <= GADDR; - end else if( isR(rx_data) ) begin - rw <= 1'b1; - stat <= GADDR; - end else if( ~isNewline(rx_data) ) begin - stat <= INVALID; - end - end - GADDR: if(rx_valid) begin - if( isNewline(rx_data) ) begin - value <= '0; - stat <= IDLE; - end else if( isSpace(rx_data) ) begin - value <= '0; - if(rw) begin - araddr <= value[A_WIDTH-1:0]; - stat <= GRLEN; - end else begin - awaddr <= value[A_WIDTH-1:0]; - stat <= GWDATA; - end - end else if( isHex(rx_data) ) begin - value <= { value[V_WIDTH-5:0], getHex(rx_data) }; - end else begin - stat <= INVALID; - end - end - GRLEN: if(rx_valid) begin - if( isNewline(rx_data) ) begin - value <= '0; - arlen <= value[7:0]; - stat <= AXI_AR; - end else if( isHex(rx_data) ) begin - value <= { value[V_WIDTH-5:0], getHex(rx_data) }; - end else begin - stat <= INVALID; - end - end - GWDATA: if(rx_valid) begin - if( isNewline(rx_data) ) begin - wbuf_wen <= 1'b1; - wbuf_waddr <= value_cnt; - wbuf_wdata <= value[D_WIDTH-1:0]; - awlen <= value_cnt; - stat <= AXI_AW; - end else if( isSpace(rx_data) ) begin - value <= '0; - value_cnt <= value_cnt + 8'd1; - wbuf_wen <= 1'b1; - wbuf_waddr <= value_cnt; - wbuf_wdata <= value[D_WIDTH-1:0]; - end else if( isHex(rx_data) ) begin - value <= { value[V_WIDTH-5:0], getHex(rx_data) }; - end else begin - stat <= INVALID; - end - end - INVALID: if( rx_valid ) begin - if ( isNewline(rx_data) ) - stat <= IDLE; - end - AXI_AR: if(arready) begin - stat <= AXI_R; - end - AXI_R: if(rvalid & rready & rlast) begin - stat <= IDLE; - end - AXI_AW: if(awready) begin - stat <= AXI_W; - end - AXI_W: if(wready) begin - wbuf_raddr <= wbuf_raddr + 8'd1; - if(wbuf_raddr==awlen) - stat <= AXI_B; - end - AXI_B: if(bvalid) begin - stat <= IDLE; - end - default: stat<=IDLE; - endcase - end - - - -logic [D_WIDTH-1:0] mem_for_axi4write [256]; - -always @ (posedge clk) - wbuf_rdata <= mem_for_axi4write[wbuf_raddr_n]; - -always @ (posedge clk) - if(wbuf_wen) - mem_for_axi4write[wbuf_waddr] <= wbuf_wdata; - - - -localparam CLK_DIV = 162; -localparam CLK_PART = 6; - -reg uart_rx_done = 1'b0; -reg [ 7:0] uart_rx_data = 8'h0; -reg [ 2:0] uart_rx_supercnt=3'h0; -reg [31:0] uart_rx_cnt = 0; -reg [ 7:0] uart_rx_databuf = 8'h0; -reg [ 5:0] uart_rx_status=6'h0, uart_rx_shift=6'h0; -reg uart_rxr=1'b1; -wire recvbit = (uart_rx_shift[1]&uart_rx_shift[0]) | (uart_rx_shift[0]&uart_rxr) | (uart_rxr&uart_rx_shift[1]) ; -wire [2:0] supercntreverse = {uart_rx_supercnt[0], uart_rx_supercnt[1], uart_rx_supercnt[2]}; - -assign rx_valid = uart_rx_done; -assign rx_data = uart_rx_data; - -always @ (posedge clk or negedge rstn) - if(~rstn) - uart_rxr <= 1'b1; - else - uart_rxr <= uart_rx; - -always @ (posedge clk or negedge rstn) - if(~rstn) begin - uart_rx_done <= 1'b0; - uart_rx_data <= 8'h0; - uart_rx_supercnt<= 3'h0; - uart_rx_status <= 6'h0; - uart_rx_shift <= 6'h0; - uart_rx_databuf <= 8'h0; - uart_rx_cnt <= 0; - end else begin - uart_rx_done <= 1'b0; - if( (supercntreverse=CLK_DIV) : (uart_rx_cnt>=CLK_DIV-1) ) begin - if(uart_rx_status==0) begin - if(uart_rx_shift == 6'b111_000) - uart_rx_status <= 1; - end else begin - if(uart_rx_status[5] == 1'b0) begin - if(uart_rx_status[1:0] == 2'b11) - uart_rx_databuf <= {recvbit, uart_rx_databuf[7:1]}; - uart_rx_status <= uart_rx_status + 5'b1; - end else begin - if(uart_rx_status<62) begin - uart_rx_status <= 62; - uart_rx_data <= uart_rx_databuf; - uart_rx_done <= 1'b1; - end else begin - uart_rx_status <= uart_rx_status + 6'd1; - end - end - end - uart_rx_shift <= {uart_rx_shift[4:0], uart_rxr}; - uart_rx_supercnt <= uart_rx_supercnt + 3'h1; - uart_rx_cnt <= 0; - end else - uart_rx_cnt <= uart_rx_cnt + 1; - end - - - -axis2uarttx #( - .CLK_DIV ( 651 ), - .DATA_WIDTH ( D_WIDTH ), - .FIFO_ASIZE ( 10 ) -) uart_tx_i ( - .rstn ( rstn ), - .clk ( clk ), - .tvalid ( rvalid ), - .tready ( rready ), - .tlast ( rlast ), - .tdata ( rdata ), - .uart_tx ( uart_tx ) -); - -endmodule - - - - - - -module axis2uarttx #( - parameter CLK_DIV = 434, - parameter DATA_WIDTH = 32, - parameter FIFO_ASIZE = 8 -) ( - // AXI-stream (slave) side - input logic rstn, - input logic clk, - input logic tvalid, - input logic tlast, - output logic tready, - input logic [DATA_WIDTH-1:0] tdata, - // UART TX signal - output logic uart_tx -); -localparam TX_WIDTH = (DATA_WIDTH+3) / 4; - -function automatic logic [7:0] hex2ascii (input [3:0] hex); - return {4'h3, hex} + ((hex<4'hA) ? 8'h0 : 8'h7) ; -endfunction - -logic uart_txb; -logic [FIFO_ASIZE-1:0] fifo_rpt='0, fifo_wpt='0; -wire [FIFO_ASIZE-1:0] fifo_wpt_next = fifo_wpt + {{(FIFO_ASIZE-1){1'b0}}, 1'b1}; -wire [FIFO_ASIZE-1:0] fifo_rpt_next = fifo_rpt + {{(FIFO_ASIZE-1){1'b0}}, 1'b1}; -logic [31:0] cyccnt=0, hexcnt=0, txcnt=0; -logic [ 7:0] txshift = '1; -logic fifo_tlast; -logic [DATA_WIDTH-1:0] fifo_data; -logic endofline = 1'b0; -logic [TX_WIDTH*4-1:0] data='0; -wire emptyn = (fifo_rpt != fifo_wpt); -assign tready = (fifo_rpt != fifo_wpt_next) & rstn; - -always @ (posedge clk or negedge rstn) - if(~rstn) - uart_tx <= 1'b1; - else begin - uart_tx <= uart_txb; - end - -always @ (posedge clk or negedge rstn) - if(~rstn) - fifo_wpt <= '0; - else begin - if(tvalid & tready) fifo_wpt <= fifo_wpt_next; - end - -always @ (posedge clk or negedge rstn) - if(~rstn) - cyccnt <= 0; - else - cyccnt <= (cyccnt1) - txshift <= hex2ascii(data[(hexcnt-2)*4+:4]); - else if(endofline) - txshift <= 8'h0A; - else - txshift <= 8'h20; - txcnt <= 11; - end - end - end else if(emptyn) begin - uart_txb <= 1'b1; - hexcnt <= 2 + TX_WIDTH; - txcnt <= 0; - fifo_rpt <= fifo_rpt_next; - end - end - - -logic [DATA_WIDTH:0] mem_for_axi_stream_to_uart_tx_fifo [1<U-LVu{zMMQe#~ zB(wkleDOKYIp^N{<=zkX)Bf$f*37J#S+myu&rFQ2whGx@`nxzdIAm(7iuyP>cYfjE z;8x?~-F`VvB9yp&JkixOR6-ve_4N-{Rz|$e{e}ykF9*qM>*|Vml;FsK?YZs{kci(- zOexAy$H8HNt0^iNf|d|DP#|pRW6$QctyeRC01k3D0nat+TU<%AV}4cwUBKe>TO3Xy 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