# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
# Date created = 17:45:24  January 23, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		ddr_test_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:24  JANUARY 23, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name SYSTEMVERILOG_FILE RTL/top.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/ddr_sdram_ctrl.sv
set_global_assignment -name SYSTEMVERILOG_FILE RTL/uart2axi4.sv
set_global_assignment -name SYSTEMVERILOG_FILE RTL/axis2uarttx.sv
set_global_assignment -name SYSTEMVERILOG_FILE RTL/uart_rx.sv
set_global_assignment -name VERILOG_FILE IP/pll.v

set_location_assignment PIN_23 -to clk50m

set_location_assignment PIN_28 -to uart_tx
set_location_assignment PIN_25 -to uart_rx

set_location_assignment PIN_10 -to ddr_cs_n
set_location_assignment PIN_30 -to ddr_ras_n
set_location_assignment PIN_31 -to ddr_cas_n
set_location_assignment PIN_32 -to ddr_we_n
set_location_assignment PIN_86 -to ddr_cke
set_location_assignment PIN_85 -to ddr_ck_p
set_location_assignment PIN_84 -to ddr_ck_n
set_location_assignment PIN_7 -to ddr_ba[0]
set_location_assignment PIN_3 -to ddr_ba[1]
set_location_assignment PIN_1 -to ddr_a[0]
set_location_assignment PIN_144 -to ddr_a[1]
set_location_assignment PIN_143 -to ddr_a[2]
set_location_assignment PIN_142 -to ddr_a[3]
set_location_assignment PIN_106 -to ddr_a[4]
set_location_assignment PIN_105 -to ddr_a[5]
set_location_assignment PIN_104 -to ddr_a[6]
set_location_assignment PIN_103 -to ddr_a[7]
set_location_assignment PIN_100 -to ddr_a[8]
set_location_assignment PIN_99 -to ddr_a[9]
set_location_assignment PIN_2 -to ddr_a[10]
set_location_assignment PIN_98 -to ddr_a[11]
set_location_assignment PIN_87 -to ddr_a[12]
set_location_assignment PIN_83 -to ddr_dm[0]
set_location_assignment PIN_80 -to ddr_dqs[0]
set_location_assignment PIN_38 -to ddr_dq[0]
set_location_assignment PIN_39 -to ddr_dq[1]
set_location_assignment PIN_34 -to ddr_dq[2]
set_location_assignment PIN_33 -to ddr_dq[3]
set_location_assignment PIN_76 -to ddr_dq[4]
set_location_assignment PIN_75 -to ddr_dq[5]
set_location_assignment PIN_74 -to ddr_dq[6]
set_location_assignment PIN_73 -to ddr_dq[7]


set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top