FPGA/FPGA-DDR-SDRAM
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FPGA-DDR-SDRAM/SIM
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WangXuan95 ffa1fe0414 change to Verilog2001
2023-06-06 19:52:19 +08:00
..
axi_self_test_master.v
change to Verilog2001
2023-06-06 19:52:19 +08:00
micron_ddr_sdram_model.v
change to Verilog2001
2023-06-06 19:52:19 +08:00
tb_ddr_sdram_ctrl_run_iverilog.bat
change to Verilog2001
2023-06-06 19:52:19 +08:00
tb_ddr_sdram_ctrl.v
change to Verilog2001
2023-06-06 19:52:19 +08:00