FPGA-DDR-SDRAM/tb_ddr_sdram_ctrl_run_iverilog.bat at main - FPGA-DDR-SDRAM - Gitea: Git with a cup of tea

FPGA/FPGA-DDR-SDRAM

mirror of https://github.com/WangXuan95/FPGA-DDR-SDRAM.git synced 2025-01-30 02:32:53 +08:00

WangXuan95 ffa1fe0414 change to Verilog2001

2023-06-06 19:52:19 +08:00

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Batchfile

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 del sim.out dump.vcd
 iverilog  -g2001  -o sim.out  tb_ddr_sdram_ctrl.v  axi_self_test_master.v  micron_ddr_sdram_model.v  ../RTL/ddr_sdram_ctrl.v
 vvp -n sim.out
 del sim.out
 pause