FPGA/FPGA-DDR-SDRAM
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FPGA-DDR-SDRAM/example-selftest
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WangXuan95 ffa1fe0414 change to Verilog2001
2023-06-06 19:52:19 +08:00
..
SignalTap
change to Verilog2001
2023-06-06 19:52:19 +08:00
axi_self_test_master.v
change to Verilog2001
2023-06-06 19:52:19 +08:00
ddr_test.qpf
first commit
2021-01-27 18:06:35 +08:00
ddr_test.qsf
change to Verilog2001
2023-06-06 19:52:19 +08:00
fpga_top.v
change to Verilog2001
2023-06-06 19:52:19 +08:00