FPGA/FPGA-DDR-SDRAM
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FPGA-DDR-SDRAM/example-uart-read-write
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WangXuan95 2c6c3843a8 change to Verilog2001
2023-06-08 18:36:04 +08:00
..
uart
change to Verilog2001
2023-06-08 18:36:04 +08:00
ddr_test.qpf
first commit
2021-01-27 18:06:35 +08:00
ddr_test.qsf
change to Verilog2001
2023-06-06 19:52:19 +08:00
fpga_top.v
change to Verilog2001
2023-06-06 19:52:19 +08:00
UartSession.exe
update
2022-04-04 19:07:30 +08:00