FPGA/FPGA-DDR-SDRAM
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FPGA-DDR-SDRAM/example-uart-read-write/uart
History
WangXuan95 2c6c3843a8 change to Verilog2001
2023-06-08 18:36:04 +08:00
..
uart2axi4.v
change to Verilog2001
2023-06-06 19:52:19 +08:00
uart_rx.v
change to Verilog2001
2023-06-08 18:36:04 +08:00
uart_tx.v
change to Verilog2001
2023-06-06 19:52:19 +08:00