mirror of
https://github.com/WangXuan95/FPGA-DDR-SDRAM.git
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402 lines
12 KiB
Systemverilog
402 lines
12 KiB
Systemverilog
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//--------------------------------------------------------------------------------------------------------
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// Module : uart2axi4
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// Type : synthesizable
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// Standard: SystemVerilog 2005 (IEEE1800-2005)
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// Function: convert UART command to AXI4 read/write action
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//--------------------------------------------------------------------------------------------------------
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module uart2axi4 #(
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parameter A_WIDTH = 26,
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parameter D_WIDTH = 16
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) (
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input wire rstn,
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input wire clk,
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output wire awvalid,
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input wire awready,
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output reg [A_WIDTH-1:0] awaddr,
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output reg [ 7:0] awlen,
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output wire wvalid,
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input wire wready,
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output wire wlast,
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output wire [D_WIDTH-1:0] wdata,
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input wire bvalid,
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output wire bready,
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output wire arvalid,
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input wire arready,
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output reg [A_WIDTH-1:0] araddr,
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output reg [ 7:0] arlen,
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input wire rvalid,
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output wire rready,
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input wire rlast,
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input wire [D_WIDTH-1:0] rdata,
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input wire uart_rx,
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output wire uart_tx
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);
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function automatic logic isW(input [7:0] c);
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return c==8'h57 || c==8'h77;
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endfunction
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function automatic logic isR(input [7:0] c);
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return c==8'h52 || c==8'h72;
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endfunction
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function automatic logic isSpace(input [7:0] c);
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return c==8'h20 || c==8'h09;
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endfunction
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function automatic logic isNewline(input [7:0] c);
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return c==8'h0D || c==8'h0A;
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endfunction
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function automatic logic [3:0] isHex(input [7:0] c);
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if(c>=8'h30 && c<= 8'h39)
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return 1'b1;
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else if(c>=8'h41 && c<=8'h46 || c>=8'h61 && c<=8'h66)
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return 1'b1;
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else
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return 1'b0;
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endfunction
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function automatic logic [3:0] getHex(input [7:0] c);
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if(c>=8'h30 && c<= 8'h39)
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return c[3:0];
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else if(c>=8'h41 && c<=8'h46 || c>=8'h61 && c<=8'h66)
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return c[3:0] + 8'h9;
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else
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return 4'd0;
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endfunction
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localparam V_WIDTH = A_WIDTH>D_WIDTH ? (A_WIDTH>8?A_WIDTH:8) : (D_WIDTH>8?D_WIDTH:8);
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wire rx_valid;
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wire [7:0] rx_data;
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reg rw; // 0:write 1:read
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reg [V_WIDTH-1:0] value;
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reg [ 7:0] value_cnt;
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reg wbuf_wen;
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reg [ 7:0] wbuf_waddr;
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reg [D_WIDTH-1:0] wbuf_wdata;
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reg [ 7:0] wbuf_raddr;
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reg [D_WIDTH-1:0] wbuf_rdata;
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enum logic [3:0] {IDLE, INVALID, GADDR, GRLEN, GWDATA, AXI_AR, AXI_R, AXI_AW, AXI_W, AXI_B} stat;
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wire[ 7:0] wbuf_raddr_n = stat == AXI_W && wready ? wbuf_raddr + 8'd1 : wbuf_raddr;
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assign awvalid = stat == AXI_AW;
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assign wvalid = stat == AXI_W;
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assign wlast = wbuf_raddr == wbuf_waddr;
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assign wdata = wbuf_rdata;
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assign bready = stat == AXI_B;
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assign arvalid = stat == AXI_AR;
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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awaddr <= '0;
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awlen <= '0;
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araddr <= '0;
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arlen <= '0;
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rw <= 1'b0;
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value <= '0;
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value_cnt <= '0;
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wbuf_wen <= 1'b0;
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wbuf_waddr <= '0;
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wbuf_wdata <= '0;
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wbuf_raddr <= '0;
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stat <= IDLE;
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end else begin
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wbuf_wen <= 1'b0;
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case(stat)
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IDLE: if(rx_valid) begin
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value <= '0;
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value_cnt <= '0;
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wbuf_raddr <= '0;
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if( isW(rx_data) ) begin
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rw <= 1'b0;
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stat <= GADDR;
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end else if( isR(rx_data) ) begin
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rw <= 1'b1;
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stat <= GADDR;
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end else if( ~isNewline(rx_data) ) begin
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stat <= INVALID;
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end
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end
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GADDR: if(rx_valid) begin
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if( isNewline(rx_data) ) begin
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value <= '0;
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stat <= IDLE;
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end else if( isSpace(rx_data) ) begin
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value <= '0;
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if(rw) begin
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araddr <= value[A_WIDTH-1:0];
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stat <= GRLEN;
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end else begin
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awaddr <= value[A_WIDTH-1:0];
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stat <= GWDATA;
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end
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end else if( isHex(rx_data) ) begin
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value <= { value[V_WIDTH-5:0], getHex(rx_data) };
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end else begin
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stat <= INVALID;
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end
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end
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GRLEN: if(rx_valid) begin
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if( isNewline(rx_data) ) begin
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value <= '0;
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arlen <= value[7:0];
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stat <= AXI_AR;
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end else if( isHex(rx_data) ) begin
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value <= { value[V_WIDTH-5:0], getHex(rx_data) };
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end else begin
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stat <= INVALID;
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end
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end
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GWDATA: if(rx_valid) begin
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if( isNewline(rx_data) ) begin
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wbuf_wen <= 1'b1;
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wbuf_waddr <= value_cnt;
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wbuf_wdata <= value[D_WIDTH-1:0];
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awlen <= value_cnt;
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stat <= AXI_AW;
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end else if( isSpace(rx_data) ) begin
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value <= '0;
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value_cnt <= value_cnt + 8'd1;
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wbuf_wen <= 1'b1;
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wbuf_waddr <= value_cnt;
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wbuf_wdata <= value[D_WIDTH-1:0];
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end else if( isHex(rx_data) ) begin
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value <= { value[V_WIDTH-5:0], getHex(rx_data) };
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end else begin
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stat <= INVALID;
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end
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end
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INVALID: if( rx_valid ) begin
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if ( isNewline(rx_data) )
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stat <= IDLE;
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end
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AXI_AR: if(arready) begin
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stat <= AXI_R;
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end
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AXI_R: if(rvalid & rready & rlast) begin
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stat <= IDLE;
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end
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AXI_AW: if(awready) begin
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stat <= AXI_W;
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end
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AXI_W: if(wready) begin
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wbuf_raddr <= wbuf_raddr + 8'd1;
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if(wbuf_raddr==awlen)
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stat <= AXI_B;
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end
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AXI_B: if(bvalid) begin
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stat <= IDLE;
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end
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default: stat<=IDLE;
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endcase
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end
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logic [D_WIDTH-1:0] mem_for_axi4write [256];
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always @ (posedge clk)
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wbuf_rdata <= mem_for_axi4write[wbuf_raddr_n];
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always @ (posedge clk)
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if(wbuf_wen)
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mem_for_axi4write[wbuf_waddr] <= wbuf_wdata;
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localparam CLK_DIV = 162;
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localparam CLK_PART = 6;
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reg uart_rx_done = 1'b0;
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reg [ 7:0] uart_rx_data = 8'h0;
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reg [ 2:0] uart_rx_supercnt=3'h0;
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reg [31:0] uart_rx_cnt = 0;
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reg [ 7:0] uart_rx_databuf = 8'h0;
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reg [ 5:0] uart_rx_status=6'h0, uart_rx_shift=6'h0;
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reg uart_rxr=1'b1;
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wire recvbit = (uart_rx_shift[1]&uart_rx_shift[0]) | (uart_rx_shift[0]&uart_rxr) | (uart_rxr&uart_rx_shift[1]) ;
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wire [2:0] supercntreverse = {uart_rx_supercnt[0], uart_rx_supercnt[1], uart_rx_supercnt[2]};
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assign rx_valid = uart_rx_done;
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assign rx_data = uart_rx_data;
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always @ (posedge clk or negedge rstn)
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if(~rstn)
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uart_rxr <= 1'b1;
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else
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uart_rxr <= uart_rx;
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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uart_rx_done <= 1'b0;
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uart_rx_data <= 8'h0;
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uart_rx_supercnt<= 3'h0;
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uart_rx_status <= 6'h0;
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uart_rx_shift <= 6'h0;
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uart_rx_databuf <= 8'h0;
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uart_rx_cnt <= 0;
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end else begin
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uart_rx_done <= 1'b0;
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if( (supercntreverse<CLK_PART) ? (uart_rx_cnt>=CLK_DIV) : (uart_rx_cnt>=CLK_DIV-1) ) begin
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if(uart_rx_status==0) begin
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if(uart_rx_shift == 6'b111_000)
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uart_rx_status <= 1;
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end else begin
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if(uart_rx_status[5] == 1'b0) begin
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if(uart_rx_status[1:0] == 2'b11)
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uart_rx_databuf <= {recvbit, uart_rx_databuf[7:1]};
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uart_rx_status <= uart_rx_status + 5'b1;
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end else begin
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if(uart_rx_status<62) begin
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uart_rx_status <= 62;
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uart_rx_data <= uart_rx_databuf;
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uart_rx_done <= 1'b1;
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end else begin
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uart_rx_status <= uart_rx_status + 6'd1;
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end
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end
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end
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uart_rx_shift <= {uart_rx_shift[4:0], uart_rxr};
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uart_rx_supercnt <= uart_rx_supercnt + 3'h1;
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uart_rx_cnt <= 0;
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end else
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uart_rx_cnt <= uart_rx_cnt + 1;
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end
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axis2uarttx #(
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.CLK_DIV ( 651 ),
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.DATA_WIDTH ( D_WIDTH ),
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.FIFO_ASIZE ( 10 )
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) uart_tx_i (
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.rstn ( rstn ),
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.clk ( clk ),
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.tvalid ( rvalid ),
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.tready ( rready ),
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.tlast ( rlast ),
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.tdata ( rdata ),
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.uart_tx ( uart_tx )
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);
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endmodule
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module axis2uarttx #(
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parameter CLK_DIV = 434,
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parameter DATA_WIDTH = 32,
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parameter FIFO_ASIZE = 8
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) (
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// AXI-stream (slave) side
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input logic rstn,
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input logic clk,
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input logic tvalid,
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input logic tlast,
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output logic tready,
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input logic [DATA_WIDTH-1:0] tdata,
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// UART TX signal
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output logic uart_tx
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);
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localparam TX_WIDTH = (DATA_WIDTH+3) / 4;
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function automatic logic [7:0] hex2ascii (input [3:0] hex);
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return {4'h3, hex} + ((hex<4'hA) ? 8'h0 : 8'h7) ;
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endfunction
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logic uart_txb;
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logic [FIFO_ASIZE-1:0] fifo_rpt='0, fifo_wpt='0;
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wire [FIFO_ASIZE-1:0] fifo_wpt_next = fifo_wpt + {{(FIFO_ASIZE-1){1'b0}}, 1'b1};
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wire [FIFO_ASIZE-1:0] fifo_rpt_next = fifo_rpt + {{(FIFO_ASIZE-1){1'b0}}, 1'b1};
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logic [31:0] cyccnt=0, hexcnt=0, txcnt=0;
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logic [ 7:0] txshift = '1;
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logic fifo_tlast;
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logic [DATA_WIDTH-1:0] fifo_data;
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logic endofline = 1'b0;
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logic [TX_WIDTH*4-1:0] data='0;
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wire emptyn = (fifo_rpt != fifo_wpt);
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assign tready = (fifo_rpt != fifo_wpt_next) & rstn;
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always @ (posedge clk or negedge rstn)
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if(~rstn)
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uart_tx <= 1'b1;
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else begin
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uart_tx <= uart_txb;
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end
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always @ (posedge clk or negedge rstn)
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if(~rstn)
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fifo_wpt <= '0;
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else begin
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if(tvalid & tready) fifo_wpt <= fifo_wpt_next;
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end
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always @ (posedge clk or negedge rstn)
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if(~rstn)
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cyccnt <= 0;
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else
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cyccnt <= (cyccnt<CLK_DIV-1) ? cyccnt+1 : 0;
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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fifo_rpt <= '0;
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endofline <= 1'b0;
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data <= '0;
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uart_txb <= 1'b1;
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txshift <= '1;
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txcnt <= 0;
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hexcnt <= 0;
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end else begin
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if( hexcnt>(1+TX_WIDTH) ) begin
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uart_txb <= 1'b1;
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endofline <= fifo_tlast;
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data <= '0;
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data[DATA_WIDTH-1:0] <= fifo_data;
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hexcnt <= hexcnt-1;
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end else if(hexcnt>0 || txcnt>0) begin
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if(cyccnt==CLK_DIV-1) begin
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if(txcnt>0) begin
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{txshift, uart_txb} <= {1'b1, txshift};
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txcnt <= txcnt-1;
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end else begin
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uart_txb <= 1'b0;
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hexcnt <= hexcnt-1;
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if(hexcnt>1)
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txshift <= hex2ascii(data[(hexcnt-2)*4+:4]);
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else if(endofline)
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txshift <= 8'h0A;
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else
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txshift <= 8'h20;
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txcnt <= 11;
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end
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end
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end else if(emptyn) begin
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uart_txb <= 1'b1;
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hexcnt <= 2 + TX_WIDTH;
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txcnt <= 0;
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fifo_rpt <= fifo_rpt_next;
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end
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end
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logic [DATA_WIDTH:0] mem_for_axi_stream_to_uart_tx_fifo [1<<FIFO_ASIZE];
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always @ (posedge clk)
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{fifo_tlast, fifo_data} <= mem_for_axi_stream_to_uart_tx_fifo[fifo_rpt];
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always @ (posedge clk)
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if(tvalid & tready)
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mem_for_axi_stream_to_uart_tx_fifo[fifo_wpt] <= {tlast, tdata};
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endmodule
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