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https://github.com/WangXuan95/FPGA-DDR-SDRAM.git
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124 lines
3.9 KiB
Systemverilog
124 lines
3.9 KiB
Systemverilog
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//--------------------------------------------------------------------------------------------------------
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// Module : axi_self_test_master
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// Type : synthesizable
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// Standard: SystemVerilog 2005 (IEEE1800-2005)
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// Function: write increase data to AXI4 slave,
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// then read data and check whether they are increasing
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//--------------------------------------------------------------------------------------------------------
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module axi_self_test_master #(
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parameter A_WIDTH_TEST = 26,
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parameter A_WIDTH = 26,
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parameter D_WIDTH = 16,
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parameter D_LEVEL = 1,
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parameter [7:0] WBURST_LEN = 8'd7,
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parameter [7:0] RBURST_LEN = 8'd7
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)(
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input wire rstn,
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input wire clk,
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output wire awvalid,
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input wire awready,
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output reg [A_WIDTH-1:0] awaddr,
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output wire [ 7:0] awlen,
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output wire wvalid,
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input wire wready,
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output wire wlast,
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output wire [D_WIDTH-1:0] wdata,
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input wire bvalid,
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output wire bready,
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output wire arvalid,
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input wire arready,
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output reg [A_WIDTH-1:0] araddr,
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output wire [ 7:0] arlen,
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input wire rvalid,
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output wire rready,
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input wire rlast,
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input wire [D_WIDTH-1:0] rdata,
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output reg error,
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output reg [ 15:0] error_cnt
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);
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initial {awaddr, araddr} = '0;
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initial {error, error_cnt} = '0;
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wire aw_end;
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reg awaddr_carry = '0;
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reg [7:0] w_cnt = '0;
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enum logic [2:0] {INIT, AW, W, B, AR, R} stat = INIT;
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generate if(A_WIDTH_TEST<A_WIDTH)
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assign aw_end = awaddr[A_WIDTH_TEST];
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else
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assign aw_end = awaddr_carry;
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endgenerate
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assign awvalid = stat==AW;
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assign awlen = WBURST_LEN;
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assign wvalid = stat==W;
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assign wlast = w_cnt==WBURST_LEN;
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assign wdata = (D_WIDTH)'(awaddr);
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assign bready = 1'b1;
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assign arvalid = stat==AR;
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assign arlen = RBURST_LEN;
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assign rready = 1'b1;
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wire [A_WIDTH:0] araddr_next = {1'b0,araddr} + (A_WIDTH+1)'(1<<D_LEVEL);
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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{awaddr_carry, awaddr} <= '0;
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w_cnt <= 8'd0;
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araddr <= '0;
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stat <= INIT;
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end else begin
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case(stat)
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INIT: begin
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{awaddr_carry, awaddr} <= '0;
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w_cnt <= 8'd0;
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araddr <= '0;
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stat <= AW;
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end
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AW: if(awready) begin
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w_cnt <= 8'd0;
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stat <= W;
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end
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W: if(wready) begin
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{awaddr_carry, awaddr} <= {awaddr_carry, awaddr} + (A_WIDTH+1)'(1<<D_LEVEL);
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w_cnt <= w_cnt + 8'd1;
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if(wlast)
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stat <= B;
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end
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B: if(bvalid) begin
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stat <= aw_end ? AR : AW;
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end
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AR: if(arready) begin
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stat <= R;
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end
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R: if(rvalid) begin
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araddr <= araddr_next[A_WIDTH-1:0];
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if(rlast) begin
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stat <= AR;
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if(araddr_next[A_WIDTH_TEST])
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araddr <= '0;
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end
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end
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endcase
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end
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// ------------------------------------------------------------
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// read and write mismatch detect
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// ------------------------------------------------------------
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wire [D_WIDTH-1:0] rdata_idle = (D_WIDTH)'(araddr);
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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error <= 1'b0;
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error_cnt <= 16'd0;
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end else begin
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error <= rvalid && rready && rdata!=rdata_idle;
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if(error)
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error_cnt <= error_cnt + 16'd1;
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end
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endmodule
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