FPGA-DDR-SDRAM/RTL at f5d5819e09f7405636e13beaff26576113c8108a - FPGA-DDR-SDRAM - Gitea: Git with a cup of tea

FPGA/FPGA-DDR-SDRAM

mirror of https://github.com/WangXuan95/FPGA-DDR-SDRAM.git synced 2025-01-30 02:32:53 +08:00

History

WangXuan95 a528872406 first commit

2021-01-27 18:06:35 +08:00

..

axis2uarttx.sv

first commit

2021-01-27 18:06:35 +08:00

top.sv

first commit

2021-01-27 18:06:35 +08:00

uart2axi4.sv

first commit

2021-01-27 18:06:35 +08:00

uart_rx.sv

first commit

2021-01-27 18:06:35 +08:00