From 24ce90a1ea2d173b26dceee52fdea046d082b36d Mon Sep 17 00:00:00 2001 From: WangXuan95 <629708558@qq.com> Date: Thu, 8 Jun 2023 20:40:07 +0800 Subject: [PATCH] change to Verilog2001 --- README.md | 363 +++++++------- RTL/{sd_file_reader.sv => sd_file_reader.v} | 189 ++++--- RTL/{sd_reader.sv => sd_reader.v} | 98 ++-- RTL/{sdcmd_ctrl.sv => sdcmd_ctrl.v} | 98 ++-- SIM/{sd_fake.sv => sd_fake.v} | 470 ++++++++++-------- ..._sd_file_reader.sv => tb_sd_file_reader.v} | 8 +- SIM/tb_sd_file_reader_run_iverilog.bat | 2 +- example-vivado-readfile.zip | Bin 0 -> 85564 bytes example-vivado-readfile/Nexys-4-DDR-pins.xdc | 41 -- example-vivado-readfile/Nexys4-ReadFile.xpr | 234 --------- example-vivado-readfile/RTL/top.sv | 84 ---- example-vivado-readfile/RTL/uart_tx.sv | 188 ------- example-vivado-readsector.zip | Bin 0 -> 8350 bytes .../Nexys-4-DDR-pins.xdc | 41 -- .../Nexys4-ReadSector.xpr | 228 --------- example-vivado-readsector/RTL/top.sv | 96 ---- example-vivado-readsector/RTL/uart_tx.sv | 188 ------- figures/pin.png | Bin 23691 -> 0 bytes pin.png | Bin 0 -> 4861 bytes 19 files changed, 708 insertions(+), 1620 deletions(-) rename RTL/{sd_file_reader.sv => sd_file_reader.v} (80%) rename RTL/{sd_reader.sv => sd_reader.v} (76%) rename RTL/{sdcmd_ctrl.sv => sdcmd_ctrl.v} (54%) rename SIM/{sd_fake.sv => sd_fake.v} (54%) rename SIM/{tb_sd_file_reader.sv => tb_sd_file_reader.v} (97%) create mode 100644 example-vivado-readfile.zip delete mode 100644 example-vivado-readfile/Nexys-4-DDR-pins.xdc delete mode 100644 example-vivado-readfile/Nexys4-ReadFile.xpr delete mode 100644 example-vivado-readfile/RTL/top.sv delete mode 100644 example-vivado-readfile/RTL/uart_tx.sv create mode 100644 example-vivado-readsector.zip delete mode 100644 example-vivado-readsector/Nexys-4-DDR-pins.xdc delete mode 100644 example-vivado-readsector/Nexys4-ReadSector.xpr delete mode 100644 example-vivado-readsector/RTL/top.sv delete mode 100644 example-vivado-readsector/RTL/uart_tx.sv delete mode 100644 figures/pin.png create mode 100644 pin.png diff --git a/README.md b/README.md index fb802a5..48bbe36 100644 --- a/README.md +++ b/README.md @@ -1,154 +1,8 @@ -![语言](https://img.shields.io/badge/语言-systemverilog_(IEEE1800_2005)-CAD09D.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg) - -中文 | [English](#en) - -FPGA SDcard File Reader -=========================== - -基于 FPGA 的 SD卡文件读取器 - -* **功能** ：FPGA作为 **SD-host** ， 指定文件名读取文件内容；或指定扇区号读取扇区内容。 -* **性能** ：使用 SD总线，而不是 SPI总线。读取速度更快。 -* **兼容性强** ：自动适配 **SD卡版本** ，自动适配 **FAT16/FAT32文件系统**。 -* 纯 RTL 实现，便于移植和仿真。 - -| | SDv1.1 card | SDv2 card | SDHCv2 card | -| :----- | :------------: | :------------: | :------------: | -| **读取扇区** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| **读取文件 (FAT16)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -| **读取文件 (FAT32)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | - - - -# 背景知识 - -## SD总线 - -SD卡使用 SD 总线与 SD-host （比如读卡器）连接，SD总线的信号包括： - -| 信号名 | 输入输出方向 | -| ------------------------------ | ------------------------------------------------ | -| sdclk | host→ card | -| sdcmd | 当发起命令时 host→ card ，当响应命令时 card→host | -| sddat0、sddat1、sddat2、sddat3 | 当写数据时 host→card ，当读数据时 card→host | - -这些信号在 SD 卡和 microSD 卡上的引脚定义如下图（SD卡和microSD卡除了外形尺寸外，功能上没有差别） - -| ![pin](./figures/pin.png) | -| :------------------------------------------: | -| 图：SD 卡（左）与 microSD 卡（右）的引脚定义 | - - - -## 文件系统 - -SD卡本身只是一大块线性的数据存储空间，分为多个扇区 (sector)，每个扇区 512 字节，扇区0的地址范围为 0x00000000\~0x000001FF，扇区1的地址范围为 0x00000200\~0x000003FF，以此类推……。底层的读取和写入操作都以扇区为单位。为了在这片线性的存储空间中组织磁盘分区和文件，人们规定了复杂的数据结构——文件系统，SD卡最常用的文件系统是 FAT16 和 FAT32 。 - -为了从 SD 卡中读取文件数据，本库分为两个功能模块： - -- 按照 SD 总线标准操控 SD 总线，指定扇区号，读取扇区。 -- 在能够读取扇区的基础上，解析文件系统，也就是给定文件名，找到文件所在的位置和长度。实际上，文件可能不是连续存储的（被拆成多块放在不同扇区），本库会正确地处理这种情况。 - - - - -# 如何调用本模块 - -RTL 文件夹中的 sd_file_reader.sv 是 SD卡文件读取器的顶层模块，它的定义如下： - -``` -module sd_file_reader #( - parameter FILE_NAME = "example.txt", - parameter [2:0] CLK_DIV = 3'd1, - parameter SIMULATE = 0 -)( - // rstn active-low, 1:working, 0:reset - input wire rstn, - // clock - input wire clk, - // SDcard signals (connect to SDcard), this design do not use sddat1~sddat3. - output wire sdclk, - inout sdcmd, - input wire sddat0, // FPGA only read SDDAT signal but never drive it - // status output (optional for user) - output wire [3:0] card_stat, // show the sdcard initialize status - output wire [1:0] card_type, // 0=UNKNOWN , 1=SDv1 , 2=SDv2 , 3=SDHCv2 - output wire [1:0] filesystem_type, // 0=UNASSIGNED , 1=UNKNOWN , 2=FAT16 , 3=FAT32 - output reg file_found, // 0=file not found, 1=file found - // file content data output (sync with clk) - output reg outen, // when outen=1, a byte of file content is read out from outbyte - output reg [7:0] outbyte // a byte of file content -); -``` - -其中： - -- `FILE_NAME` 指定要读的目标文件名。 -- `CLK_DIV` 是时钟分频系数，它的取值需要根据你提供的 clk 时钟频率来决定（详见代码注释）。 -- `SIMULATE` 是仿真加速选项。**平常要设为 `0` **。只有仿真时才可以设 为 `1` 来加速 SD 卡初始化进度，防止仿真占用过多时间。 -- `clk` 是模块驱动时钟。 -- `rstn` 是复位信号，在开始工作前需要令 `rstn=0` 复位一下，然后令 `rstn=1` 释放。 -- `sdclk` 、 `sdcmd` 、 `sddat0` 是 SD 总线信号，需要连接到 SD 卡。 - - 注意到本模块只用到了 `sddat0` 而没用到 `sddat1~sddat3` ，因为 SD 卡上电会默认运行在 1bit 窄数据总线模式，可以用命令切换到 4bit 宽数据总线模式，我没有做切换，一直只用 `sddat0` 。而 `sddat1~sddat3` 需要弱上拉或强上拉到高电平（避免 SD 卡进入 SPI 总线模式）。 -- `card_type` 指示检测到的 SD 卡的类型：0对应未知、1对应SDv1、2对应SDv2、3对应SDHCv2。 -- `file_system_type` 指示检测到的 SD 卡的文件系统：1对应未知、2对应FAT16、3对应FAT32。 -- `file_found` 指示是否找到目标文件：0代表未找到，1代表找到。 -- 如果找到目标文件，模块会逐个输出目标文件中的所有字节，每输出一个字节，`outen` 上就产生一个高电平脉冲，同时该字节出现在 `outbyte` 上。 - -> **注意**：本库只使用了 sddat0 ，而不使用 sddat1\~3 （也即SD 1-bit总线模式）。在工作时需要将 sddat1\~3 持续拉高（可以在 FPGA 代码里 `assign sddat[3:1] = 3'b111;` ，或者在PCB板上使用上拉电阻），这样 SD 卡才能正常进入 SD 总线模式，否则会进入 SPI 总线模式。 - - - -# 仿真 - -仿真相关的文件都在 SIM 文件夹中，其中： - -- sd_fake.sv ：是一个 FPGA 模拟 SD 卡的代码，它模拟了一个具有 FAT32 系统，里面有一个 example.txt 文件的 SD 卡。它来自我的另一个库：[FPGA-SDfake](https://github.com/WangXuan95/FPGA-SDfake) -- tb_sd_file_reader.sv 是仿真顶层，它会调用 sd_file_reader 读取 sd_fake 中的 example.txt 。 -- tb_sd_file_reader_run_iverilog.bat 是运行 iverilog 仿真的脚本。 - -使用 iverilog 进行仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) - -然后双击 tb_sd_file_reader_run_iverilog.bat 运行仿真，会运行大约几分钟。 - -仿真运行完后，可以打开生成的 dump.vcd 文件查看波形。 - - - -读取文件示例 -=========================== - -example-vivado-readfile 文件夹中包含一个 vivado 工程，它运行在 [Nexys4开发板](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga-trainer-board.html) 上（Nexys4 开发板有 microSD 卡槽，比较方便）。它会从 SD卡根目录中找到文件 example.txt 并读取其全部内容，然后用 **UART** 发送出给PC机。 - -按以下步骤运行该示例： - -1. 准备一张 **microSD卡** 。如果是标准尺寸的SD卡（大SD卡），可以用大卡转 microSD 卡的转接板转接一下。 -1. 确保卡中的文件系统是 **FAT16** 或 **FAT32** 。如果不是，则需要格式化一下。 -2. 在根目录下创建 **example.txt** (文件名大小写不限) ， 在文件中随便写入一些内容。 -3. 将卡插入 Nexys4 的卡槽。 -4. 将 Nexys4 的USB口插在PC机上，用 **串口助手** 或 **Putty** 等软件打开对应的串口。 -5. 用 vivado 打开目录 example-vivado-readfile 中的工程，综合并烧录。 -6. 观察到串口打印出文件内容。 -7. 同时，还能看到 Nexys4 上的 LED 灯发生变化，它们指示了SD卡的类型和状态，具体含义见代码。 -8. 按下 Nexys4 上的红色 CPU_RESET 按钮可以重新读取，再次打印出文件内容。 - - - -读取扇区示例 -=========================== - -example-vivado-readsector 文件夹中包含一个 vivado 工程，它运行在 [Nexys4开发板](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga-trainer-board.html) 上。它会从 SD卡中读取扇区0（它在文件系统中往往叫 MBR 扇区），然后用 **UART** 发送出给PC机。 - -按以下步骤运行该示例： - -1. 准备一张 **microSD卡** 。如果是标准尺寸的SD卡（大SD卡），可以用大卡转 microSD 卡的转接板转接一下。 -2. 将 Nexys4 的USB口插在PC机上，用 **串口助手** 打开对应的串口，请选择 “HEX接收” ，以十六进制的形式打印每个字节，这样我们才能看到那些 ASCII 不可打印字符。 -3. 用 vivado 打开目录 example-vivado-readsector 中的工程，综合并烧录。 -4. 观察到串口打印出扇区0的内容。 -5. 同时，还能看到 Nexys4 上的 LED 灯发生变化，它们指示了SD卡的类型和状态，具体含义见代码注释。 -6. 按下 Nexys4 上的红色 CPU_RESET 按钮可以重新读取，再次打印出扇区内容。 +![语言](https://img.shields.io/badge/语言-verilog_(IEEE1364_2001)-9A90FD.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg) +[English](#en) | [中文](#cn) +　 FPGA SDcard File Reader =========================== @@ -158,7 +12,7 @@ FPGA-based SDcard file reader * **Function**: FPGA acts as **SD-host**, specifying the file name to read the file content; or specifying the sector number to read the sector content. * **Performance**: Use SD bus instead of SPI bus. Read faster. * **Strong compatibility**: automatically adapt to **SDcard version**, automatically adapt to **FAT16/FAT32 file system**. -* pure RTL implement, easy to simulate and transplant. +* pure Verilog implement, easy to simulate and transplant. | | SDv1.1 card | SDv2 card | SDHCv2 card | | :-------------------- | :----------------: | :----------------: | :----------------: | @@ -166,7 +20,7 @@ FPGA-based SDcard file reader | **Read File (FAT16)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | **Read File (FAT32)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | - +　 # Background @@ -182,7 +36,7 @@ The SDcard is connected to the SD-host (such as a card adaptor) using the SD bus The pin definitions of these signals on SDcard and microSDcard are as follows (SDcard and microSDcard have no difference in function except for the shape and appearance). -| ![pin](./figures/pin.png) | +| ![pin](./pin.png) | | :----------------------------------------------------------: | | Figure : pin defination of SDcard (left) and microSDcard (right) | @@ -195,19 +49,26 @@ In order to read file data from SDcard, this library is divided into two functio - Manipulate the SD bus according to the SD bus standard, specify the sector number and read the sector. - On the basis of being able to read sectors, parse the file system, that is, given the file name, to find the location and length of the file. In fact, the file may not be stored contiguously (that is, split into multiple blocks in different sectors), my code will handle this case correctly. - +　 # How to use this module -sd_file_reader.sv in the [RTL](./RTL) folder is the top-level module of the SD card file reader, and it is defined as follows: +sd_file_reader.v in the [RTL](./RTL) folder is the top-level module of the SD card file reader, and it is defined as follows: -``` +```verilog module sd_file_reader #( - parameter FILE_NAME = "example.txt", - parameter [2:0] CLK_DIV = 3'd1, + parameter FILE_NAME_LEN = 11 , // valid length of FILE_NAME (in bytes) + parameter [52*8-1:0] FILE_NAME = "example.txt", // file to read, ignore Upper and Lower Case + // For example, if you want to read a file named HeLLo123.txt in the SD card, + // this parameter can be hello123.TXT, HELLO123.txt or HEllo123.Txt + parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1, + // when clk = 25~ 50MHz , set CLK_DIV = 3'd2, + // when clk = 50~100MHz , set CLK_DIV = 3'd3, + // when clk = 100~200MHz , set CLK_DIV = 3'd4, + // ...... parameter SIMULATE = 0 -)( +) ( // rstn active-low, 1:working, 0:reset input wire rstn, // clock @@ -230,6 +91,7 @@ module sd_file_reader #( where: - `FILE_NAME` specifies the name of the target file to read. +- `FILE_NAME_LEN` specifies the file name's length (in bytes). E.g., length of "example.txt" is 11. - `CLK_DIV` is the clock frequency division factor, its value needs to be determined according to the `clk` frequency you provide (see code comments for details). - `SIMULATE` is the simulation speed-up option. **Usually set to `0`**. It can be set to `1` only during simulation to speed up the SD card initialization progress and prevent the simulation from taking too much time. - `clk` is the module driving clock. @@ -241,16 +103,16 @@ where: - `file_found` will output whether the target file was found: 0 means not found, 1 means found. - If the target file is found, the module will output all the bytes in the file. For each output byte, a high-level pulse will be generated on `outen`, and the byte will appear on `outbyte`. -> **Note**: This repo only uses sddat0 (i.e. SD 1-bit bus mode) instead of sddat1\~3. When working, you need to continuously pull sddat1\~3 high (you can write `assign sddat[3:1] = 3'b111;` in the FPGA code, or use pull-up resistors on the PCB). This is to ensure that the SD card can enter SD bus mode normally, otherwise it will enter SPI bus mode. - +> :warning: This repo only uses sddat0 (i.e. SD 1-bit bus mode) instead of sddat1\~3. When working, you need to continuously pull sddat1\~3 high (you can write `assign sddat[3:1] = 3'b111;` in the FPGA code, or use pull-up resistors on the PCB). This is to ensure that the SD card can enter SD bus mode normally, otherwise it will enter SPI bus mode. +　 # RTL Simulation Simulation related files are in the [SIM](./SIM) folder, where: -- sd_fake.sv is a code for FPGA to imitate an SDcard. In this simulation program, it imitates an SDcard with FAT32 system and has an file example.txt inside. It comes from another repository of mine: [FPGA-SDfake](https://github.com/WangXuan95/FPGA-SDfake) -- tb_sd_file_reader.sv is the top level of the simulation, it will call sd_file_reader.sv to read the file in sd_fake.sv . +- sd_fake.v is the code for FPGA to imitate an SDcard. It comes from another repo of mine: [FPGA-SDfake](https://github.com/WangXuan95/FPGA-SDfake) . In this simulation, it imitates an SDcard with FAT32 system with a file "example.txt" inside. And it will be readed by the design under test (sd_file_reader.v). +- tb_sd_file_reader.v is the top level of the simulation, it will call sd_file_reader.v to read the file in sd_fake.v . - tb_sd_file_reader_run_iverilog.bat is a command script to run iverilog simulations. Before simulate using iverilog, you need to install iverilog , see: [iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) @@ -259,12 +121,12 @@ Then double-click tb_sd_file_reader_run_iverilog.bat to run simulation, which wi After the simulation runs, you can open the generated dump.vcd file to view the waveform. - +　 FPGA Demo: Read File =========================== -The [example-vivado-readfile](./example-vivado-readfile) folder contains a vivado project, which runs on the [Nexys4 development board](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga- trainer-board.html) (it has a microSDcard slot,). It will find the file example.txt from the root directory of the SDcard and read its entire content, and then send it to PC via **UART**. +example-vivado-readfile.zip contains a vivado project, which runs on the [Nexys4 development board](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga- trainer-board.html) (it has a microSDcard slot). It will search the file example.txt from the root directory of the SDcard and read its entire content, and then send it to PC via **UART**. Run the demo as follows: @@ -272,24 +134,189 @@ Run the demo as follows: 2. Create **example.txt** in the root directory (the file name is not limited in case), and write some content in the file. 3. Insert the SDcard into the card slot of Nexys4. 4. Plug the USB port of Nexys4 into PC, and open the corresponding serial port with software such as **Serial Assistant**, **Putty**, **HyperTerminal** or **minicom**. -5. Open the project in the directory [example-vivado-readfile](./example-vivado-readfile) with vivado, synthesize and program it. +5. Unzip example-vivado-readfile.zip . Then open the project in it with vivado, synthesize and program it. 6. Observe that the serial port prints the contents of the file. 7. Simutinously, you can see that the LEDs on the Nexys4 change, they indicate the type and status of the SDcard, see the code for the specific meaning. 8. Press the red CPU\_RESET button on Nexys4 to re-read and print out the file content again. - +　 FPGA Demo: Read Sector =========================== -The [example-vivado-readsector](./example-vivado-readsector) folder contains a vivado project, which runs on the [Nexys4 development board](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga- trainer-board.html), it will read sector 0 from the SD card (it is often called the MBR sector in file systems) and send it to PC via **UART**. +example-vivado-readsector.zip contains a vivado project, which runs on the [Nexys4 development board](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga- trainer-board.html), it will read sector 0 from the SD card (it is often called the MBR sector in file systems) and send it to PC via **UART**. Run the demo as follows: 1. Prepare a **microSDcard**. Plug it into the card slot of Nexys4. 2. Plug the USB port of Nexys4 into PC, use **Serial Assistant** to open the corresponding serial port, please select "HEX Receive Mode", print each byte in hexadecimal form, so that we can see those ASCII non-printable characters. -3. Use vivado to open the project in the directory [example-vivado-readsector](./example-vivado-readsector) , synthesize and program it. +3. Unzip example-vivado-readsector.zip . Then use vivado to open the project in it, synthesize and program it. 4. Observe that the serial port prints the contents of sector 0. 5. At the same time, you can also see that the LEDs on the Nexys4 change, they indicate the type and status of the SDcard, see the code comments for the specific meaning. 6. Press the red CPU\_RESET button on Nexys4 to re-read and print out the sector content again. +　 + +　 + +　 + +　 + +　 + + +FPGA SDcard File Reader +=========================== + +基于 FPGA 的 SD卡文件读取器 + +* **功能** ：FPGA作为 **SD-host** ， 指定文件名读取文件内容；或指定扇区号读取扇区内容。 +* **性能** ：使用 SD总线，而不是 SPI总线。读取速度更快。 +* **兼容性强** ：自动适配 **SD卡版本** ，自动适配 **FAT16/FAT32文件系统**。 +* 纯 Verilog 实现，便于移植和仿真。 + +| | SDv1.1 card | SDv2 card | SDHCv2 card | +| :----- | :------------: | :------------: | :------------: | +| **读取扇区** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| **读取文件 (FAT16)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| **读取文件 (FAT32)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | + +　 + +# 背景知识 + +## SD总线 + +SD卡使用 SD 总线与 SD-host （比如读卡器）连接，SD总线的信号包括： + +| 信号名 | 输入输出方向 | +| ------------------------------ | ------------------------------------------------ | +| sdclk | host→ card | +| sdcmd | 当发起命令时 host→ card ，当响应命令时 card→host | +| sddat0、sddat1、sddat2、sddat3 | 当写数据时 host→card ，当读数据时 card→host | + +这些信号在 SD 卡和 microSD 卡上的引脚定义如下图（SD卡和microSD卡除了外形尺寸外，功能上没有差别） + +| ![pin](./pin.png) | +| :------------------------------------------: | +| 图：SD 卡（左）与 microSD 卡（右）的引脚定义 | + +　 + +## 文件系统 + +SD卡本身只是一大块线性的数据存储空间，分为多个扇区 (sector)，每个扇区 512 字节，扇区0的地址范围为 0x00000000\~0x000001FF，扇区1的地址范围为 0x00000200\~0x000003FF，以此类推……。底层的读取和写入操作都以扇区为单位。为了在这片线性的存储空间中组织磁盘分区和文件，人们规定了复杂的数据结构——文件系统，SD卡最常用的文件系统是 FAT16 和 FAT32 。 + +为了从 SD 卡中读取文件数据，本库分为两个功能模块： + +- 按照 SD 总线标准操控 SD 总线，指定扇区号，读取扇区。 +- 在能够读取扇区的基础上，解析文件系统，也就是给定文件名，找到文件所在的位置和长度。实际上，文件可能不是连续存储的（被拆成多块放在不同扇区），本库会正确地处理这种情况。 + +　 + + +# 如何调用本模块 + +RTL 文件夹中的 sd_file_reader.v 是 SD卡文件读取器的顶层模块，它的定义如下： + +```verilog +module sd_file_reader #( + parameter FILE_NAME_LEN = 11 , // valid length of FILE_NAME (in bytes) + parameter [52*8-1:0] FILE_NAME = "example.txt", // file to read, ignore Upper and Lower Case + // For example, if you want to read a file named HeLLo123.txt in the SD card, + // this parameter can be hello123.TXT, HELLO123.txt or HEllo123.Txt + parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1, + // when clk = 25~ 50MHz , set CLK_DIV = 3'd2, + // when clk = 50~100MHz , set CLK_DIV = 3'd3, + // when clk = 100~200MHz , set CLK_DIV = 3'd4, + // ...... + parameter SIMULATE = 0 +) ( + // rstn active-low, 1:working, 0:reset + input wire rstn, + // clock + input wire clk, + // SDcard signals (connect to SDcard), this design do not use sddat1~sddat3. + output wire sdclk, + inout sdcmd, + input wire sddat0, // FPGA only read SDDAT signal but never drive it + // status output (optional for user) + output wire [3:0] card_stat, // show the sdcard initialize status + output wire [1:0] card_type, // 0=UNKNOWN , 1=SDv1 , 2=SDv2 , 3=SDHCv2 + output wire [1:0] filesystem_type, // 0=UNASSIGNED , 1=UNKNOWN , 2=FAT16 , 3=FAT32 + output reg file_found, // 0=file not found, 1=file found + // file content data output (sync with clk) + output reg outen, // when outen=1, a byte of file content is read out from outbyte + output reg [7:0] outbyte // a byte of file content +); +``` + +其中： + +- `FILE_NAME` 指定要读的目标文件名。 +- 需要在 `FILE_NAME_LEN` 指定文件名的长度 (字节数量) ，例如 "example.txt" 的长度为 11。 +- `CLK_DIV` 是时钟分频系数，它的取值需要根据你提供的 clk 时钟频率来决定（详见代码注释）。 +- `SIMULATE` 是仿真加速选项。**平常要设为 `0` **。只有仿真时才可以设 为 `1` 来加速 SD 卡初始化进度，防止仿真占用过多时间。 +- `clk` 是模块驱动时钟。 +- `rstn` 是复位信号，在开始工作前需要令 `rstn=0` 复位一下，然后令 `rstn=1` 释放。 +- `sdclk` 、 `sdcmd` 、 `sddat0` 是 SD 总线信号，需要连接到 SD 卡。 + - 注意到本模块只用到了 `sddat0` 而没用到 `sddat1~sddat3` ，因为 SD 卡上电会默认运行在 1bit 窄数据总线模式，可以用命令切换到 4bit 宽数据总线模式，我没有做切换，一直只用 `sddat0` 。而 `sddat1~sddat3` 需要弱上拉或强上拉到高电平（避免 SD 卡进入 SPI 总线模式）。 +- `card_type` 指示检测到的 SD 卡的类型：0对应未知、1对应SDv1、2对应SDv2、3对应SDHCv2。 +- `file_system_type` 指示检测到的 SD 卡的文件系统：1对应未知、2对应FAT16、3对应FAT32。 +- `file_found` 指示是否找到目标文件：0代表未找到，1代表找到。 +- 如果找到目标文件，模块会逐个输出目标文件中的所有字节，每输出一个字节，`outen` 上就产生一个高电平脉冲，同时该字节出现在 `outbyte` 上。 + +> :warning: 本库只使用了 sddat0 ，而不使用 sddat1\~3 （也即SD 1-bit总线模式）。在工作时需要将 sddat1\~3 持续拉高（可以在 FPGA 代码里 `assign sddat[3:1] = 3'b111;` ，或者在PCB板上使用上拉电阻），这样 SD 卡才能正常进入 SD 总线模式，否则会进入 SPI 总线模式。 + +　 + +# 仿真 + +仿真相关的文件都在 SIM 文件夹中，其中： + +- sd_fake.v ：是一个 FPGA 模拟 SD 卡的代码。它来自我的另一个库：[FPGA-SDfake](https://github.com/WangXuan95/FPGA-SDfake) 。在本仿真中，我们把它当作 SD 卡仿真模型，我们用它模拟了一个具有 FAT32 系统，里面有一个 example.txt 文件的 SD 卡。它会被我们的 SD 读取器 (sd_file_reader.v) 读取。 +- tb_sd_file_reader.v 是仿真顶层，它会调用 sd_file_reader 读取 sd_fake 中的 example.txt 。 +- tb_sd_file_reader_run_iverilog.bat 是运行 iverilog 仿真的脚本。 + +使用 iverilog 进行仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) + +然后双击 tb_sd_file_reader_run_iverilog.bat 运行仿真，会运行大约几分钟。 + +仿真运行完后，可以打开生成的 dump.vcd 文件查看波形。 + +　 + +读取文件示例 +=========================== + +example-vivado-readfile.zip 中包含一个 vivado 工程，它运行在 [Nexys4开发板](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga-trainer-board.html) 上（Nexys4 开发板有 microSD 卡槽，比较方便）。它会从 SD卡根目录中找到文件 example.txt 并读取其全部内容，然后用 **UART** 发送出给PC机。 + +按以下步骤运行该示例： + +1. 准备一张 **microSD卡** 。如果是标准尺寸的SD卡（大SD卡），可以用大卡转 microSD 卡的转接板转接一下。 +1. 确保卡中的文件系统是 **FAT16** 或 **FAT32** 。如果不是，则需要格式化一下。 +2. 在根目录下创建 **example.txt** (文件名大小写不限) ， 在文件中随便写入一些内容。 +3. 将卡插入 Nexys4 的卡槽。 +4. 将 Nexys4 的USB口插在PC机上，用 **串口助手** 或 **Putty** 等软件打开对应的串口。 +5. 解压 example-vivado-readfile.zip ，然后用 vivado 打开目录 example-vivado-readfile 中的工程，综合并烧录。 +6. 观察到串口打印出文件内容。 +7. 同时，还能看到 Nexys4 上的 LED 灯发生变化，它们指示了SD卡的类型和状态，具体含义见代码。 +8. 按下 Nexys4 上的红色 CPU_RESET 按钮可以重新读取，再次打印出文件内容。 + +　 + +读取扇区示例 +=========================== + +example-vivado-readsector.zip 中包含一个 vivado 工程，它运行在 [Nexys4开发板](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga-trainer-board.html) 上。它会从 SD卡中读取扇区0（它在文件系统中往往叫 MBR 扇区），然后用 **UART** 发送出给PC机。 + +按以下步骤运行该示例： + +1. 准备一张 **microSD卡** 。如果是标准尺寸的SD卡（大SD卡），可以用大卡转 microSD 卡的转接板转接一下。 +2. 将 Nexys4 的USB口插在PC机上，用 **串口助手** 打开对应的串口，请选择 “HEX接收” ，以十六进制的形式打印每个字节，这样我们才能看到那些 ASCII 不可打印字符。 +3. 解压 example-vivado-readsector.zip ，然后用 vivado 打开目录 example-vivado-readsector 中的工程，综合并烧录。 +4. 观察到串口打印出扇区0的内容。 +5. 同时，还能看到 Nexys4 上的 LED 灯发生变化，它们指示了SD卡的类型和状态，具体含义见代码注释。 +6. 按下 Nexys4 上的红色 CPU_RESET 按钮可以重新读取，再次打印出扇区内容。 + diff --git a/RTL/sd_file_reader.sv b/RTL/sd_file_reader.v similarity index 80% rename from RTL/sd_file_reader.sv rename to RTL/sd_file_reader.v index 6aa1fcf..5483ba0 100644 --- a/RTL/sd_file_reader.sv +++ b/RTL/sd_file_reader.v @@ -2,24 +2,25 @@ //-------------------------------------------------------------------------------------------------------- // Module : sd_file_reader // Type : synthesizable, IP's top -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// Function: A SD-host. +// Standard: Verilog 2001 (IEEE1364-2001) +// Function: A SD-card host to initialize SD-card and read files // Specify a filename, sd_file_reader will read out file content -// Compatibility: CardType : SDv1.1 , SDv2 or SDHCv2 -// FileSystem : FAT16 or FAT32 +// Support CardType : SDv1.1 , SDv2 or SDHCv2 +// Support FileSystem : FAT16 or FAT32 //-------------------------------------------------------------------------------------------------------- module sd_file_reader #( - parameter FILE_NAME = "example.txt", // file to read, ignore Upper and Lower Case - // For example, if you want to read a file named HeLLo123.txt in the SD card, - // this parameter can be hello123.TXT, HELLO123.txt or HEllo123.Txt - parameter [2:0] CLK_DIV = 3'd1, // when clk = 0~ 25MHz , set CLK_DIV = 3'd0, - // when clk = 25~ 50MHz , set CLK_DIV = 3'd1, - // when clk = 50~100MHz , set CLK_DIV = 3'd2, - // when clk = 100~200MHz , set CLK_DIV = 3'd3, + parameter FILE_NAME_LEN = 11 , // valid length of FILE_NAME (in bytes) + parameter [52*8-1:0] FILE_NAME = "example.txt", // file to read, ignore Upper and Lower Case + // For example, if you want to read a file named HeLLo123.txt in the SD card, + // this parameter can be hello123.TXT, HELLO123.txt or HEllo123.Txt + parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1, + // when clk = 25~ 50MHz , set CLK_DIV = 3'd2, + // when clk = 50~100MHz , set CLK_DIV = 3'd3, + // when clk = 100~200MHz , set CLK_DIV = 3'd4, // ...... parameter SIMULATE = 0 -)( +) ( // rstn active-low, 1:working, 0:reset input wire rstn, // clock @@ -38,20 +39,29 @@ module sd_file_reader #( output reg [7:0] outbyte // a byte of file content ); -initial file_found = 1'b0; -initial {outen,outbyte} = '0; -function automatic logic [7:0] toUpperCase(input [7:0] in); - return (in>=8'h61 && in<=8'h7A) ? in&8'b11011111 : in; + +function [7:0] toUpperCase; + input [7:0] in; +begin + toUpperCase = (in>=8'h61 && in<=8'h7A) ? (in & 8'b11011111) : in; +end endfunction -localparam TARGET_FNAME_LEN = ($bits(FILE_NAME)/8); -wire [$bits(FILE_NAME)-1:0] TARGET_FNAME = FILE_NAME; -reg [$bits(FILE_NAME)-1:0] TARGET_FNAME_UPPER; -always_comb - for(int ii=0; ii0) begin // FAT16 case + if(sectors_per_fat>0) begin // FAT16 case filesystem_parsed = FAT16; end else if(sector_content['h56]==8'h32) begin // FAT32 case filesystem_parsed = FAT32; @@ -165,7 +198,8 @@ always @ (posedge clk or negedge rstn) rootdir_sectorcount_t = rootdir_sectorcount; read_start <= 1'b0; - if(read_done) begin + + if (read_done) begin case(filesystem_state) SEARCH_MBR : if(is_boot_sector) begin filesystem_state <= SEARCH_DBR; @@ -210,7 +244,7 @@ always @ (posedge clk or negedge rstn) read_sector_no <= first_data_sector_no_t + cluster_size_t * curr_cluster_t + cluster_sector_offset_t; filesystem_state <= READ_A_FILE; end else if(cluster_sector_offset_t5'h0&&raddr[4:0]<5'hB || raddr[4:0]>=5'hE&&raddr[4:0]<5'h1A || raddr[4:0]>=5'h1C)begin if(raddr[4:0]<5'hB ? raddr[0] : ~raddr[0]) begin lastchar <= rdata; - fdtnamelen_t++; + fdtnamelen_t = fdtnamelen_t + 8'd1; end else begin //automatic logic [15:0] unicode = {rdata,lastchar}; if({rdata,lastchar} == 16'h0000) begin @@ -456,16 +501,16 @@ always @ (posedge clk or negedge rstn) begin if(raddr[4:0]<5'h8) begin if(rdata!=8'h20) begin file_name[sdtnamelen_t] <= rdata; - sdtnamelen_t++; + sdtnamelen_t = sdtnamelen_t + 8'd1; end end else if(raddr[4:0]<5'hB) begin if(raddr[4:0]==5'h8) begin file_name[sdtnamelen_t] <= 8'h2E; - sdtnamelen_t++; + sdtnamelen_t = sdtnamelen_t + 8'd1; end if(rdata!=8'h20) begin file_name[sdtnamelen_t] <= rdata; - sdtnamelen_t++; + sdtnamelen_t = sdtnamelen_t + 8'd1; end end else if(raddr[4:0]==5'hB) begin file_namelen <= sdtnamelen_t; @@ -494,12 +539,12 @@ always @ (posedge clk or negedge rstn) file_cluster <= 0; file_size <= 0; end else begin - if(fready && fnamelen==TARGET_FNAME_LEN) begin + if (fready && fnamelen==FILE_NAME_LEN) begin file_found <= 1'b1; file_cluster <= fcluster; file_size <= fsize; - for(int ii=0; ii=8 && cnt2<48) req_crc <= CalcCrc7(req_crc, request[cnt2]); end - end else if( clkcnt == {clkdivr[16:0],1'b1} && cnt1=='0 && cnt2=='1 ) begin - if(cnt3 != '0) begin + end else if( clkcnt == {clkdivr[16:0],1'b1} && cnt1==16'd0 && cnt2==6'h3F ) begin + if(cnt3 != 8'd0) begin cnt3 <= cnt3 - 8'd1; if(~sdcmdin) - cnt3 <= '0; + cnt3 <= 8'd0; else if(cnt3 == 8'd1) {done, timeout, syntaxe} <= 3'b110; - end else if(cnt4 != '1) begin + end else if(cnt4 != 8'hFF) begin cnt4 <= cnt4 - 8'd1; if(cnt4 >= 8'd96) - response <= {response[37:0], sdcmdin}; - if(cnt4 == '0) begin + {resp_st, resp_cmd, resp_arg} <= {resp_cmd, resp_arg, sdcmdin}; + if(cnt4 == 8'd0) begin {done, timeout} <= 2'b10; - syntaxe <= response.st || ((response.cmd!=req_cmd) && (response.cmd!='1) && (response.cmd!='0)); + syntaxe <= resp_st || ((resp_cmd!=req_cmd) && (resp_cmd!=6'h3F) && (resp_cmd!=6'd0)); end end end diff --git a/SIM/sd_fake.sv b/SIM/sd_fake.v similarity index 54% rename from SIM/sd_fake.sv rename to SIM/sd_fake.v index 96c2fe5..693da14 100644 --- a/SIM/sd_fake.sv +++ b/SIM/sd_fake.v @@ -2,7 +2,7 @@ //-------------------------------------------------------------------------------------------------------- // Module : sd_fake // Type : synthesizable, IP's top -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // Function: Imitate a SDHCv2 Read-Only SD card //-------------------------------------------------------------------------------------------------------- @@ -24,30 +24,33 @@ module sd_fake ( output reg [31:0] show_sdcmd_arg ); -initial rdreq = '0; -initial rdaddr = '0; -initial show_sdcmd_en = '0; -initial show_sdcmd_cmd = '0; -initial show_sdcmd_arg = '0; +initial rdreq = 1'b0; +initial rdaddr = 40'd0; + +initial show_sdcmd_en = 1'b0; +initial show_sdcmd_cmd = 6'h0; +initial show_sdcmd_arg = 0; // generate reset sync with posedge of sdclk -reg rstn_sdclk_p = '0; -reg [1:0] rstn_sdclk_p_l = '0; +reg rstn_sdclk_p = 1'b0; +reg [1:0] rstn_sdclk_p_l = 2'b0; + always @ (posedge sdclk or negedge rstn_async) if(~rstn_async) - {rstn_sdclk_p, rstn_sdclk_p_l} <= '0; + {rstn_sdclk_p, rstn_sdclk_p_l} <= 3'b0; else {rstn_sdclk_p, rstn_sdclk_p_l} <= {rstn_sdclk_p_l, 1'b1}; // generate reset sync with negedge of sdclk -reg rstn_sdclk_n = '0; -reg [1:0] rstn_sdclk_n_l = '0; +reg rstn_sdclk_n = 1'b0; +reg [1:0] rstn_sdclk_n_l = 2'b0; + always @ (negedge sdclk or negedge rstn_async) if(~rstn_async) - {rstn_sdclk_n, rstn_sdclk_n_l} <= '0; + {rstn_sdclk_n, rstn_sdclk_n_l} <= 3'b0; else {rstn_sdclk_n, rstn_sdclk_n_l} <= {rstn_sdclk_n_l, 1'b1}; @@ -56,19 +59,30 @@ always @ (negedge sdclk or negedge rstn_async) reg sdcmdoe = 1'b0; reg sdcmdout = 1'b1; reg sddatoe = 1'b0; -reg [3:0] sddatout = '1; +reg [3:0] sddatout = 4'hF; assign sdcmd = sdcmdoe ? sdcmdout : 1'bz; assign sddat = sddatoe ? sddatout : 4'bz; -function automatic logic [ 6:0] CalcCrcCMD(input [ 6:0] crc, input inbit); - return {crc[5:0],crc[6]^inbit} ^ {3'b0,crc[6]^inbit,3'b0}; + +function [6:0] CalcCrcCMD; + input [6:0] crc; + input [0:0] inbit; +begin + CalcCrcCMD = {crc[5:0],crc[6]^inbit} ^ {3'b0,crc[6]^inbit,3'b0}; +end endfunction -function automatic logic [15:0] CalcCrcDAT(input [15:0] crc, input inbit); - return {crc[14:0],crc[15]^inbit} ^ {3'b0,crc[15]^inbit,6'b0,crc[15]^inbit,5'b0}; + +function [15:0] CalcCrcDAT; + input [15:0] crc; + input [ 0:0] inbit; +begin + CalcCrcDAT = {crc[14:0],crc[15]^inbit} ^ {3'b0,crc[15]^inbit,6'b0,crc[15]^inbit,5'b0}; +end endfunction + localparam BLOCK_SIZE = 512; // 512B per block localparam [ 15:0] RCA_REG = 16'h0013; @@ -85,71 +99,101 @@ localparam [ 64:0] SCR_REG = 64'h0005_0000_00000000; // 64'h0231_0000_00000000; // Normal card, disable 4-bit bus mode // 64'h0235_0000_00000000; // Normal card, enable 4-bit bus mode -reg last_is_acmd=1'b0; +reg last_is_acmd = 1'b0; -enum logic [1:0] {WAITINGCMD, LOADRESP, RESPING} respstate = WAITINGCMD; -struct packed{ - logic [ 3:0] pre_st; - logic [ 5:0] cmd; - logic [31:0] arg; - logic [ 6:0] crc; - logic stop; -} request = '0; +localparam [1:0] WAITINGCMD = 2'd0, + LOADRESP = 2'd1, + RESPING = 2'd2; +reg [1:0] respstate = WAITINGCMD; -typedef enum logic [3:0] {IDLE, READY, IDENT, STBY, TRAN, DATA, RCV, PRG, DIS} current_state_t; -struct packed{ - logic out_of_range; - logic address_error; - logic block_len_error; - logic erase_seq_error; - logic erase_param; - logic wp_violation; - logic card_is_locked; - logic lock_unlock_failed; - logic com_crc_error; - logic illegal_command; - logic card_ecc_failed; - logic cc_error; - logic error; - logic [1:0] rsvd1; // reserved - logic csd_overwrite; - logic wp_erase_skip; - logic card_ecc_disabled; - logic erase_reset; - current_state_t current_state; - logic ready_for_data; - logic [1:0] rsvd2; - logic app_cmd; - logic rsvd3; - logic ake_seq_error; - logic [2:0] rsvd4; -} cardstatus = '0; +reg [49:0] request = 50'h3ffffffffffff; +wire [ 3:0] request_pre_st; +wire [ 5:0] request_cmd; +wire [31:0] request_arg; +wire [ 6:0] request_crc; +wire request_stop; +assign {request_pre_st, request_cmd, request_arg, request_crc, request_stop} = request; + + +localparam [3:0] IDLE = 4'd0, + READY = 4'd1, + IDENT = 4'd2, + STBY = 4'd3, + TRAN = 4'd4, + DATA = 4'd5, + RCV = 4'd6, + PRG = 4'd7, + DIS = 4'd8; +//typedef enum logic [3:0] {IDLE, READY, IDENT, STBY, TRAN, DATA, RCV, PRG, DIS} current_state_t; + + +//struct packed{ +reg cardstatus_out_of_range = 0; +reg cardstatus_address_error = 0; +reg cardstatus_block_len_error = 0; +reg cardstatus_erase_seq_error = 0; +reg cardstatus_erase_param = 0; +reg cardstatus_wp_violation = 0; +reg cardstatus_card_is_locked = 0; +reg cardstatus_lock_unlock_failed = 0; +reg cardstatus_com_crc_error = 0; +reg cardstatus_illegal_command = 0; +reg cardstatus_card_ecc_failed = 0; +reg cardstatus_cc_error = 0; +reg cardstatus_error = 0; +reg [1:0] cardstatus_rsvd1 = 0; // reserved +reg cardstatus_csd_overwrite = 0; +reg cardstatus_wp_erase_skip = 0; +reg cardstatus_card_ecc_disabled = 0; +reg cardstatus_erase_reset = 0; +reg [3:0] cardstatus_current_state = 0; +reg cardstatus_ready_for_data = 0; +reg [1:0] cardstatus_rsvd2 = 0; +reg cardstatus_app_cmd = 0; +reg cardstatus_rsvd3 = 0; +reg cardstatus_ake_seq_error = 0; +reg [2:0] cardstatus_rsvd4 = 0; + +wire [31:0] cardstatus = {cardstatus_out_of_range, cardstatus_address_error, cardstatus_block_len_error, cardstatus_erase_seq_error, cardstatus_erase_param, cardstatus_wp_violation, cardstatus_card_is_locked, cardstatus_lock_unlock_failed, cardstatus_com_crc_error, cardstatus_illegal_command, cardstatus_card_ecc_failed, cardstatus_cc_error, cardstatus_error, cardstatus_rsvd1, cardstatus_csd_overwrite, cardstatus_wp_erase_skip, cardstatus_card_ecc_disabled, cardstatus_erase_reset, cardstatus_current_state, cardstatus_ready_for_data, cardstatus_rsvd2, cardstatus_app_cmd, cardstatus_rsvd3, cardstatus_ake_seq_error, cardstatus_rsvd4}; wire [15:0] cardstatus_short = {cardstatus[23:22], cardstatus[19], cardstatus[12:0]}; // for R6 (CMD3) + localparam HIGHZLEN = 1; localparam WAITLEN = HIGHZLEN + 3; -reg [ 5:0] cmd='0; -reg [119:0] arg='0; -reg [ 6:0] crc='0; + +reg [ 5:0] cmd = 6'd0; +reg [119:0] arg = 120'd0; +reg [ 6:0] crc = 7'd0; reg response_end = 1'b0; -reg valid='0, dummycrc='0; -int idx=0, arglen=0; +reg valid=1'b0, dummycrc=1'b0; +reg [31:0] idx = 0; +reg [ 7:0] arglen = 0; -task automatic response_init(input _valid, input _dummycrc, input [5:0] _cmd, input int _arglen, input [119:0] _arg); + +task response_init; + input _valid; + input _dummycrc; + input [5:0] _cmd; + input [7:0] _arglen; + input [119:0] _arg; +begin cmd = _cmd; arg = _arg; - crc = '0; + crc = 0; valid = _valid; dummycrc = _dummycrc; idx = 0; arglen = _arglen; response_end = 1'b0; +end endtask -task automatic response_yield; + +task response_yield; +begin response_end = 1'b0; if ( ~valid) begin sdcmdoe = 0; @@ -184,18 +228,21 @@ task automatic response_yield; sdcmdout = 1; response_end = 1'b1; end - if(~response_end) idx++; + if(~response_end) idx = idx + 1; +end endtask + localparam DATAWAITLEN = HIGHZLEN + 16; localparam DATASTARTLEN = DATAWAITLEN + 1; + reg read_task=0, read_continue=0, read_scr=0, read_sdstat=0, read_cmd6stat=0; reg [31:0] read_idx = 0; wire [31:0] read_byte_idx = (read_idx-DATASTARTLEN); wire [ 3:0] readbyteidx = 4'hf - read_byte_idx[3:0]; wire [ 1:0] readquadidx = 2'h3 - read_byte_idx[1:0]; reg [15:0] read_crc = 0; -reg [15:0] read_crc_wide[4]; +reg [15:0] read_crc_wide [0:3]; wire [15:0] rddata_reversed = {rddata[7:0], rddata[15:8]}; reg widebus = 1'b0; // 0:1bit Mode 1:4bit Mode @@ -207,15 +254,23 @@ wire [511:0] SD_STAT = { widebus,1'b0, 1'b0, 13'h0, // bus-width, no security 4'h9, 428'h0 }; -reg [5:0] cmd6_invalid = 6'h0; +reg [ 5:0] cmd6_invalid = 6'h0; wire [511:0] CMD6_RESP = { 12'h0, (~(|cmd6_invalid)), 3'h0, // 8mA when not invalid 16'h8001, 16'h8001, 16'h8001, 16'h8001, 16'h8001, 16'h8001, {4{cmd6_invalid[5]}}, {4{cmd6_invalid[4]}}, {4{cmd6_invalid[3]}}, {4{cmd6_invalid[2]}}, {4{cmd6_invalid[1]}}, {4{cmd6_invalid[0]}}, 376'h0 }; -assign show_status_bits = { response_end, widebus, cardstatus.ready_for_data, cardstatus.app_cmd, cardstatus.current_state }; +assign show_status_bits = { response_end, widebus, cardstatus_ready_for_data, cardstatus_app_cmd, cardstatus_current_state }; -task automatic data_response_init(input [31:0] _read_sector_no=0, input _read_continue=1'b0); + + +integer i; + + +task data_response_init; + input [31:0] _read_sector_no; + input [ 0:0] _read_continue; +begin read_task = 1; read_continue = _read_continue; read_scr = 0; @@ -224,59 +279,74 @@ task automatic data_response_init(input [31:0] _read_sector_no=0, input _read_co rdaddr <= {_read_sector_no,8'h0}; read_idx = 0; read_crc = 0; - for(int i=0;i<4;i++) read_crc_wide[i] = '0; + for(i=0;i<4;i=i+1) read_crc_wide[i] = 0; +end endtask -task automatic data_response_sdstat_init; + +task data_response_sdstat_init; +begin read_task = 1; read_continue = 0; read_scr = 0; read_sdstat = 1; read_cmd6stat = 0; - rdaddr <= '0; + rdaddr <= 0; read_idx = 0; read_crc = 0; - for(int i=0;i<4;i++) read_crc_wide[i] = '0; + for(i=0;i<4;i=i+1) read_crc_wide[i] = 0; +end endtask -task automatic data_response_cmd6stat_init; + +task data_response_cmd6stat_init; +begin read_task = 1; read_continue = 0; read_scr = 0; read_sdstat = 0; read_cmd6stat = 1; - rdaddr <= '0; + rdaddr <= 0; read_idx = 0; read_crc = 0; - for(int i=0;i<4;i++) read_crc_wide[i] = '0; + for(i=0;i<4;i=i+1) read_crc_wide[i] = 0; +end endtask -task automatic data_response_scr_init; + +task data_response_scr_init; +begin read_task = 1; read_continue = 0; read_scr = 1; read_sdstat = 0; read_cmd6stat = 0; - rdaddr <= '0; + rdaddr <= 0; read_idx = 0; read_crc = 0; - for(int i=0;i<4;i++) read_crc_wide[i] = '0; + for(i=0;i<4;i=i+1) read_crc_wide[i] = 0; +end endtask -task automatic data_response_stop; + +task data_response_stop; +begin read_task = 0; read_continue = 0; read_scr = 0; read_sdstat = 0; read_cmd6stat = 0; - rdaddr <= '0; + rdaddr <= 0; read_idx = 0; read_crc = 0; - for(int i=0;i<4;i++) read_crc_wide[i] = '0; + for(i=0;i<4;i=i+1) read_crc_wide[i] = 0; +end endtask -task automatic data_response_yield; - rdreq <='0; + +task data_response_yield; +begin + rdreq <=0; sddatoe = 1'b1; if(~read_task) begin sddatoe = 1'b0; @@ -289,7 +359,7 @@ task automatic data_response_yield; end else if(read_idx 512) cardstatus.block_len_error = 1'b1; - response_init( 1, 0 , request.cmd , 32 , cardstatus ); - cardstatus.illegal_command = 1'b0; + 16 : if(cardstatus_current_state==TRAN) begin // SET_BLOCKLEN + if(request_arg > 512) cardstatus_block_len_error = 1'b1; + response_init( 1, 0 , request_cmd , 32 , cardstatus ); + cardstatus_illegal_command = 1'b0; end - 17 : if(cardstatus.current_state==TRAN) begin // READ_SINGLE_BLOCK - response_init( 1, 0 , request.cmd , 32 , cardstatus ); - data_response_init(request.arg); - cardstatus.illegal_command = 1'b0; + 17 : if(cardstatus_current_state==TRAN) begin // READ_SINGLE_BLOCK + response_init( 1, 0 , request_cmd , 32 , cardstatus ); + data_response_init(request_arg, 0); + cardstatus_illegal_command = 1'b0; end - 18 : if(cardstatus.current_state==TRAN) begin // READ_MULTIPLE_BLOCK - response_init( 1, 0 , request.cmd , 32 , cardstatus ); - data_response_init(request.arg, 1); - cardstatus.illegal_command = 1'b0; + 18 : if(cardstatus_current_state==TRAN) begin // READ_MULTIPLE_BLOCK + response_init( 1, 0 , request_cmd , 32 , cardstatus ); + data_response_init(request_arg, 1); + cardstatus_illegal_command = 1'b0; end - 55 : if(request.arg[31:16]=='0 || request.arg[31:16]==RCA_REG) begin // APP_CMD + 55 : if(request_arg[31:16]==16'd0 || request_arg[31:16]==RCA_REG) begin // APP_CMD last_is_acmd <= 1'b1; - cardstatus.app_cmd = 1'b1; - response_init( 1, 0 , request.cmd , 32 , cardstatus ); - cardstatus.illegal_command = 1'b0; + cardstatus_app_cmd = 1'b1; + response_init( 1, 0 , request_cmd , 32 , cardstatus ); + cardstatus_illegal_command = 1'b0; end 41 : if(last_is_acmd) begin // SD_SEND_OP_COND - cardstatus.app_cmd = 1'b1; + cardstatus_app_cmd = 1'b1; response_init( 1, 1 , 6'b111111 , 32 , OCR_REG ); - cardstatus.illegal_command = 1'b0; + cardstatus_illegal_command = 1'b0; end 42 : if(last_is_acmd) begin // SET_CLR_CARD_DETECT - cardstatus.app_cmd = 1'b1; - response_init( 1, 0 , request.cmd , 32 , cardstatus ); - cardstatus.illegal_command = 1'b0; + cardstatus_app_cmd = 1'b1; + response_init( 1, 0 , request_cmd , 32 , cardstatus ); + cardstatus_illegal_command = 1'b0; end - 51 : if(last_is_acmd && cardstatus.current_state==TRAN) begin // SEND_SCR - cardstatus.app_cmd = 1'b1; - response_init( 1, 0 , request.cmd , 32 , cardstatus ); + 51 : if(last_is_acmd && cardstatus_current_state==TRAN) begin // SEND_SCR + cardstatus_app_cmd = 1'b1; + response_init( 1, 0 , request_cmd , 32 , cardstatus ); data_response_scr_init; - cardstatus.illegal_command = 1'b0; + cardstatus_illegal_command = 1'b0; end default : begin // undefined CMD response_init( 0, 0 , 0 , 0 , 0 ); - cardstatus.illegal_command = 1'b1; + cardstatus_illegal_command = 1'b1; end endcase end @@ -566,14 +644,14 @@ always @ (negedge sdclk or negedge rstn_sdclk_n) always @ (posedge sdclk or negedge rstn_sdclk_p) if(~rstn_sdclk_p) begin show_sdcmd_en <= 1'b0; - show_sdcmd_cmd <= '0; - show_sdcmd_arg <= '0; + show_sdcmd_cmd <= 0; + show_sdcmd_arg <= 0; end else begin show_sdcmd_en <= 1'b0; - if(respstate == LOADRESP) begin + if (respstate == LOADRESP) begin show_sdcmd_en <= 1'b1; - show_sdcmd_cmd <= request.cmd; - show_sdcmd_arg <= request.arg; + show_sdcmd_cmd <= request_cmd; + show_sdcmd_arg <= request_arg; end end diff --git a/SIM/tb_sd_file_reader.sv b/SIM/tb_sd_file_reader.v similarity index 97% rename from SIM/tb_sd_file_reader.sv rename to SIM/tb_sd_file_reader.v index 400b982..5f478ed 100644 --- a/SIM/tb_sd_file_reader.sv +++ b/SIM/tb_sd_file_reader.v @@ -2,7 +2,7 @@ //-------------------------------------------------------------------------------------------------------- // Module : tb_sd_file_reader // Type : simulation, top -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // Function: testbench for sd_file_reader // connect sd_file_reader (SD-host) to sd_fake (SD-card) // sd_file_reader will read sd_fake's content @@ -45,7 +45,7 @@ always @ (posedge clk) if(outen) $display("readout byte: %c", outbyte); //-------------------------------------------------------------------------------------------------------- sd_file_reader #( .FILE_NAME ( "example.txt" ), - .CLK_DIV ( 0 ), + .CLK_DIV ( 1 ), .SIMULATE ( 1 ) ) sd_file_reader_i ( .rstn ( rstn ), @@ -102,8 +102,8 @@ sd_fake sd_fake_i ( // A ROM, contains a complete FAT32 partition data mirror //-------------------------------------------------------------------------------------------------------- always @ (posedge sdclk) - if(rom_req) - case(rom_addr) + if (rom_req) + case (rom_addr) 40'h00000000df: rom_data <= 16'h8200; 40'h00000000e0: rom_data <= 16'h0003; 40'h00000000e1: rom_data <= 16'hd50b; diff --git a/SIM/tb_sd_file_reader_run_iverilog.bat b/SIM/tb_sd_file_reader_run_iverilog.bat index 24643c9..365d5b9 100644 --- a/SIM/tb_sd_file_reader_run_iverilog.bat +++ b/SIM/tb_sd_file_reader_run_iverilog.bat @@ -1,5 +1,5 @@ del sim.out dump.vcd -iverilog -g2005-sv -o sim.out tb_sd_file_reader.sv sd_fake.sv ../RTL/sd_file_reader.sv ../RTL/sd_reader.sv ../RTL/sdcmd_ctrl.sv +iverilog -g2001 -o sim.out tb_sd_file_reader.v sd_fake.v ../RTL/sd_file_reader.v ../RTL/sd_reader.v ../RTL/sdcmd_ctrl.v vvp -n sim.out del sim.out pause \ No newline at end of file diff --git a/example-vivado-readfile.zip b/example-vivado-readfile.zip new file mode 100644 index 0000000000000000000000000000000000000000..fa3e0348e47c43956071d7b77e75b806d3e7502d GIT binary patch literal 85564 zcmbTdQ;;sO->unpzioTBZQHi7+qP}nwr$(iZrira`G04o&YAD#)Xd36l8dZWxk&w1 zQuRbZ8Wao_=)c-}!MNK0nEXE-=6^;LcLN)HYZF>m3s(bUJ6cB*17lMQYZH2f|EYR# z`tK^7|BXsg;r}HBcK+`|(*M2C$l6NJ&B9ZU;eS~0|7S4(=)Ww~827zWh=G7O$bf*D z{=ZuMPcu4WBYQ*;aG<|HKoCGc6v*BB6lu$UxwDrMC=WSw(54bRPwL-mIO0Bn+&^oA zfD|IKBVS9qlXC0!CfUgf_oP5_uKP<10LUAOm2B#lmPNqBXAKv>Q)20e=dhyD5Uud;4Y$7d;HwdQqE26q6v-4gT6XoA^_vEJ6#N)NIeF&pf<{h1c-2Gl|??dCazr5-+& zf!vpdUhBC=M0fs+AuNv=9Y9AM8b58G=`Hxg{b28-RP#u0&dODL$}dp%d|q^$?y}u- z&Kvn_L)wX?m^7DQ%H0TKM!}lNx5$k);#i2;?yqTU2+CI6h|TyEqurI)6%t?Ye%GYY z1(Ng#K#?L|v5~6RoknxW?}v;cueUDwH?7`*XiaT#|V-_F{TpFP-!ZZJ|@k{P(IHFI(ESnZ|O=FRI$Tg z%l46)TO+fG(4M8Y%w!k(isur-zg*1F6JhavEMt^l9%(OCFYT-Azz%%<@`09G?5l*TdLqWlSky5B_(#M*UfsI zj6#{@S5SZl9$9&Wp@Uz%gC&t`%k}YU;+JEs4;WT64fS!fI#G|x25M*?-cMhh{{5ya z_2A;%TFcyqs#NT6JVyfOnqjYbLTi(uX+ymkXS~#zzO?}GG9zfUFfV=@;H}6Vb=kt& zP{InSL&HtQZpXAD!%Vd*aCatq?t);%*H~}Ry%vBp-6;nw+cn!qIv|v_hcR?-1C=mD zK|g80%9Uz|m_)>Ggh{y5176rzgi9c{KEBn{84L;ivpuH-O|@mACYPf=)h(If!@*j> zQd4>Hynul*sVUoA-eZje{FP5f#~OV!iJ9J>nWbuUUj>N zHK;jV^E{;9iafKr9EWFgKX&5c-^ucND5RDYvy_G#G$05jAhT3U*+FmiaDl7iR;5TQ9S zBlUP!{^E;nRvpX4wB99Y*UF$@g`c%iVE4z#lIeICvt0_;i|W3syBSD$IduG%9b_&8DlO}9-#xs`Gh+70 z!1e-l+9WqVBM7m|#X;d>0tg{&Rl|Y z&j?lzZ>MS_$_I#sE-jf4smFLcR}cKs)k~~Dn&F1oLoNN18mvv`5&C}>iKmhkG(T7w z4$$TA8;4=y$`*CoUbO@}p$M6@-=1xxLB>>hOd?+Eo&RX0Dk&BbHZtyS#G3acl2$C( z!mbYz>{_uSOIx`q$~hfA1x>wsX5`TJXfpH2E|wJeQB9PIbO$f%!se;}W!z7?MmuKKJVdswiC(3S)zGBA@Vd>;M;S*-VN0vs^Y~Sx> z((qX<+dLY^3s2q&U)(>|s3Xotlk0o=L0mO^I^w%ZZHd4j^8^6`Ov)xa*p-$eQejcf zd6#R}bUmHIy4sI#DWL0#KJ#(G!Vn6t&-5*dmF0wJbvQ9V3`as6w2ucHJ=sCWqNmkX zv@!HaIvqK}J5y&CRBBtM;wxBeqlwE7#3<)W=$mZEV>H^6PXDxH3ELcvTMj`sRUBm* zu4OF>sa=2mUVk6pouR;wsip5%B@V|91t7HjY!ym(j zgx~QxZGy`BQp$&w$9IYbG9J$dq>?AzkB{0YT|jZ$N}1b|fHj#AIh$!=c+Qu zZM#{xbKT$tQ6gDIJZzRlH_Eyqo@P@UgP~H^@*?<_q_g4W(^qRkfdW(zh@5WlAFbiu z<-E)TS`|yv6aZ`z1G7Bys~*rxni6q~yPM;f5c&#>NV+Y!*~{#>vu$Qfcwk8ch~}Tl zRpO8q3f=KwY2_7&3hYoK^ySQacP##4$R z9;(3Em>eMOc7qGdOx%COYUw%@rhN-fAnaaUp<%OL8R_z4PZLH9FZEfA2jPg2Fj-;R zOv%}-SK%U}J(~iY!unH~b{y8#jkmrv%2Veo?|pyCEiV~j=^v^PP1x?m4>S*ipo9np z*73tEc>|8h9o4$i{fU{LAxzw(09{je19Qoz9;c~co7!P@QHd$ycpr{Mgjy3H@J_d) zjuqtHU|in~H5{7!`_&8>zV4S8a>(ynLo>Gwj*I-AkHdUjhE}VEomrcwqBZs-!~6I; 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-set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -## LEDs -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - - -# UART -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out - - -# SDcard -set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sdcard_pwr_n }]; #IO_L14P_T2_SRCC_35 Sch=sd_resetn -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sdclk }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sdclk -set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sdcmd }]; #IO_L16N_T2_35 Sch=sdcmd -set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sddat0 }]; #IO_L16P_T2_35 Sch=sd_dat[0] -set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sddat1 }]; #IO_L18N_T2_35 Sch=sd_dat[1] -set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sddat2 }]; #IO_L18P_T2_35 Sch=sd_dat[2] -set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sddat3 }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - diff --git a/example-vivado-readfile/Nexys4-ReadFile.xpr b/example-vivado-readfile/Nexys4-ReadFile.xpr deleted file mode 100644 index dbccc20..0000000 --- a/example-vivado-readfile/Nexys4-ReadFile.xpr +++ /dev/null @@ -1,234 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - default_dashboard - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/example-vivado-readfile/RTL/top.sv b/example-vivado-readfile/RTL/top.sv deleted file mode 100644 index 4ce66ac..0000000 --- a/example-vivado-readfile/RTL/top.sv +++ /dev/null @@ -1,84 +0,0 @@ - -//-------------------------------------------------------------------------------------------------------- -// Module : top -// Type : synthesizable, FPGA's top, IP's example design -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// Function: an example of sd_file_reader, read a file from SDcard and send file content to UART -// this example runs on Digilent Nexys4-DDR board (Xilinx Artix-7), -// see http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga-trainer-board.html -//-------------------------------------------------------------------------------------------------------- - -module top ( - // clock = 100MHz - input wire clk100mhz, - // rstn active-low, You can re-read SDcard by pushing the reset button. - input wire resetn, - // when sdcard_pwr_n = 0, SDcard power on - output wire sdcard_pwr_n, - // signals connect to SD bus - output wire sdclk, - inout sdcmd, - input wire sddat0, - output wire sddat1, sddat2, sddat3, - // 16 bit led to show the status of SDcard - output wire [15:0] led, - // UART tx signal, connected to host-PC's UART-RXD, baud=115200 - output wire uart_tx -); - -assign led[15:9] = '0; - -assign sdcard_pwr_n = 1'b0; - -assign {sddat1, sddat2, sddat3} = 3'b111; // Must set sddat1~3 to 1 to avoid SD card from entering SPI mode - - -wire outen; // when outen=1, a byte of file content is read out from outbyte -wire [7:0] outbyte; // a byte of file content - - -//---------------------------------------------------------------------------------------------------- -// sd_file_reader -//---------------------------------------------------------------------------------------------------- -sd_file_reader #( - .FILE_NAME ( "example.txt" ), // file name to read - .CLK_DIV ( 2 ), // because clk=100MHz, CLK_DIV is set to 2 - .SIMULATE ( 0 ) -) sd_file_reader_i ( - .rstn ( resetn ), - .clk ( clk100mhz ), - .sdclk ( sdclk ), - .sdcmd ( sdcmd ), - .sddat0 ( sddat0 ), - .card_stat ( led[3:0] ), // show the sdcard initialize status - .card_type ( led[5:4] ), // 0=UNKNOWN , 1=SDv1 , 2=SDv2 , 3=SDHCv2 - .filesystem_type ( led[7:6] ), // 0=UNASSIGNED , 1=UNKNOWN , 2=FAT16 , 3=FAT32 - .file_found ( led[ 8] ), // 0=file not found, 1=file found - .outen ( outen ), - .outbyte ( outbyte ) -); - - -//---------------------------------------------------------------------------------------------------- -// send file content to UART -//---------------------------------------------------------------------------------------------------- -uart_tx #( - .CLK_DIV ( 868 ), // 100MHz/868 = 115200 - .PARITY ( "NONE" ), // no parity bit - .ASIZE ( 14 ), // - .DWIDTH ( 1 ), // tx_data is 8 bit (1 Byte) - .ENDIAN ( "LITTLE" ), // - .MODE ( "RAW" ), // - .END_OF_DATA ( "" ), // - .END_OF_PACK ( "" ) // -) uart_tx_i ( - .rstn ( resetn ), - .clk ( clk100mhz ), - .tx_data ( outbyte ), - .tx_last ( 1'b0 ), - .tx_en ( outen ), - .tx_rdy ( ), - .o_uart_tx ( uart_tx ) -); - -endmodule diff --git a/example-vivado-readfile/RTL/uart_tx.sv b/example-vivado-readfile/RTL/uart_tx.sv deleted file mode 100644 index 62e62c6..0000000 --- a/example-vivado-readfile/RTL/uart_tx.sv +++ /dev/null @@ -1,188 +0,0 @@ - -//-------------------------------------------------------------------------------------------------------- -// Module : uart_tx -// Type : synthesizable, IP's top -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// Function: buffer input data and send them to UART -// UART format: 8 data bits -//-------------------------------------------------------------------------------------------------------- - -module uart_tx #( - parameter CLK_DIV = 434, // UART baud rate = clk freq/(2*UART_TX_CLK_DIV). for example, when clk=50MHz, UART_TX_CLK_DIV=434, then baud=50MHz/(2*434)=115200 - parameter PARITY = "NONE", // "NONE", "ODD" or "EVEN" - parameter ASIZE = 10, // UART TX buffer size = 2^ASIZE bytes, Set it smaller if your FPGA doesn't have enough BRAM - parameter DWIDTH = 1, // Specify width of tx_data , that is, how many bytes can it input per clock cycle - parameter ENDIAN = "LITTLE", // "LITTLE" or "BIG". when DWIDTH>=2, this parameter determines the byte order of tx_data - parameter MODE = "RAW", // "RAW", "PRINTABLE", "HEX" or "HEXSPACE" - parameter END_OF_DATA = "", // Specify a extra send byte after each tx_data. when ="", do not send this extra byte - parameter END_OF_PACK = "" // Specify a extra send byte after each tx_data with tx_last=1. when ="", do not send this extra byte -)( - input wire rstn, - input wire clk, - // user interface - input wire [DWIDTH*8-1:0] tx_data, - input wire tx_last, - input wire tx_en, - output wire tx_rdy, - // uart tx output signal - output reg o_uart_tx -); - -initial o_uart_tx = 1'b1; - - - -function automatic logic [7:0] hex2ascii (input [3:0] hex); - return {4'h3, hex} + ((hex<4'hA) ? 8'h0 : 8'h7) ; -endfunction - - -function automatic logic is_printable_ascii(input [7:0] ascii); - return (ascii>=8'h20 && ascii<8'h7F) || ascii==8'h0A || ascii==8'h0D; -endfunction - - -function automatic logic [11:0] build_send_byte(input [7:0] send_byte); - if ( PARITY == "ODD" ) - return {1'b1, (~(^send_byte)), send_byte, 2'b01}; - else if( PARITY == "EVEN" ) - return {1'b1, (^send_byte) , send_byte, 2'b01}; - else - return {1'b1, 1'b1 , send_byte, 2'b01}; -endfunction - - -function automatic logic [6+35:0] build_send_data(input [7:0] send_data); - logic [ 5:0] dcnt = '0; - logic [35:0] data = '1; - if( MODE != "PRINTABLE" || is_printable_ascii(send_data) ) begin - if( MODE == "HEXSPACE" ) begin - dcnt += 6'd12; - data[11:0] = build_send_byte(8'h20); - end - dcnt += 6'd12; - data <<= 12; - if( MODE == "HEX" || MODE == "HEXSPACE" ) begin - data[11:0] = build_send_byte(hex2ascii(send_data[3:0])); - dcnt += 6'd12; - data <<= 12; - data[11:0] = build_send_byte(hex2ascii(send_data[7:4])); - end else begin - data[11:0] = build_send_byte(send_data); - end - end - return {dcnt, data}; -endfunction - - -function automatic logic [6+35:0] build_send_eod(input send_last); - logic [ 5:0] dcnt = '0; - logic [35:0] data = '1; - if( END_OF_PACK != "" && send_last ) begin - dcnt += 6'd12; - data[11:0] = build_send_byte((8)'(END_OF_PACK)); - end - if( END_OF_DATA != "" ) begin - dcnt += 6'd12; - data <<= 12; - data[11:0] = build_send_byte((8)'(END_OF_DATA)); - end - return {dcnt, data}; -endfunction - - - - -reg [DWIDTH*8-1:0] tx_data_endian; - -always_comb - if(ENDIAN == "BIG") begin - for(int i=0; i '0 ) begin - if( cyc+1 == CLK_DIV ) begin - txdcnt <= txdcnt - 6'd1; - {txdata, o_uart_tx} <= {1'b1, txdata}; - end - end else if( bcnt > '0 ) begin - bcnt <= bcnt - 16'd1; - send_data <= send_data >> 8; - {txdcnt, txdata} <= build_send_data(send_data[7:0]); - end else if( eod ) begin - eod <= '0; - {txdcnt, txdata} <= build_send_eod(send_last); - end else if( fifo_empty_n ) begin - fifo_rptr <= fifo_rptr + (ASIZE+1)'(1); - fifo_rd_en <= 1'b1; - end - end - - -endmodule diff --git a/example-vivado-readsector.zip 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a/example-vivado-readsector/Nexys-4-DDR-pins.xdc b/example-vivado-readsector/Nexys-4-DDR-pins.xdc deleted file mode 100644 index 757eacf..0000000 --- a/example-vivado-readsector/Nexys-4-DDR-pins.xdc +++ /dev/null @@ -1,41 +0,0 @@ - -## Clock -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk100mhz}]; - - -set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -## LEDs -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - - -# UART -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out - - -# SDcard -set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sdcard_pwr_n }]; #IO_L14P_T2_SRCC_35 Sch=sd_resetn -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sdclk }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sdclk -set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sdcmd }]; #IO_L16N_T2_35 Sch=sdcmd -set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sddat0 }]; #IO_L16P_T2_35 Sch=sd_dat[0] -set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sddat1 }]; #IO_L18N_T2_35 Sch=sd_dat[1] -set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sddat2 }]; #IO_L18P_T2_35 Sch=sd_dat[2] -set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sddat3 }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - diff --git a/example-vivado-readsector/Nexys4-ReadSector.xpr b/example-vivado-readsector/Nexys4-ReadSector.xpr deleted file mode 100644 index 968a7d2..0000000 --- a/example-vivado-readsector/Nexys4-ReadSector.xpr +++ /dev/null @@ -1,228 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - default_dashboard - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/example-vivado-readsector/RTL/top.sv b/example-vivado-readsector/RTL/top.sv deleted file mode 100644 index dc365e8..0000000 --- a/example-vivado-readsector/RTL/top.sv +++ /dev/null @@ -1,96 +0,0 @@ - -//-------------------------------------------------------------------------------------------------------- -// Module : top -// Type : synthesizable, FPGA's top, IP's example design -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// Function: an example of sd_reader, read a sector (512B) from SDcard and send its content to UART -// this example runs on Digilent Nexys4-DDR board (Xilinx Artix-7), -// see http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga-trainer-board.html -//-------------------------------------------------------------------------------------------------------- - -module top ( - // clock = 100MHz - input wire clk100mhz, - // rstn active-low, You can re-read SDcard by pushing the reset button. - input wire resetn, - // when sdcard_pwr_n = 0, SDcard power on - output wire sdcard_pwr_n, - // signals connect to SD bus - output wire sdclk, - inout sdcmd, - input wire sddat0, - output wire sddat1, sddat2, sddat3, - // 16 bit led to show the status of SDcard - output wire [15:0] led, - // UART tx signal, connected to host-PC's UART-RXD, baud=115200 - output wire uart_tx -); - -assign led[15:6] = 10'h0; - -assign sdcard_pwr_n = 1'b0; - -assign {sddat1, sddat2, sddat3} = 3'b111; // Must set sddat1~3 to 1 to avoid SD card from entering SPI mode - - -wire rdone; -reg rstart = 1'b1; - -wire outen; -wire [7:0] outbyte; - -always @ (posedge clk100mhz or negedge resetn) - if(~resetn) begin - rstart <= 1'b1; - end else begin - if(rdone) rstart <= 1'b0; // read a sector only once, so set rstart=0 when rdone=1. - end - - -//---------------------------------------------------------------------------------------------------- -// sd_reader -//---------------------------------------------------------------------------------------------------- -sd_reader #( - .CLK_DIV ( 2 ), - .SIMULATE ( 0 ) -) sd_reader_i ( - .rstn ( resetn ), - .clk ( clk100mhz ), - .sdclk ( sdclk ), - .sdcmd ( sdcmd ), - .sddat0 ( sddat0 ), - .card_stat ( led[ 3: 0] ), // show the sdcard initialize status - .card_type ( led[ 5: 4] ), // 0=UNKNOWN , 1=SDv1 , 2=SDv2 , 3=SDHCv2 - .rstart ( rstart ), - .rsector ( 0 ), // read No. 0 sector (the first sector) in SDcard - .rbusy ( ), - .rdone ( rdone ), - .outen ( outen ), - .outaddr ( ), - .outbyte ( outbyte ) -); - - -//---------------------------------------------------------------------------------------------------- -// send file content to UART -//---------------------------------------------------------------------------------------------------- -uart_tx #( - .CLK_DIV ( 868 ), // 100MHz/868 = 115200 - .PARITY ( "NONE" ), // no parity bit - .ASIZE ( 14 ), // - .DWIDTH ( 1 ), // tx_data is 8 bit (1 Byte) - .ENDIAN ( "LITTLE" ), // - .MODE ( "RAW" ), // - .END_OF_DATA ( "" ), // - .END_OF_PACK ( "" ) // -) uart_tx_i ( - .rstn ( resetn ), - .clk ( clk100mhz ), - .tx_data ( outbyte ), - .tx_last ( 1'b0 ), - .tx_en ( outen ), - .tx_rdy ( ), - .o_uart_tx ( uart_tx ) -); - -endmodule diff --git a/example-vivado-readsector/RTL/uart_tx.sv b/example-vivado-readsector/RTL/uart_tx.sv deleted file mode 100644 index 62e62c6..0000000 --- a/example-vivado-readsector/RTL/uart_tx.sv +++ /dev/null @@ -1,188 +0,0 @@ - -//-------------------------------------------------------------------------------------------------------- -// Module : uart_tx -// Type : synthesizable, IP's top -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// Function: buffer input data and send them to UART -// UART format: 8 data bits -//-------------------------------------------------------------------------------------------------------- - -module uart_tx #( - parameter CLK_DIV = 434, // UART baud rate = clk freq/(2*UART_TX_CLK_DIV). for example, when clk=50MHz, UART_TX_CLK_DIV=434, then baud=50MHz/(2*434)=115200 - parameter PARITY = "NONE", // "NONE", "ODD" or "EVEN" - parameter ASIZE = 10, // UART TX buffer size = 2^ASIZE bytes, Set it smaller if your FPGA doesn't have enough BRAM - parameter DWIDTH = 1, // Specify width of tx_data , that is, how many bytes can it input per clock cycle - parameter ENDIAN = "LITTLE", // "LITTLE" or "BIG". when DWIDTH>=2, this parameter determines the byte order of tx_data - parameter MODE = "RAW", // "RAW", "PRINTABLE", "HEX" or "HEXSPACE" - parameter END_OF_DATA = "", // Specify a extra send byte after each tx_data. when ="", do not send this extra byte - parameter END_OF_PACK = "" // Specify a extra send byte after each tx_data with tx_last=1. when ="", do not send this extra byte -)( - input wire rstn, - input wire clk, - // user interface - input wire [DWIDTH*8-1:0] tx_data, - input wire tx_last, - input wire tx_en, - output wire tx_rdy, - // uart tx output signal - output reg o_uart_tx -); - -initial o_uart_tx = 1'b1; - - - -function automatic logic [7:0] hex2ascii (input [3:0] hex); - return {4'h3, hex} + ((hex<4'hA) ? 8'h0 : 8'h7) ; -endfunction - - -function automatic logic is_printable_ascii(input [7:0] ascii); - return (ascii>=8'h20 && ascii<8'h7F) || ascii==8'h0A || ascii==8'h0D; -endfunction - - -function automatic logic [11:0] build_send_byte(input [7:0] send_byte); - if ( PARITY == "ODD" ) - return {1'b1, (~(^send_byte)), send_byte, 2'b01}; - else if( PARITY == "EVEN" ) - return {1'b1, (^send_byte) , send_byte, 2'b01}; - else - return {1'b1, 1'b1 , send_byte, 2'b01}; -endfunction - - -function automatic logic [6+35:0] build_send_data(input [7:0] send_data); - logic [ 5:0] dcnt = '0; - logic [35:0] data = '1; - if( MODE != "PRINTABLE" || is_printable_ascii(send_data) ) begin - if( MODE == "HEXSPACE" ) begin - dcnt += 6'd12; - data[11:0] = build_send_byte(8'h20); - end - dcnt += 6'd12; - data <<= 12; - if( MODE == "HEX" || MODE == "HEXSPACE" ) begin - data[11:0] = build_send_byte(hex2ascii(send_data[3:0])); - dcnt += 6'd12; - data <<= 12; - data[11:0] = build_send_byte(hex2ascii(send_data[7:4])); - end else begin - data[11:0] = build_send_byte(send_data); - end - end - return {dcnt, data}; -endfunction - - -function automatic logic [6+35:0] build_send_eod(input send_last); - logic [ 5:0] dcnt = '0; - logic [35:0] data = '1; - if( END_OF_PACK != "" && send_last ) begin - dcnt += 6'd12; - data[11:0] = build_send_byte((8)'(END_OF_PACK)); - end - if( END_OF_DATA != "" ) begin - dcnt += 6'd12; - data <<= 12; - data[11:0] = build_send_byte((8)'(END_OF_DATA)); - end - return {dcnt, data}; -endfunction - - - - -reg [DWIDTH*8-1:0] tx_data_endian; - -always_comb - if(ENDIAN == "BIG") begin - for(int i=0; i '0 ) begin - if( cyc+1 == CLK_DIV ) begin - txdcnt <= txdcnt - 6'd1; - {txdata, o_uart_tx} <= {1'b1, txdata}; - end - end else if( bcnt > '0 ) begin - bcnt <= bcnt - 16'd1; - send_data <= send_data >> 8; - {txdcnt, txdata} <= build_send_data(send_data[7:0]); - end else if( eod ) begin - eod <= '0; - {txdcnt, txdata} <= build_send_eod(send_last); - end else if( fifo_empty_n ) begin - fifo_rptr <= fifo_rptr + (ASIZE+1)'(1); - fifo_rd_en <= 1'b1; - end - end - - -endmodule diff --git a/figures/pin.png b/figures/pin.png deleted file mode 100644 index f840aa3d3ecbe375ca64c97e2f310daca40a6f04..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 23691 zcmV)oK%BpcP)|Npq5p`rQp zhSSs2|MrbkR!`g8+xz*9c6N4KR7n5!fcWf^|J#uN|C~cZLjUoN`}2f) z|F&lT_m=QI*|PIe_ByE^69bo?}?O@l#Gmv|NMqkSUvyn zlqo4F|NgQ6`kVXlmGM?56nkq#F_d z_3@VW^Nr`;e)jjWwq`o=?2qyChEq{k|NMSt06H}^H1g|$FfT9m_J02MckSkQJ2wOQ z`Tt;8K>z;7VP8#5P)0cb0Q2p1^zWbN+GpjQEO&8IxZ#xW&i;7^}c4d|21Zi;@xSOkU)?+I_KlF+mL4a{PXSNklVJ9w6U4X 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