FPGA/FPGA-SDcard-Reader
1
0
Fork 0
mirror of https://github.com/WangXuan95/FPGA-SDcard-Reader.git synced 2025-01-13 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity

update comment

Browse Source
This commit is contained in:
WangXuan95 2023-07-26 19:07:59 +08:00
parent 24ce90a1ea
commit 91f20a1b17
1 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
RTL/sd_file_reader.v
View File

@ -10,10 +10,9 @@
//-------------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------------
module sd_file_reader #( module sd_file_reader #(
parameter FILE_NAME_LEN = 11 , // valid length of FILE_NAME (in bytes) parameter FILE_NAME_LEN = 11 , // length of FILE_NAME (in bytes). Since the length of "example.txt" is 11, so here is 11.
parameter [52*8-1:0] FILE_NAME = "example.txt", // file to read, ignore Upper and Lower Case parameter [52*8-1:0] FILE_NAME = "example.txt", // file name to read, ignore Upper and Lower Case
// For example, if you want to read a file named HeLLo123.txt in the SD card, // For example, if you want to read a file named "HeLLo123.txt", this parameter can be "hello123.TXT", "HELLO123.txt" or "HEllo123.Txt"
// this parameter can be hello123.TXT, HELLO123.txt or HEllo123.Txt
parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1, parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1,
// when clk = 25~ 50MHz , set CLK_DIV = 3'd2, // when clk = 25~ 50MHz , set CLK_DIV = 3'd2,
// when clk = 50~100MHz , set CLK_DIV = 3'd3, // when clk = 50~100MHz , set CLK_DIV = 3'd3,