mirror of
https://github.com/WangXuan95/FPGA-SDcard-Reader.git
synced 2025-01-13 20:02:53 +08:00
134 lines
4.1 KiB
Systemverilog
134 lines
4.1 KiB
Systemverilog
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//--------------------------------------------------------------------------------------------------------
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// Module : sdcmd_ctrl
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// Type : synthesizable, IP's sub module
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// Standard: SystemVerilog 2005 (IEEE1800-2005)
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// Function: sdcmd signal control,
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// instantiated by sd_reader
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//--------------------------------------------------------------------------------------------------------
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module sdcmd_ctrl (
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input wire rstn,
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input wire clk,
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// SDcard signals (sdclk and sdcmd)
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output reg sdclk,
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inout sdcmd,
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// config clk freq
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input wire [15:0] clkdiv,
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// user input signal
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input wire start,
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input wire [15:0] precnt,
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input wire [ 5:0] cmd,
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input wire [31:0] arg,
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// user output signal
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output reg busy,
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output reg done,
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output reg timeout,
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output reg syntaxe,
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output wire [31:0] resparg
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);
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initial {busy, done, timeout, syntaxe} = '0;
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initial sdclk = '0;
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localparam [7:0] TIMEOUT = 8'd250;
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reg sdcmdoe = 1'b0;
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reg sdcmdout = 1'b1;
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// sdcmd tri-state driver
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assign sdcmd = sdcmdoe ? sdcmdout : 1'bz;
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wire sdcmdin = sdcmdoe ? 1'b1 : sdcmd;
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function automatic logic [6:0] CalcCrc7(input logic [6:0] crc, input logic inbit);
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return {crc[5:0],crc[6]^inbit} ^ {3'b0,crc[6]^inbit,3'b0};
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endfunction
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reg [ 5:0] req_cmd = '0; // request[45:40]
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reg [31:0] req_arg = '0; // request[39: 8]
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reg [ 6:0] req_crc = '0; // request[ 7: 1]
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wire [51:0] request = {6'b111101, req_cmd, req_arg, req_crc, 1'b1};
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struct packed {
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logic st;
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logic [ 5:0] cmd;
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logic [31:0] arg;
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} response = '0;
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assign resparg = response.arg;
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reg [17:0] clkdivr = '1;
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reg [17:0] clkcnt = '0;
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reg [15:0] cnt1 = '0;
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reg [ 5:0] cnt2 = '1;
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reg [ 7:0] cnt3 = '0;
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reg [ 7:0] cnt4 = '1;
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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{busy, done, timeout, syntaxe} <= '0;
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sdclk <= 1'b0;
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{sdcmdoe, sdcmdout} <= 2'b01;
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{req_cmd, req_arg, req_crc} <= '0;
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response <= '0;
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clkdivr <= '1;
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clkcnt <= '0;
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cnt1 <= '0;
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cnt2 <= '1;
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cnt3 <= '0;
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cnt4 <= '1;
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end else begin
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{done, timeout, syntaxe} <= '0;
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clkcnt <= ( clkcnt < {clkdivr[16:0],1'b1} ) ? clkcnt+18'd1 : '0;
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if (clkcnt == '0)
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clkdivr <= {2'h0, clkdiv} + 18'd1;
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if(clkcnt == clkdivr)
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sdclk <= 1'b0;
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else if(clkcnt == {clkdivr[16:0],1'b1} )
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sdclk <= 1'b1;
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if(~busy) begin
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if(start) busy <= '1;
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req_cmd <= cmd;
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req_arg <= arg;
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req_crc <= '0;
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cnt1 <= precnt;
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cnt2 <= 6'd51;
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cnt3 <= TIMEOUT;
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cnt4 <= 8'd134;
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end else if(done) begin
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busy <= '0;
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end else if( clkcnt == clkdivr) begin
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{sdcmdoe, sdcmdout} <= 2'b01;
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if (cnt1 != '0) begin
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cnt1 <= cnt1 - 16'd1;
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end else if(cnt2 != '1) begin
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cnt2 <= cnt2 - 6'd1;
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{sdcmdoe, sdcmdout} <= {1'b1, request[cnt2]};
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if(cnt2>=8 && cnt2<48) req_crc <= CalcCrc7(req_crc, request[cnt2]);
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end
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end else if( clkcnt == {clkdivr[16:0],1'b1} && cnt1=='0 && cnt2=='1 ) begin
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if(cnt3 != '0) begin
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cnt3 <= cnt3 - 8'd1;
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if(~sdcmdin)
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cnt3 <= '0;
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else if(cnt3 == 8'd1)
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{done, timeout, syntaxe} <= 3'b110;
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end else if(cnt4 != '1) begin
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cnt4 <= cnt4 - 8'd1;
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if(cnt4 >= 8'd96)
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response <= {response[37:0], sdcmdin};
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if(cnt4 == '0) begin
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{done, timeout} <= 2'b10;
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syntaxe <= response.st || ((response.cmd!=req_cmd) && (response.cmd!='1) && (response.cmd!='0));
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end
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end
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end
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end
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endmodule
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