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32 lines
862 B
Verilog
32 lines
862 B
Verilog
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//--------------------------------------------------------------------------------------------------------
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// Module : clock_beat
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// Type : synthesizable, FPGA's top, IP's example design
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// Standard: Verilog 2001 (IEEE1364-2001)
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// Function: When clk runs, beat signal will blink
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//--------------------------------------------------------------------------------------------------------
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module clock_beat # (
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parameter CLK_FREQ = 50000000, // Unit:Hz
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parameter BEAT_FREQ = 5 // Unit:Hz
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) (
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input wire clk,
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output reg beat
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);
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localparam CYCLES = (CLK_FREQ / 2 / BEAT_FREQ);
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reg [31:0] count = 0;
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initial beat = 1'b0;
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always @ (posedge clk)
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if ( count < (CYCLES-1) ) begin
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count <= count + 1;
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end else begin
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count <= 0;
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beat <= ~beat;
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end
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endmodule
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