mirror of
https://github.com/WangXuan95/FTDI-245fifo-interface.git
synced 2025-01-14 06:42:52 +08:00
139 lines
6.6 KiB
Verilog
139 lines
6.6 KiB
Verilog
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//--------------------------------------------------------------------------------------------------------
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// Module : fpga_top_ft232h_rx_crc
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// Type : synthesizable, FPGA's top, IP's example design
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// Standard: Verilog 2001 (IEEE1364-2001)
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// Function: an example of ftdi_245fifo_top
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// the pins of this module should connect to FT600 chip
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// This design will receive a data block from FTDI chip, and calculate its CRC.
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// When meeting 0xFF, it thinks that the data block ends, and then send the block's CRC to FTDI chip.
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//--------------------------------------------------------------------------------------------------------
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module fpga_top_ft232h_rx_crc (
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input wire clk, // main clock, connect to on-board crystal oscillator
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output wire [ 3:0] LED,
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// USB2.0 HS (FT232H chip) ------------------------------------------------------------
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//output wire ftdi_resetn, // to FT232H's pin34 (RESET#) , !!!!!! UnComment this line if this signal is connected to FPGA !!!!!!
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//output wire ftdi_pwrsav, // to FT232H's pin31 (PWRSAV#), !!!!!! UnComment this line if this signal is connected to FPGA !!!!!!
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//output wire ftdi_siwu, // to FT232H's pin28 (SIWU#) , !!!!!! UnComment this line if this signal is connected to FPGA !!!!!!
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input wire ftdi_clk, // to FT232H's pin29 (CLKOUT)
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input wire ftdi_rxf_n, // to FT232H's pin21 (RXF#)
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input wire ftdi_txe_n, // to FT232H's pin25 (TXE#)
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output wire ftdi_oe_n, // to FT232H's pin30 (OE#)
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output wire ftdi_rd_n, // to FT232H's pin26 (RD#)
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output wire ftdi_wr_n, // to FT232H's pin27 (WR#)
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inout [ 7:0] ftdi_data // to FT232H's pin20~13 (ADBUS7~ADBUS0)
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);
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//assign ftdi_resetn = 1'b1; // 1=normal operation , !!!!!! UnComment this line if this signal is connected to FPGA !!!!!!
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//assign ftdi_pwrsav = 1'b1; // 1=normal operation , !!!!!! UnComment this line if this signal is connected to FPGA !!!!!!
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//assign ftdi_siwu = 1'b1; // 1=send immidiently , !!!!!! UnComment this line if this signal is connected to FPGA !!!!!!
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//-----------------------------------------------------------------------------------------------------------------------------
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// user AXI-stream signals (loopback)
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//-----------------------------------------------------------------------------------------------------------------------------
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localparam RX_AXIS_EW = 1;
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wire rx_tready;
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wire rx_tvalid;
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wire [(8<<RX_AXIS_EW)-1:0] rx_tdata;
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wire [(1<<RX_AXIS_EW)-1:0] rx_tkeep;
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wire tx_tready;
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wire tx_tvalid;
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wire [ 31:0] tx_tdata;
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//-----------------------------------------------------------------------------------------------------------------------------
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// FTDI USB chip's 245fifo mode controller
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//-----------------------------------------------------------------------------------------------------------------------------
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ftdi_245fifo_top #(
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.TX_EW ( 2 ), // TX data stream width, 0=8bit, 1=16bit, 2=32bit, 3=64bit, 4=128bit ...
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.TX_EA ( 8 ), // TX FIFO depth = 2^TX_AEXP = 2^10 = 1024
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.RX_EW ( RX_AXIS_EW ), // RX data stream width, 0=8bit, 1=16bit, 2=32bit, 3=64bit, 4=128bit ...
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.RX_EA ( 10 ), // RX FIFO depth = 2^RX_AEXP = 2^10 = 1024
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.CHIP_TYPE ( "FTx232H" )
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) u_ftdi_245fifo_top (
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.rstn_async ( 1'b1 ),
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.tx_clk ( clk ),
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.tx_tready ( tx_tready ),
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.tx_tvalid ( tx_tvalid ),
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.tx_tdata ( tx_tdata ),
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.tx_tkeep ( 4'b1111 ),
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.tx_tlast ( 1'b1 ),
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.rx_clk ( clk ),
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.rx_tready ( rx_tready ),
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.rx_tvalid ( rx_tvalid ),
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.rx_tdata ( rx_tdata ),
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.rx_tkeep ( rx_tkeep ),
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.rx_tlast ( ),
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.ftdi_clk ( ftdi_clk ),
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.ftdi_rxf_n ( ftdi_rxf_n ),
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.ftdi_txe_n ( ftdi_txe_n ),
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.ftdi_oe_n ( ftdi_oe_n ),
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.ftdi_rd_n ( ftdi_rd_n ),
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.ftdi_wr_n ( ftdi_wr_n ),
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.ftdi_data ( ftdi_data ),
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.ftdi_be ( ) // FT232H do not have BE signals
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);
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//-----------------------------------------------------------------------------------------------------------------------------
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//
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//-----------------------------------------------------------------------------------------------------------------------------
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rx_calc_crc #(
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.IEW ( RX_AXIS_EW )
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) u_rx_calc_crc (
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.rstn ( 1'b1 ),
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.clk ( clk ),
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.i_tready ( rx_tready ),
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.i_tvalid ( rx_tvalid ),
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.i_tdata ( rx_tdata ),
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.i_tkeep ( rx_tkeep ),
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.o_tready ( tx_tready ),
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.o_tvalid ( tx_tvalid ),
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.o_tdata ( tx_tdata )
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);
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//-----------------------------------------------------------------------------------------------------------------------------
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// show the low 3-bit of the last received data on LED
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//-----------------------------------------------------------------------------------------------------------------------------
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reg [2:0] tdata_d = 3'h0;
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always @ (posedge clk)
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if (rx_tvalid)
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tdata_d <= rx_tdata[2:0];
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assign LED[2:0] = tdata_d;
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//-----------------------------------------------------------------------------------------------------------------------------
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// if ftdi_clk continuous run, then beat will blink. The function of this module is to observe whether ftdi_clk is running
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//-----------------------------------------------------------------------------------------------------------------------------
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clock_beat # (
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.CLK_FREQ ( 60000000 ),
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.BEAT_FREQ ( 5 )
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) u_ftdi_clk_beat (
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.clk ( ftdi_clk ),
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.beat ( LED[3] )
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);
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endmodule
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