mirror of
https://github.com/WangXuan95/FTDI-245fifo-interface.git
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96 lines
2.8 KiB
Verilog
96 lines
2.8 KiB
Verilog
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//--------------------------------------------------------------------------------------------------------
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// Module : tx_specified_len
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// Type : synthesizable
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// Standard: Verilog 2001 (IEEE1364-2001)
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// Function: receive 4 bytes from AXI-stream slave,
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// then regard the 4 bytes as a length, send length of bytes on AXI-stream master
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// this module will called by fpga_top_ft600_tx_mass.v or fpga_top_ft232h_tx_mass.v
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//--------------------------------------------------------------------------------------------------------
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module tx_specified_len (
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input wire rstn,
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input wire clk,
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// AXI-stream slave
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output wire i_tready,
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input wire i_tvalid,
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input wire [ 7:0] i_tdata,
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// AXI-stream master
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input wire o_tready,
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output wire o_tvalid,
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output wire [31:0] o_tdata,
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output wire [ 3:0] o_tkeep,
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output wire o_tlast
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);
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localparam [2:0] RX_BYTE0 = 3'd0,
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RX_BYTE1 = 3'd1,
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RX_BYTE2 = 3'd2,
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RX_BYTE3 = 3'd3,
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TX_DATA = 3'd4;
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reg [ 2:0] state = RX_BYTE0;
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reg [31:0] length = 0;
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always @ (posedge clk or negedge rstn)
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if (~rstn) begin
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state <= RX_BYTE0;
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length <= 0;
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end else begin
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case (state)
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RX_BYTE0 : if (i_tvalid) begin
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length[ 7: 0] <= i_tdata;
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state <= RX_BYTE1;
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end
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RX_BYTE1 : if (i_tvalid) begin
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length[15: 8] <= i_tdata;
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state <= RX_BYTE2;
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end
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RX_BYTE2 : if (i_tvalid) begin
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length[23:16] <= i_tdata;
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state <= RX_BYTE3;
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end
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RX_BYTE3 : if (i_tvalid) begin
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length[31:24] <= i_tdata;
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state <= TX_DATA;
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end
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default : // TX_DATA :
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if (o_tready) begin
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if (length >= 4) begin
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length <= length - 4;
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end else begin
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length <= 0;
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state <= RX_BYTE0;
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end
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end
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endcase
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end
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assign i_tready = (state != TX_DATA);
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assign o_tvalid = (state == TX_DATA);
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assign o_tdata = {length[7:0] - 8'd4,
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length[7:0] - 8'd3,
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length[7:0] - 8'd2,
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length[7:0] - 8'd1 };
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assign o_tkeep = (length>=4) ? 4'b1111 :
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(length==3) ? 4'b0111 :
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(length==2) ? 4'b0011 :
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(length==1) ? 4'b0001 :
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/*length==0*/ 4'b0000;
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assign o_tlast = (length>=4) ? 1'b0 : 1'b1;
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endmodule
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