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https://github.com/WangXuan95/FTDI-245fifo-interface.git
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27 lines
833 B
Verilog
27 lines
833 B
Verilog
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//--------------------------------------------------------------------------------------------------------
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// Module : resetn_sync
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// Type : synthesizable, IP's sub-module
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// Standard: Verilog 2001 (IEEE1364-2001)
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// Function: Synchronize the asynchronous reset signal to the local clock domain (asynchronous reset, synchronous release)
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// called by ftdi_245fifo.v
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//--------------------------------------------------------------------------------------------------------
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module resetn_sync (
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input wire rstn_async,
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input wire clk,
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output wire rstn
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);
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reg [3:0] rstn_shift = 4'd0;
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always @ (posedge clk or negedge rstn_async)
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if (~rstn_async)
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rstn_shift <= 4'd0;
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else
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rstn_shift <= {1'b1, rstn_shift[3:1]};
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assign rstn = rstn_shift[0];
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endmodule
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